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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 42/46] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
Date: Fri, 29 Jan 2021 11:00:08 +0000
Message-Id: <20210129110012.8660-43-peter.maydell@linaro.org>
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Now that the CMSDK APB watchdog uses its Clock input, it will
correctly respond when the system clock frequency is changed using
the RCC register on in the Stellaris board system registers. Test
that when the RCC register is written it causes the watchdog timer to
change speed.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Tested-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Message-id: 20210128114145.20536-22-peter.maydell@linaro.org
Message-id: 20210121190622.22000-22-peter.maydell@linaro.org
---
tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-=
watchdog-test.c
index 950f64c527b..2710cb17b86 100644
--- a/tests/qtest/cmsdk-apb-watchdog-test.c
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
@@ -15,6 +15,7 @@
*/
=20
#include "qemu/osdep.h"
+#include "qemu/bitops.h"
#include "libqtest-single.h"
=20
/*
@@ -31,6 +32,11 @@
#define WDOGMIS 0x14
#define WDOGLOCK 0xc00
=20
+#define SSYS_BASE 0x400fe000
+#define RCC 0x60
+#define SYSDIV_SHIFT 23
+#define SYSDIV_LENGTH 4
+
static void test_watchdog(void)
{
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0);
@@ -61,6 +67,50 @@ static void test_watchdog(void)
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0);
}
=20
+static void test_clock_change(void)
+{
+ uint32_t rcc;
+
+ /*
+ * Test that writing to the stellaris board's RCC register to
+ * change the system clock frequency causes the watchdog
+ * to change the speed it counts at.
+ */
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0);
+
+ writel(WDOG_BASE + WDOGCONTROL, 1);
+ writel(WDOG_BASE + WDOGLOAD, 1000);
+
+ /* Step to just past the 500th tick */
+ clock_step(80 * 500 + 1);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 500);
+
+ /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick =
*/
+ rcc =3D readl(SSYS_BASE + RCC);
+ g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), =3D=3D, =
0xf);
+ rcc =3D deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
+ writel(SSYS_BASE + RCC, rcc);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(40 * 500);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 1);
+
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 0);
+
+ /* VALUE reloads at following tick */
+ clock_step(41);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 1000);
+
+ /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
+ clock_step(40 * 500);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 500);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 1);
+ writel(WDOG_BASE + WDOGINTCLR, 0);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 1000);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0);
+}
+
int main(int argc, char **argv)
{
int r;
@@ -70,6 +120,8 @@ int main(int argc, char **argv)
qtest_start("-machine lm3s811evb");
=20
qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
+ qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change",
+ test_clock_change);
=20
r =3D g_test_run();
=20
--=20
2.20.1