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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/46] target/arm: Implement ID_PFR2
Date: Fri, 29 Jan 2021 10:59:27 +0000
Message-Id: <20210129110012.8660-2-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210120204400.1056582-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 1 +
target/arm/helper.c | 4 ++--
target/arm/kvm64.c | 2 ++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df0d6778330..d080239863c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -922,6 +922,7 @@ struct ARMCPU {
uint32_t id_mmfr4;
uint32_t id_pfr0;
uint32_t id_pfr1;
+ uint32_t id_pfr2;
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2ead3fcbdb..417777d4bed 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7662,11 +7662,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access =3D PL1_R, .type =3D ARM_CP_CONST,
.accessfn =3D access_aa64_tid3,
.resetvalue =3D 0 },
- { .name =3D "MVFR4_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64,
+ { .name =3D "ID_PFR2", .state =3D ARM_CP_STATE_BOTH,
.opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D =
4,
.access =3D PL1_R, .type =3D ARM_CP_CONST,
.accessfn =3D access_aa64_tid3,
- .resetvalue =3D 0 },
+ .resetvalue =3D cpu->isar.id_pfr2 },
{ .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D =
5,
.access =3D PL1_R, .type =3D ARM_CP_CONST,
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index f74bac24574..3c37fc4fb6a 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -578,6 +578,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *=
ahcf)
ARM64_SYS_REG(3, 0, 0, 1, 0));
err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
ARM64_SYS_REG(3, 0, 0, 1, 1));
+ err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
+ ARM64_SYS_REG(3, 0, 0, 3, 4));
err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
ARM64_SYS_REG(3, 0, 0, 1, 2));
err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
--=20
2.20.1