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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y2K1kNTbNOMvi2EpXTLd2ToPKEqAh/Wj79aMwJhopKA=; b=JIRT16NxMAt4jGsxudcY7nyUYMc7HdDT7Q62QSd21ojMk9pOd3VdjogA0Bfwddkrxt HOajJg++U+vgKEJejBe1Nub9Xf891Dx5c7HPfNPSpARM7nw2KrrTvnaOwI2Ck5sJz3uf 2MfB56EEp7a5RrepckUYmZcupE0EkyuD9PNvqOAL5BTqsjxy3zs5hFM2pIM2px3YQGjv 3x3EAPGV5aBS4Z5NxZm84WwmsNfMOA4U/ZdrUI/TpY1tqQ4dBRaRi28SUttMaPfYYTug DtRCtSABPS86wjglSopxQA9A+ygw1+buOOXQzKfHChTRJc6t0XIvaFf7iAaIpeU89ea7 lHIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y2K1kNTbNOMvi2EpXTLd2ToPKEqAh/Wj79aMwJhopKA=; b=H45WpsTaWqBRLPiBx9YGmTKMFIIwbeg9ui7lBz15jYkdSbpH59+2sAf1vRcZFDLh3q 2GW1hbQmavpfn9CM5VqUNgTpY54VCJ9wqGiwvOgAA126o96+s+yyKYsSkZXyoFqlsVJE z//wTzKEAWhIBuPqxQrtj5mGx2O1XWXhbnJGlVPCE2CO7dcgiU8at5VlyRkXvyjGjFGh CdXvyXQkLI8+rsPn2aYH5cHFsZdwUO99MS72CrSjPuD6N8Ac5TKVWQFSTO09qmiqQsSt 5NYUy8drVnMC/Whkmpze6nowsfNdiXB0QZCP59LAnTlG7BBrp2uoURGfW+n2Z24VV3kT LAJg== X-Gm-Message-State: AOAM531jEgzS+fMXkqg8kwD400MzSAIaFgyWPFb8O3U51JIpKFXC2TOR f2DxSxbqMHJsQXKbYk5kT7hXbg== X-Google-Smtp-Source: ABdhPJwZnFECUz1kYZpnn0kXBg33+nbhBxPQKXwu/gMKWDAkeLm35/td7OQ9snPlZo5OzIzPvr/6zw== X-Received: by 2002:a1c:df04:: with SMTP id w4mr8085586wmg.66.1611834118959; Thu, 28 Jan 2021 03:41:58 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/25] hw/arm/armsse: Wire up clocks Date: Thu, 28 Jan 2021 11:41:31 +0000 Message-Id: <20210128114145.20536-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Create two input clocks on the ARMSSE devices, one for the normal MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the appropriate devices. The old property-based clock frequency setting will remain in place until conversion is complete. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel Message-id: 20210121190622.22000-12-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 6 ++++++ hw/arm/armsse.c | 17 +++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 4860a793f4b..bfa1e79c4fe 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -37,6 +37,8 @@ * per-CPU identity and control register blocks * * QEMU interface: + * + Clock input "MAINCLK": clock for CPUs and most peripherals + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provi= ded * by the board model. * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock @@ -103,6 +105,7 @@ #include "hw/misc/armsse-mhu.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" +#include "hw/clock.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" #include "qom/object.h" @@ -209,6 +212,9 @@ struct ARMSSE { =20 uint32_t nsccfg; =20 + Clock *mainclk; + Clock *s32kclk; + /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index d2ba0459c44..4349ce9bfdb 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -21,6 +21,7 @@ #include "hw/arm/armsse.h" #include "hw/arm/boot.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" =20 /* Format of the System Information block SYS_CONFIG register */ typedef enum SysConfigFormat { @@ -241,6 +242,9 @@ static void armsse_init(Object *obj) assert(info->sram_banks <=3D MAX_SRAM_BANKS); assert(info->num_cpus <=3D SSE_MAX_CPUS); =20 + s->mainclk =3D qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); + s->s32kclk =3D qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); + memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 for (i =3D 0; i < info->num_cpus; i++) { @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) * map its upstream ends to the right place in the container. */ qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; } @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) &error_abort); =20 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; } @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) &error_abort); =20 qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq= ); + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; } @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) * 0x4002f000: S32K timer */ qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; } @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI"= , 0)); =20 qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; } @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ =20 qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk= _frq); + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; } @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); =20 qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_= frq); + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; } @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uin= t32_t address, =20 static const VMStateDescription armsse_vmstate =3D { .name =3D "iotkit", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(mainclk, ARMSSE), + VMSTATE_CLOCK(s32kclk, ARMSSE), VMSTATE_UINT32(nsccfg, ARMSSE), VMSTATE_END_OF_LIST() } --=20 2.20.1