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Thu, 28 Jan 2021 09:28:23 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Peter Maydell Subject: [PATCH v14 07/22] cpu: Move debug_excp_handler to tcg_ops Date: Thu, 28 Jan 2021 10:27:59 +0100 Message-Id: <20210128092814.8676-8-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210128092814.8676-1-cfontana@suse.de> References: <20210128092814.8676-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , qemu-devel@nongnu.org, Roman Bolshakov , Alistair Francis , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index aa464c9633..a0e040c617 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -116,6 +116,8 @@ typedef struct TcgCpuOperations { bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); + /** @debug_excp_handler: Callback for handling debug exceptions */ + void (*debug_excp_handler)(CPUState *cpu); =20 } TcgCpuOperations; #endif /* CONFIG_TCG */ @@ -161,7 +163,6 @@ typedef struct TcgCpuOperations { * @gdb_write_register: Callback for letting GDB write a register. * @debug_check_watchpoint: Callback: return true if the architectural * watchpoint whose address has matched should really fire. - * @debug_excp_handler: Callback for handling debug exceptions. * @write_elf64_note: Callback for writing a CPU-specific ELF note to a * 64-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF @@ -224,7 +225,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); - void (*debug_excp_handler)(CPUState *cpu); =20 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 953f050698..e7e54fd75d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -512,8 +512,8 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } } =20 - if (cc->debug_excp_handler) { - cc->debug_excp_handler(cpu); + if (cc->tcg_ops.debug_excp_handler) { + cc->tcg_ops.debug_excp_handler(cpu); } } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 27a16c1950..66ac210b0c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2280,7 +2280,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; - cc->debug_excp_handler =3D arm_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 85b69224a9..6c1ebbdcc6 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -67,6 +67,6 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.initialize =3D tcg_x86_init; cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->debug_excp_handler =3D breakpoint_handler; + cc->tcg_ops.debug_excp_handler =3D breakpoint_handler; #endif } diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 76dc728858..bbe1405e32 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -235,7 +235,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; - cc->debug_excp_handler =3D lm32_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D lm32_debug_excp_handler; cc->disas_set_info =3D lm32_cpu_disas_set_info; cc->tcg_ops.initialize =3D lm32_translate_init; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index ceee62ddca..8ade66178e 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -509,7 +509,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->write_elf64_note =3D s390_cpu_write_elf64_note; #ifdef CONFIG_TCG cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; - cc->debug_excp_handler =3D s390x_cpu_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D s390x_cpu_debug_excp_handler; cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif #endif diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e764dbeb73..b6f13ceb32 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -207,7 +207,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif - cc->debug_excp_handler =3D xtensa_breakpoint_handler; + cc->tcg_ops.debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->tcg_ops.initialize =3D xtensa_translate_init; dc->vmsd =3D &vmstate_xtensa_cpu; --=20 2.26.2