From nobody Tue Feb 10 11:12:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1611826650; cv=none; d=zohomail.com; s=zohoarc; b=KOFP55iyVLsbiJ3BOrjmsjv4ImTijCaHlVl4YlNqCTSe0mgp+HBf9E+SwjJY4l/1XIjcJuChBHOU37bP73KqCnXJKuxdzGDOmpgC50wCPhVuU2qOwr5zUZjE3gpbBHVzJLGPOg7ueLEaX08OfnXoUu/TsMJG+OkT0eXQRDiUFj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611826650; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zGM7FwsRMnpr9UEcK3IbwD0o+wX3d862RA1C4LdNoWQ=; b=PZQLqfiUgm4HGRMZ1XAVgcnCT1jsJXBFzIUvGiFdg1Bw3TvaCjEl7VgIEkIAEHVcwdyNfRL/67Xo3Mn6Q2tLPUvx2jA/UJbtTENDUiorlwatgI7Q09loAA7oSNdli2hxSmCwAAZG/OPIPmSZcuOdDxLBS/20V3Y+MjGmzenozxE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611826650038267.7087312422873; Thu, 28 Jan 2021 01:37:30 -0800 (PST) Received: from localhost ([::1]:47362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l53jz-0002OY-WE for importer@patchew.org; Thu, 28 Jan 2021 04:37:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l53bb-0001X5-8i for qemu-devel@nongnu.org; Thu, 28 Jan 2021 04:28:47 -0500 Received: from mx2.suse.de ([195.135.220.15]:38140) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l53bX-00020H-Nv for qemu-devel@nongnu.org; Thu, 28 Jan 2021 04:28:47 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 70633AC97; Thu, 28 Jan 2021 09:28:29 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Peter Maydell Subject: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass Date: Thu, 28 Jan 2021 10:28:10 +0100 Message-Id: <20210128092814.8676-19-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210128092814.8676-1-cfontana@suse.de> References: <20210128092814.8676-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , qemu-devel@nongnu.org, Roman Bolshakov , Alistair Francis , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. Add the field before tcg_ops, and mark tcg_ops as needing to be last in the struct until we rework this further in a later patch. Signed-off-by: Claudio Fontana --- include/hw/core/accel-cpu.h | 35 +++++++++++++++++++++++++++++ include/hw/core/cpu.h | 1 + accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++ MAINTAINERS | 1 + 4 files changed, 81 insertions(+) create mode 100644 include/hw/core/accel-cpu.h diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h new file mode 100644 index 0000000000..246b3e2fcb --- /dev/null +++ b/include/hw/core/accel-cpu.h @@ -0,0 +1,35 @@ +/* + * Accelerator interface, specializes CPUClass + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_CPU_H +#define ACCEL_CPU_H + +/* + * these defines cannot be in cpu.h, because we are using + * CPU_RESOLVING_TYPE here. + * Use this header to define your accelerator-specific + * cpu-specific accelerator interfaces. + */ + +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) +typedef struct AccelCPUClass AccelCPUClass; +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) + +typedef struct AccelCPUClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + void (*cpu_class_init)(CPUClass *cc); + void (*cpu_instance_init)(CPUState *cpu); + void (*cpu_realizefn)(CPUState *cpu, Error **errp); +} AccelCPUClass; + +#endif /* ACCEL_CPU_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500e2c4fce..81153c349f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -190,6 +190,7 @@ struct CPUClass { /* Keep non-pointer data at the end to minimize holes. */ int gdb_num_core_regs; bool gdb_stop_before_watchpoint; + struct AccelCPUClass *accel_cpu; =20 /* * NB: this should be covered by CONFIG_TCG, but it is unsafe to do it= here, diff --git a/accel/accel-common.c b/accel/accel-common.c index 6b59873419..9901b0531c 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -26,6 +26,9 @@ #include "qemu/osdep.h" #include "qemu/accel.h" =20 +#include "cpu.h" +#include "hw/core/accel-cpu.h" + #ifndef CONFIG_USER_ONLY #include "accel-softmmu.h" #endif /* !CONFIG_USER_ONLY */ @@ -46,16 +49,57 @@ AccelClass *accel_find(const char *opt_name) return ac; } =20 +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque) +{ + CPUClass *cc =3D CPU_CLASS(klass); + AccelCPUClass *accel_cpu =3D opaque; + + cc->accel_cpu =3D accel_cpu; + if (accel_cpu->cpu_class_init) { + accel_cpu->cpu_class_init(cc); + } +} + +/* initialize the arch-specific accel CpuClass interfaces */ +static void accel_init_cpu_interfaces(AccelClass *ac) +{ + const char *ac_name; /* AccelClass name */ + char *acc_name; /* AccelCPUClass name */ + ObjectClass *acc; /* AccelCPUClass */ + + ac_name =3D object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name !=3D NULL); + + acc_name =3D g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE); + acc =3D object_class_by_name(acc_name); + g_free(acc_name); + + if (acc) { + object_class_foreach(accel_init_cpu_int_aux, + CPU_RESOLVING_TYPE, false, acc); + } +} + void accel_init_interfaces(AccelClass *ac) { #ifndef CONFIG_USER_ONLY accel_init_ops_interfaces(ac); #endif /* !CONFIG_USER_ONLY */ + + accel_init_cpu_interfaces(ac); } =20 +static const TypeInfo accel_cpu_type =3D { + .name =3D TYPE_ACCEL_CPU, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelCPUClass), +}; + static void register_accel_types(void) { type_register_static(&accel_type); + type_register_static(&accel_cpu_type); } =20 type_init(register_accel_types); diff --git a/MAINTAINERS b/MAINTAINERS index 4cc8d9e502..1a83b60312 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -440,6 +440,7 @@ R: Paolo Bonzini S: Maintained F: include/qemu/accel.h F: include/sysemu/accel-ops.h +F: include/hw/core/accel-cpu.h F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs --=20 2.26.2