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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id k5sm367349ljg.119.2021.01.26.23.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jan 2021 23:48:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AiuGvTPGKFpIhZ2vJD8la6tRAd3TGUEQyGxMVtg+XwA=; b=htCf/CAxYuGWVrekib6DZg5fchDalAvItjoTTZVvSnczRLGSjwMG3FCPpf2bLZeJCR 26RiXer0JLg97Z9OJJfxPWPtDCLcOt7B5yPDi5r7WkLjoEU944cQrHfUTpwRg4AM3tW8 NRLyvS7Zxb7p8+aaygR4I3joo8g/Pj1r5zRycVDmqMWH+GxefIRqSGYVqFX9ICeCgY5O nOwN3/1ix/DQB0VkZKVws4+/BiS10Xs9NzeFHm9bghQ1E9k6cKkDg2V4evp6XzUOzLxv LtgRaCdewyPE4cbVbq6yJv2Et0ePk2f/N+MBbyyGTupQj+AZNNw2ge6bRo+6MjoOe6sv CPEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AiuGvTPGKFpIhZ2vJD8la6tRAd3TGUEQyGxMVtg+XwA=; b=gCc1knsFiFdrvMWpZQDvZhpOpeSmIs4QWeeaDo8GH1mvJV4kmJXtN/1SnXWAULVZgV 8LEld5kOMDacRIqu8t9tUfl+hKdDBAfggGtp4CjcYvXndaZta1LU4TziIaNNBvVnLI3K SR8xauICrdMI+1nWoUnmwRsA9UydTp6t1Z9duTfjHuobBvZ0B4MIKhTpTnu6pkoHS9ps NZqH4jTtw3O9GAxZiTo9vfO74MSQAR1Z66/vYZ6Yr6XqEhPxIwAiDjVQDtM4ja44obdr ov5uI5M0iEJKyP0/vKIXUA21QPOAlWgaeNhbhlfX0lXCr1z//miD/+WArUJZDoNwXX34 LH2g== X-Gm-Message-State: AOAM532HaypUH+ml3rhScQuTMCvN7zT/DoiRcxLe7TmSfpcwHSTyaFQR LPIxUm5icBE6pIw7TmREF5PwGcI1Pf0= X-Google-Smtp-Source: ABdhPJw2yx476ozhcXKNfKvt/+Xim1Hlxt1pGi8IVQqOHA/MPQoKlWKatFrVcxBsf930ZhvBRX5bRQ== X-Received: by 2002:a05:651c:233:: with SMTP id z19mr4827313ljn.486.1611733732967; Tue, 26 Jan 2021 23:48:52 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 1/3] target/microblaze: Add use-non-secure property Date: Wed, 27 Jan 2021 08:48:48 +0100 Message-Id: <20210127074850.1886235-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210127074850.1886235-1-edgar.iglesias@gmail.com> References: <20210127074850.1886235-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, joe.komlodi@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Joe Komlodi This property is used to control the security of the following interfaces on MicroBlaze: M_AXI_DP - data interface M_AXI_IP - instruction interface M_AXI_DC - dcache interface M_AXI_IC - icache interface It works by enabling or disabling the use of the non_secure[3:0] signals. Interfaces and their corresponding values are taken from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-= vivado-microblaze-ref.pdf page 153. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-Id: <1611274735-303873-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 11 ++++++++++ target/microblaze/cpu.c | 46 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c1c264199f..199cfb02d6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -233,6 +233,12 @@ typedef struct CPUMBState CPUMBState; =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 +/* use-non-secure property masks */ +#define USE_NON_SECURE_M_AXI_DP_MASK 0x1 +#define USE_NON_SECURE_M_AXI_IP_MASK 0x2 +#define USE_NON_SECURE_M_AXI_DC_MASK 0x4 +#define USE_NON_SECURE_M_AXI_IC_MASK 0x8 + struct CPUMBState { uint32_t bvalue; /* TCG temporary, only valid during a TB */ uint32_t btarget; /* Full resolved branch destination */ @@ -316,6 +322,7 @@ typedef struct { bool use_msr_instr; bool use_pcmp_instr; bool use_mmu; + uint8_t use_non_secure; bool dcache_writeback; bool endi; bool dopb_bus_exception; @@ -337,6 +344,10 @@ struct MicroBlazeCPU { CPUState parent_obj; =20 /*< public >*/ + bool ns_axi_dp; + bool ns_axi_ip; + bool ns_axi_dc; + bool ns_axi_ic; =20 CPUNegativeOffsetState neg; CPUMBState env; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c8e754cfb1..accfb23a4f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -98,6 +98,38 @@ static bool mb_cpu_has_work(CPUState *cs) } =20 #ifndef CONFIG_USER_ONLY +static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu =3D opaque; + bool en =3D cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; + + cpu->ns_axi_dp =3D level & en; +} + +static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu =3D opaque; + bool en =3D cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; + + cpu->ns_axi_ip =3D level & en; +} + +static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu =3D opaque; + bool en =3D cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; + + cpu->ns_axi_dc =3D level & en; +} + +static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu =3D opaque; + bool en =3D cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; + + cpu->ns_axi_ic =3D level & en; +} + static void microblaze_cpu_set_irq(void *opaque, int irq, int level) { MicroBlazeCPU *cpu =3D opaque; @@ -248,6 +280,10 @@ static void mb_cpu_initfn(Object *obj) #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); #endif } =20 @@ -277,6 +313,16 @@ static Property mb_properties[] =3D { DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, tr= ue), DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, = true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), + /* + * use-non-secure enables/disables the use of the non_secure[3:0] sign= als. + * It is a bitfield where 1 =3D non-secure for the following bits and = their + * corresponding interfaces: + * 0x1 - M_AXI_DP + * 0x2 - M_AXI_IP + * 0x4 - M_AXI_DC + * 0x8 - M_AXI_IC + */ + DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure,= 0), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeba= ck, false), DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), --=20 2.25.1 From nobody Mon Feb 9 16:54:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 2/3] target/microblaze: use MMUAccessType instead of int in mmu_translate Date: Wed, 27 Jan 2021 08:48:49 +0100 Message-Id: <20210127074850.1886235-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210127074850.1886235-1-edgar.iglesias@gmail.com> References: <20210127074850.1886235-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, joe.komlodi@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Using MMUAccessType makes it more clear what the variable's use is. No functional change. Signed-off-by: Joe Komlodi Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-Id: <1611274735-303873-3-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.h | 2 +- target/microblaze/mmu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 09e4075739..b6b4b9ad60 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -84,7 +84,7 @@ typedef struct { } MicroBlazeMMULookup; =20 unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, - target_ulong vaddr, int rw, int mmu_idx); + target_ulong vaddr, MMUAccessType rw, int mmu_i= dx); uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); void mmu_init(MicroBlazeMMU *mmu); diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 1e426963ba..cc40f275ea 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -74,7 +74,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int = newpid) =20 /* rw - 0 =3D read, 1 =3D write, 2 =3D fetch. */ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, - target_ulong vaddr, int rw, int mmu_idx) + target_ulong vaddr, MMUAccessType rw, int mmu_i= dx) { MicroBlazeMMU *mmu =3D &cpu->env.mmu; unsigned int i, hit =3D 0; --=20 2.25.1 From nobody Mon Feb 9 16:54:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1611733980; cv=none; d=zohomail.com; s=zohoarc; b=QGuflg69g9hhbzKgZUdP5YR7iKl3Fg0puhrIxVwzRBFatiQBtZIwRI5bic7MZJUyXtnaE6XW712pjBrJVNZ/dln3xG4UVyllpasrf+brgwRS9QxYFUCGHYKn89XcfiigaPLCmtCL+QCaNssHAmeFojEsK4SKbYGxGnllODIm4ew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611733980; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yIgMDih2Mx0+rtvGNh5fCAvI77wGf0Y6e4dfvNoICtY=; b=L+Q4oh63s2oZtOxJZwwzx8s+1tHTMfsp5jIDkydGNjznU5yvT1wE85DMVXDRtF1VfxnE4WMRnTgT97+GXbcdyST/ikb1IoYx/NhfxS+hiak2Qg9ci8hVXvnPwhIWUFOUISmMwzsJiKxrH2Rz26n/NG/KeT/BoWe9uouJ36JJKm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611733980629637.9867085341002; Tue, 26 Jan 2021 23:53:00 -0800 (PST) Received: from localhost ([::1]:34012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l4fdL-0001UN-FH for importer@patchew.org; Wed, 27 Jan 2021 02:52:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60254) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4fZS-0006OI-8S for qemu-devel@nongnu.org; Wed, 27 Jan 2021 02:48:58 -0500 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]:45407) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4fZQ-0008Gu-KT for qemu-devel@nongnu.org; Wed, 27 Jan 2021 02:48:57 -0500 Received: by mail-lj1-x234.google.com with SMTP id e18so946960lja.12 for ; Tue, 26 Jan 2021 23:48:56 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. 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Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 3/3] target/microblaze: Add security attributes on memory transactions Date: Wed, 27 Jan 2021 08:48:50 +0100 Message-Id: <20210127074850.1886235-4-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210127074850.1886235-1-edgar.iglesias@gmail.com> References: <20210127074850.1886235-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, joe.komlodi@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Using the cfg.use_non_secure bitfield and the MMU access type, we can deter= mine if the access should be secure or not. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-Id: <1611274735-303873-4-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 3 ++- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 26 +++++++++++++++++++++++--- 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 199cfb02d6..e4bba8a755 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -361,7 +361,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vad= dr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index accfb23a4f..d5e8bfe11f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -375,7 +375,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D mb_cpu_transaction_failed; - cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; + cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index cda14a14be..20dbd67313 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -46,6 +46,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int si= ze, =20 #else /* !CONFIG_USER_ONLY */ =20 +static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, + MMUAccessType access_type) +{ + if (access_type =3D=3D MMU_INST_FETCH) { + return !cpu->ns_axi_ip; + } else { + return !cpu->ns_axi_dp; + } +} + bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -55,12 +65,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, MicroBlazeMMULookup lu; unsigned int hit; int prot; + MemTxAttrs attrs =3D {}; + + attrs.secure =3D mb_cpu_access_is_secure(cpu, access_type); =20 if (mmu_idx =3D=3D MMU_NOMMU_IDX) { /* MMU disabled or not available. */ address &=3D TARGET_PAGE_MASK; prot =3D PAGE_BITS; - tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE= ); + tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } =20 @@ -71,7 +85,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int siz= e, =20 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x prot=3D= %x\n", mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } =20 @@ -230,7 +245,8 @@ void mb_cpu_do_interrupt(CPUState *cs) } } =20 -hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; @@ -239,6 +255,10 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) int mmu_idx =3D cpu_mmu_index(env, false); unsigned int hit; =20 + /* Caller doesn't initialize */ + *attrs =3D (MemTxAttrs) {}; + attrs->secure =3D mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); + if (mmu_idx !=3D MMU_NOMMU_IDX) { hit =3D mmu_translate(cpu, &lu, addr, 0, 0); if (hit) { --=20 2.25.1