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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id k10sm12471076pfk.0.2021.01.25.22.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 22:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lPgVdXOd8dKlKEB1hV4iW/elZmTi6Kdti2t1vuxXyCY=; b=Kr9C7OR2d/F8dxYmk6VlFDwmz82/7516dde52C9GtQBFoWhRWivTbn8ggkXqu0M6DU jMjpwZkPYcncT0LaVQYRXb2Vy12NdLQAby3Bee4DGiJ2ua2c19Hhu5s5IbjUhqZb1pYG zQrvQCNUUIuBnolz/GqHYRrcDg7PHmyKzxWvN0ZKdPsAh8NAGlDzSpFbaAPP+H98tdBg SuaJOHnmJLyBdsI0qIvjSLW2oqum1a7STX/vV2XW0jZu+Rxa02DZ3JwSjj0Pezn3vHLi vBdDeQaUD0pPL+k1iHviaUlbHmogZ11hAaNIjBMS7VRrh5uuTDu8mN3uoJoxH2rE7eDa DntA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lPgVdXOd8dKlKEB1hV4iW/elZmTi6Kdti2t1vuxXyCY=; b=oxQhh7Fcik3kGwz4j1bNPFFMrG+27cFu0J4YS0992Uh5Z5weaKIte1wqR0yTr0kRkg eEhCc3Anun5iF7gIvXKN0zHshV5wC2uZr3aRmoPZilaw/epGF9Fy7c67uWkcz+jk5To7 imFDUEP67tBlCWq07K8SJi6uZhbAgMHh5c7YRmcbhBgmnOR9ptBaBvn6emUlvMrhhuO0 ePDUwLqwQx/UIbLisHSIrXk1E+0dAjFXuDnH0P8xFx6Ofw2MQeB77Sq1AdbtdeSNN84U eQErf8rdNOLQafWKhRIJxLYHN1N3IYer8AEZAdF7d/QQPAesQSEWQBgCnF9xGDv+/pAJ YUfg== X-Gm-Message-State: AOAM530CwJpUFge5QVX4zJgum4aMWZkPM45SW8JN7fomg5dTwH1u9Cym lxxdkdjrIXfCpohX6TaDeVM= X-Google-Smtp-Source: ABdhPJxLLezv+bV5vWwozjpqqjCZOWQrvviS4iRNAFBQ48L79w05FZhZ5EaAk5uZSq5Q4WkeUP2sWw== X-Received: by 2002:a62:7694:0:b029:1b9:8d43:95af with SMTP id r142-20020a6276940000b02901b98d4395afmr3952293pfc.2.1611640826616; Mon, 25 Jan 2021 22:00:26 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support Date: Tue, 26 Jan 2021 13:59:59 +0800 Message-Id: <20210126060007.12904-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210126060007.12904-1-bmeng.cn@gmail.com> References: <20210126060007.12904-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds the ISSI SPI flash support. The number of dummy cycles in fast read, fast read dual output and fast read quad output commands is currently using the default 8. Likewise, the same default value is used for fast read dual/quad I/O command. Per the datasheet [1], the number of dummy cycles is configurable, but this is not modeled at present. For flash whose size is larger than 16 MiB, the sequence of 3-byte address along with EXTADD bit in the bank address register (BAR) is not supported. We assume that guest software always uses op codes with 4-byte address sequence. Fortunately, this is the case for both U-Boot and Linux spi-nor drivers. QPI (Quad Peripheral Interface) that supports 2-cycle instruction has different default values for dummy cycles of fast read family commands, and is unsupported at the time being. [1] http://www.issi.com/WW/pdf/25LP-WP256.pdf Signed-off-by: Bin Meng Acked-by: Alistair Francis --- (no changes since v2) Changes in v2: - Mention QPI (Quad Peripheral Interface) mode is not supported hw/block/m25p80.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index b744a58d1c..217c130f56 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -412,6 +412,7 @@ typedef enum { MAN_NUMONYX, MAN_WINBOND, MAN_SST, + MAN_ISSI, MAN_GENERIC, } Manufacturer; =20 @@ -487,6 +488,8 @@ static inline Manufacturer get_man(Flash *s) return MAN_MACRONIX; case 0xBF: return MAN_SST; + case 0x9D: + return MAN_ISSI; default: return MAN_GENERIC; } @@ -706,6 +709,9 @@ static void complete_collecting_data(Flash *s) case MAN_SPANSION: s->quad_enable =3D !!(s->data[1] & 0x02); break; + case MAN_ISSI: + s->quad_enable =3D extract32(s->data[0], 6, 1); + break; case MAN_MACRONIX: s->quad_enable =3D extract32(s->data[0], 6, 1); if (s->len > 1) { @@ -895,6 +901,19 @@ static void decode_fast_read_cmd(Flash *s) SPANSION_DUMMY_CLK_LEN ); break; + case MAN_ISSI: + /* + * The Fast Read instruction code is followed by address bytes and + * dummy cycles, transmitted via the SI line. + * + * The number of dummy cycles is configurable but this is currently + * unmodeled, hence the default value 8 is used. + * + * QPI (Quad Peripheral Interface) mode has different default value + * of dummy cycles, but this is unsupported at the time being. + */ + s->needed_bytes +=3D 1; + break; default: break; } @@ -934,6 +953,16 @@ static void decode_dio_read_cmd(Flash *s) break; } break; + case MAN_ISSI: + /* + * The Fast Read Dual I/O instruction code is followed by address = bytes + * and dummy cycles, transmitted via the IO1 and IO0 line. + * + * The number of dummy cycles is configurable but this is currently + * unmodeled, hence the default value 4 is used. + */ + s->needed_bytes +=3D 1; + break; default: break; } @@ -974,6 +1003,19 @@ static void decode_qio_read_cmd(Flash *s) break; } break; + case MAN_ISSI: + /* + * The Fast Read Quad I/O instruction code is followed by address = bytes + * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 lin= e. + * + * The number of dummy cycles is configurable but this is currently + * unmodeled, hence the default value 6 is used. + * + * QPI (Quad Peripheral Interface) mode has different default value + * of dummy cycles, but this is unsupported at the time being. + */ + s->needed_bytes +=3D 3; + break; default: break; } @@ -1132,7 +1174,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) =20 case RDSR: s->data[0] =3D (!!s->write_enable) << 1; - if (get_man(s) =3D=3D MAN_MACRONIX) { + if (get_man(s) =3D=3D MAN_MACRONIX || get_man(s) =3D=3D MAN_ISSI) { s->data[0] |=3D (!!s->quad_enable) << 6; } if (get_man(s) =3D=3D MAN_SST) { --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id k10sm12471076pfk.0.2021.01.25.22.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 22:00:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yYTOVsDICNYs9a4Nc8bQDRVEnCpcAczZDVceLgRkdvo=; b=ZAFhstByT+cDNv3dv7zNJLbdBsYZ6uZNKRxhIKo6yRhQR/5A0k1K8SoKWdPv6A+f9r USxFnKlbpantI+f550mSyhTL0v/xgrvna7fJztFZ1n41u7uC3YMgopUYkTP9zrUCH/DK WBI4rRUM1vBSf+sgWmsQr6K3wLHlDWfyMhygxypmkrK/6+g12XApZaLujQsdl1W/Jk2E QmR1mW971QKfWbQY71hNz6iF5YvSbG1PmYzN4s95h8YLINg8ieBcGpzASMQDYrtNnpEw yIPztZhaWO1DTBzwCpOZZLmHp5ougcAK/L60eAO/lrD9D6UYIOlwvfGRf3cIGaZax1Ip S+1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yYTOVsDICNYs9a4Nc8bQDRVEnCpcAczZDVceLgRkdvo=; b=CLznBxzSHhedoO5aZItJxfltO0XbwuKrX44OaRUzD0QcJfhoSw0NMkWijU56X7hQe5 VFNe7SkeTWopPz+09+5Ehkxae6AZHixc9B3FqgzNZJ+p7A4KSPYB692yJkI2n1vVkjCS iZSecKld959Uwad+iYLmhTF1t6l4uy4elDwY+VF0lCouSbL7LlGAnM2q8s3kUTJx4mJ8 fPk022BD28VQmdPBYCMhixHiiakIsNWRm00u8ZJEDJm+q3HOw7CdjIK3kMSO3FKwODYB a+T4iq2RDQt2IsqjFRYq4EhgySUTRqboUuXJ4xx2OKyBotlk0gd46u5GIUZH3xlxvfnt zwqw== X-Gm-Message-State: AOAM530t+s8pf1i3BG02Qw/24uWZ3rrqku49t5rzcTh35ThX90jYKbTZ OTmG+cCk6FimPDCZaEntgAg= X-Google-Smtp-Source: ABdhPJyPwHi8MzHYKkxKVjI4Uok5csF97QVwmD8zUKlhA5u+FTolI1crx6wAOCysf8rwoQNS+WMN1w== X-Received: by 2002:a17:90b:1004:: with SMTP id gm4mr4284092pjb.97.1611640831068; Mon, 25 Jan 2021 22:00:31 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 2/9] hw/block: m25p80: Add various ISSI flash information Date: Tue, 26 Jan 2021 14:00:00 +0800 Message-Id: <20210126060007.12904-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210126060007.12904-1-bmeng.cn@gmail.com> References: <20210126060007.12904-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng This updates the flash information table to include various ISSI flashes that are supported by upstream U-Boot and Linux kernel. Signed-off-by: Bin Meng Acked-by: Alistair Francis --- (no changes since v1) hw/block/m25p80.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 217c130f56..4bf8aa8158 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -210,6 +210,19 @@ static const FlashPartInfo known_devices[] =3D { { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, =20 + /* ISSI */ + { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, + { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, + { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, + { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, + { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, + { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, + { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, + { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, + { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, + { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, + { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) }, + /* Macronix */ { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1611641096; cv=none; d=zohomail.com; s=zohoarc; b=FaI0UwaSem1D5U7IBAUpAnriWkHO3FI9bhBLdIx2zNa+lmYOC28UlDJl5w0o1YqsmTl/lYlofPhDGdfG7PkhOQEXaTZLCTwcUaHcSQKJskAXbOj2YO/mlobnQoQVErujs1bsgbVmBZcuJpcRmXtB2ausMyQHmt0q5ekAKKl00Sw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611641096; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7R8+YL9CpcC18QIkgeFe3H5nl1a+6lBgdK1FB9zrn+s=; b=M6PHr1pqJWCXOKqubWqI/LF3fiVNg7Em92FVOCrpuzdYdUdWJAZSLsRx8a990+NH1zmxYrTc9dv9BWfkvSbB1ZaGqxWv+/ZSLumlrwoRDfa71KNFGC1gk68x5kScjwARRvGolkOziIsq6VChTRJxWRfdqMRoDG7IetkUcp3SuBk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611641096814874.2131875673019; Mon, 25 Jan 2021 22:04:56 -0800 (PST) Received: from localhost ([::1]:42342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l4HTB-0005lf-6w for importer@patchew.org; Tue, 26 Jan 2021 01:04:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4HP6-0000fo-Vz; Tue, 26 Jan 2021 01:00:41 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:35448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4HP3-0001SX-SQ; Tue, 26 Jan 2021 01:00:40 -0500 Received: by mail-pj1-x102c.google.com with SMTP id e9so1609219pjj.0; Mon, 25 Jan 2021 22:00:36 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id k10sm12471076pfk.0.2021.01.25.22.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 22:00:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7R8+YL9CpcC18QIkgeFe3H5nl1a+6lBgdK1FB9zrn+s=; b=Jr8Gs5hO44XjVa7K7cR2rYNFmCgc/5UDT1XKZ5KzGHeBP7zE1aJiF848IqECDgBl0l vcOZ+30Nf12H8W8w6gAnIsAFGhWNFXGG+Ph7Xelwg/jWSxnDz6CPRvEIWVZqaMnRzqCA x88e6raIKQTHXfe4lA+W32Z39NJIyezoj9i7F9oraP7CC4QmEbv6hug3Q4r8dJI511h4 YWXKTcTW7mbKR3xoEkzIcujJ6CLDoEMvw7rHgNBZce0FGscp4FbpwKjSZ0wErYBO3VET i+wruqiRsmmBDwOZJERepMRs/aoMoObN4NUF19L6/Yl36TO3Qr/dTLvFXkA7F65fajrN uy1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7R8+YL9CpcC18QIkgeFe3H5nl1a+6lBgdK1FB9zrn+s=; b=umrilBx9qQznmrDnRYNvWAyUgHADe4QlSGlIl6rxTtZpbVx5DEW+P0+HR15uBgFUYC ig+PjcVz1ktTZeKxpCXNcmzLrP4f2lWwqpbab9+1ZjzSV6rrFAOUVCOlCBAZUre9gOSe Qm2x+uwnRcKFkD+Ag+yQqQ2fOPLdfPmh+yHHs8UceSAuWRDC9e/JXJDJF4tkrQx8HTvn XUgt6xCV5+kfSESjjwNnVdPtJTZGXjtJkFFENpxx9No9pEx8BEOmwxvpbjN31W+1XWkg EgmspIQmxHdRTPp4MqBs6RWK+lBp5n1ak99gBJx0w9n4motK4iYEK1lQ2vWtd5Pzx0Mr u2vQ== X-Gm-Message-State: AOAM531NldiSV1umLWT0g03j4ZWIb5CH4XPPhyCRvWmb09OJYyuucFQy ILlU/x8AON+0bwy9/NO5l7U= X-Google-Smtp-Source: ABdhPJz1pjCltAPIm3mFsSAtfYK+dtZQDHRTanZZFgZajKPwJvR/89LH7akcD4ZaFMhssj9wYCA6cw== X-Received: by 2002:a17:903:2305:b029:df:c991:8c49 with SMTP id d5-20020a1709032305b02900dfc9918c49mr4388622plh.8.1611640836007; Mon, 25 Jan 2021 22:00:36 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support Date: Tue, 26 Jan 2021 14:00:01 +0800 Message-Id: <20210126060007.12904-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210126060007.12904-1-bmeng.cn@gmail.com> References: <20210126060007.12904-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng Acked-by: Bin Meng Acked-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- Changes in v3: - Simplify flush txfifo logic Changes in v2: - Log guest error when trying to write reserved registers - Log guest error when trying to access out-of-bounds registers - log guest error when writing to reserved bits for chip select registers and watermark registers - Log unimplemented warning when trying to write direct-map flash interface registers - Add test tx fifo full logic in sifive_spi_read(), hence remove setting the tx fifo full flag in sifive_spi_write(). - Populate register with their default value include/hw/ssi/sifive_spi.h | 47 +++++ hw/ssi/sifive_spi.c | 358 ++++++++++++++++++++++++++++++++++++ hw/ssi/Kconfig | 4 + hw/ssi/meson.build | 1 + 4 files changed, 410 insertions(+) create mode 100644 include/hw/ssi/sifive_spi.h create mode 100644 hw/ssi/sifive_spi.c diff --git a/include/hw/ssi/sifive_spi.h b/include/hw/ssi/sifive_spi.h new file mode 100644 index 0000000000..47d0d6a47c --- /dev/null +++ b/include/hw/ssi/sifive_spi.h @@ -0,0 +1,47 @@ +/* + * QEMU model of the SiFive SPI Controller + * + * Copyright (c) 2021 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_SPI_H +#define HW_SIFIVE_SPI_H + +#define SIFIVE_SPI_REG_NUM (0x78 / 4) + +#define TYPE_SIFIVE_SPI "sifive.spi" +#define SIFIVE_SPI(obj) OBJECT_CHECK(SiFiveSPIState, (obj), TYPE_SIFIVE_SP= I) + +typedef struct SiFiveSPIState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t num_cs; + qemu_irq *cs_lines; + + SSIBus *spi; + + Fifo8 tx_fifo; + Fifo8 rx_fifo; + + uint32_t regs[SIFIVE_SPI_REG_NUM]; +} SiFiveSPIState; + +#endif /* HW_SIFIVE_SPI_H */ diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c new file mode 100644 index 0000000000..0c9ebca3c8 --- /dev/null +++ b/hw/ssi/sifive_spi.c @@ -0,0 +1,358 @@ +/* + * QEMU model of the SiFive SPI Controller + * + * Copyright (c) 2021 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "hw/ssi/ssi.h" +#include "sysemu/sysemu.h" +#include "qemu/fifo8.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/ssi/sifive_spi.h" + +#define R_SCKDIV (0x00 / 4) +#define R_SCKMODE (0x04 / 4) +#define R_CSID (0x10 / 4) +#define R_CSDEF (0x14 / 4) +#define R_CSMODE (0x18 / 4) +#define R_DELAY0 (0x28 / 4) +#define R_DELAY1 (0x2C / 4) +#define R_FMT (0x40 / 4) +#define R_TXDATA (0x48 / 4) +#define R_RXDATA (0x4C / 4) +#define R_TXMARK (0x50 / 4) +#define R_RXMARK (0x54 / 4) +#define R_FCTRL (0x60 / 4) +#define R_FFMT (0x64 / 4) +#define R_IE (0x70 / 4) +#define R_IP (0x74 / 4) + +#define FMT_DIR (1 << 3) + +#define TXDATA_FULL (1 << 31) +#define RXDATA_EMPTY (1 << 31) + +#define IE_TXWM (1 << 0) +#define IE_RXWM (1 << 1) + +#define IP_TXWM (1 << 0) +#define IP_RXWM (1 << 1) + +#define FIFO_CAPACITY 8 + +static void sifive_spi_txfifo_reset(SiFiveSPIState *s) +{ + fifo8_reset(&s->tx_fifo); + + s->regs[R_TXDATA] &=3D ~TXDATA_FULL; + s->regs[R_IP] &=3D ~IP_TXWM; +} + +static void sifive_spi_rxfifo_reset(SiFiveSPIState *s) +{ + fifo8_reset(&s->rx_fifo); + + s->regs[R_RXDATA] |=3D RXDATA_EMPTY; + s->regs[R_IP] &=3D ~IP_RXWM; +} + +static void sifive_spi_update_cs(SiFiveSPIState *s) +{ + int i; + + for (i =3D 0; i < s->num_cs; i++) { + if (s->regs[R_CSDEF] & (1 << i)) { + qemu_set_irq(s->cs_lines[i], !(s->regs[R_CSMODE])); + } + } +} + +static void sifive_spi_update_irq(SiFiveSPIState *s) +{ + int level; + + if (fifo8_num_used(&s->tx_fifo) < s->regs[R_TXMARK]) { + s->regs[R_IP] |=3D IP_TXWM; + } else { + s->regs[R_IP] &=3D ~IP_TXWM; + } + + if (fifo8_num_used(&s->rx_fifo) > s->regs[R_RXMARK]) { + s->regs[R_IP] |=3D IP_RXWM; + } else { + s->regs[R_IP] &=3D ~IP_RXWM; + } + + level =3D s->regs[R_IP] & s->regs[R_IE] ? 1 : 0; + qemu_set_irq(s->irq, level); +} + +static void sifive_spi_reset(DeviceState *d) +{ + SiFiveSPIState *s =3D SIFIVE_SPI(d); + + memset(s->regs, 0, sizeof(s->regs)); + + /* The reset value is high for all implemented CS pins */ + s->regs[R_CSDEF] =3D (1 << s->num_cs) - 1; + + /* Populate register with their default value */ + s->regs[R_SCKDIV] =3D 0x03; + s->regs[R_DELAY0] =3D 0x1001; + s->regs[R_DELAY1] =3D 0x01; + + sifive_spi_txfifo_reset(s); + sifive_spi_rxfifo_reset(s); + + sifive_spi_update_cs(s); + sifive_spi_update_irq(s); +} + +static void sifive_spi_flush_txfifo(SiFiveSPIState *s) +{ + uint8_t tx; + uint8_t rx; + + while (!fifo8_is_empty(&s->tx_fifo)) { + tx =3D fifo8_pop(&s->tx_fifo); + rx =3D ssi_transfer(s->spi, tx); + + if (!fifo8_is_full(&s->rx_fifo)) { + if (!(s->regs[R_FMT] & FMT_DIR)) { + fifo8_push(&s->rx_fifo, rx); + } + } + } +} + +static bool sifive_spi_is_bad_reg(hwaddr addr, bool allow_reserved) +{ + bool bad; + + switch (addr) { + /* reserved offsets */ + case 0x08: + case 0x0C: + case 0x1C: + case 0x20: + case 0x24: + case 0x30: + case 0x34: + case 0x38: + case 0x3C: + case 0x44: + case 0x58: + case 0x5C: + case 0x68: + case 0x6C: + bad =3D allow_reserved ? false : true; + break; + default: + bad =3D false; + } + + if (addr >=3D (SIFIVE_SPI_REG_NUM << 2)) { + bad =3D true; + } + + return bad; +} + +static uint64_t sifive_spi_read(void *opaque, hwaddr addr, unsigned int si= ze) +{ + SiFiveSPIState *s =3D opaque; + uint32_t r; + + if (sifive_spi_is_bad_reg(addr, true)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read at address 0x%" + HWADDR_PRIx "\n", __func__, addr); + return 0; + } + + addr >>=3D 2; + switch (addr) { + case R_TXDATA: + if (fifo8_is_full(&s->tx_fifo)) { + return TXDATA_FULL; + } + r =3D 0; + break; + + case R_RXDATA: + if (fifo8_is_empty(&s->rx_fifo)) { + return RXDATA_EMPTY; + } + r =3D fifo8_pop(&s->rx_fifo); + break; + + default: + r =3D s->regs[addr]; + break; + } + + sifive_spi_update_irq(s); + + return r; +} + +static void sifive_spi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveSPIState *s =3D opaque; + uint32_t value =3D val64; + + if (sifive_spi_is_bad_reg(addr, false)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write at addr=3D0x%" + HWADDR_PRIx " value=3D0x%x\n", __func__, addr, value= ); + return; + } + + addr >>=3D 2; + switch (addr) { + case R_CSID: + if (value >=3D s->num_cs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csid %d\n", + __func__, value); + } else { + s->regs[R_CSID] =3D value; + sifive_spi_update_cs(s); + } + break; + + case R_CSDEF: + if (value >=3D (1 << s->num_cs)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csdef %x\n", + __func__, value); + } else { + s->regs[R_CSDEF] =3D value; + } + break; + + case R_CSMODE: + if (value > 3) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csmode %x\n", + __func__, value); + } else { + s->regs[R_CSMODE] =3D value; + sifive_spi_update_cs(s); + } + break; + + case R_TXDATA: + if (!fifo8_is_full(&s->tx_fifo)) { + fifo8_push(&s->tx_fifo, (uint8_t)value); + sifive_spi_flush_txfifo(s); + } + break; + + case R_RXDATA: + case R_IP: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write to read-only reigster 0x%" + HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, val= ue); + break; + + case R_TXMARK: + case R_RXMARK: + if (value >=3D FIFO_CAPACITY) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid watermark %d\n", + __func__, value); + } else { + s->regs[addr] =3D value; + } + break; + + case R_FCTRL: + case R_FFMT: + qemu_log_mask(LOG_UNIMP, + "%s: direct-map flash interface unimplemented\n", + __func__); + break; + + default: + s->regs[addr] =3D value; + break; + } + + sifive_spi_update_irq(s); +} + +static const MemoryRegionOps sifive_spi_ops =3D { + .read =3D sifive_spi_read, + .write =3D sifive_spi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void sifive_spi_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + SiFiveSPIState *s =3D SIFIVE_SPI(dev); + int i; + + s->spi =3D ssi_create_bus(dev, "spi"); + sysbus_init_irq(sbd, &s->irq); + + s->cs_lines =3D g_new0(qemu_irq, s->num_cs); + for (i =3D 0; i < s->num_cs; i++) { + sysbus_init_irq(sbd, &s->cs_lines[i]); + } + + memory_region_init_io(&s->mmio, OBJECT(s), &sifive_spi_ops, s, + TYPE_SIFIVE_SPI, 0x1000); + sysbus_init_mmio(sbd, &s->mmio); + + fifo8_create(&s->tx_fifo, FIFO_CAPACITY); + fifo8_create(&s->rx_fifo, FIFO_CAPACITY); +} + +static Property sifive_spi_properties[] =3D { + DEFINE_PROP_UINT32("num-cs", SiFiveSPIState, num_cs, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_props(dc, sifive_spi_properties); + dc->reset =3D sifive_spi_reset; + dc->realize =3D sifive_spi_realize; +} + +static const TypeInfo sifive_spi_info =3D { + .name =3D TYPE_SIFIVE_SPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SiFiveSPIState), + .class_init =3D sifive_spi_class_init, +}; + +static void sifive_spi_register_types(void) +{ + type_register_static(&sifive_spi_info); +} + +type_init(sifive_spi_register_types) diff --git a/hw/ssi/Kconfig b/hw/ssi/Kconfig index 9e54a0c8dd..7d90a02181 100644 --- a/hw/ssi/Kconfig +++ b/hw/ssi/Kconfig @@ -2,6 +2,10 @@ config PL022 bool select SSI =20 +config SIFIVE_SPI + bool + select SSI + config SSI bool =20 diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build index dee00c0da6..3d6bc82ab1 100644 --- a/hw/ssi/meson.build +++ b/hw/ssi/meson.build @@ -2,6 +2,7 @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('a= speed_smc.c')) softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SPI', if_true: files('stm32f2xx_spi= .c')) softmmu_ss.add(when: 'CONFIG_XILINX_SPI', if_true: files('xilinx_spi.c')) --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id k10sm12471076pfk.0.2021.01.25.22.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 22:00:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HuNWMDHqGG+hRJwi1+cd0oN29gIyiEQDQI3q6sZVeEE=; b=lxPYIEws4xphtDjK5U6BxoeHk9Lvh57d2VVehOHpcbgtz+x6+QNvp2DcjpD2BHbCm+ r8UN+PEzyI45BQeHM1N5ffpNvcA6m5c4So/3XqIC6BiAqig5vSg2un+Z1XHKNEFT0DIf YEmR385PUjLhT7TvAxJlihZNTgAOCf733pjtZMUaYy3HYyPpbKNgnlZxfo0AsW/lQg/A dqzzfScJCxoDVNA1mAeoJVeD0HPuBpybV0R84xGw/Z8Iu96c5awBmnS3bH8cI1Mx9tCJ G0LBMgaGxz+SBAo38zPpKnm9K22o3IdCJUEEnKwz6odfu0kYHubLVBpJJFryuipxW4Aw yIBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HuNWMDHqGG+hRJwi1+cd0oN29gIyiEQDQI3q6sZVeEE=; b=D4uOC9BhCiN9sFgQ/93JC/pKSh6DI1ekeS/DulkLz4utfrXYW6s2NhNbTu54nQztrh XeouPfyJ4rUPopgrmSlmEUlbtAxSHcGyKwG2nZI/CXie9NQHLdiJuq6bL0x9cB2iCoA0 7+HNVKnqy8VRtDtle8cYe57oa1VuQWpZb4pNUzKZ8lsrlR8zvb6g7RlaydT2uIwLmPvD JFQXBscVUwX15aE5hM/CPwPXbxaAW7bagEg5C1uaDqt4EAXOhmQCgwMBSgLSZwxqCYn7 VmZogVVj+tb9smxYYHhw9TJ4R7rP8TNiIsRr0ad2mvTyyXLT+1WGoR7RBQLk7GY10CV9 +4uw== X-Gm-Message-State: AOAM532AQiAmmLJGpsIYzLYsIJ9qyZG+NJK82uEOPkXdIZVRbvgHM4YY T2A44lQKmSBzJmV5Rg9gsMQ8Ob14GxOVtQ== X-Google-Smtp-Source: ABdhPJxD04SP49hxcPadcI2Hwu/nHcRdlG1rFoZIUIFQ9TG4eLsAbA/S8E5LTPvH1ET8TIGph6xVNA== X-Received: by 2002:a17:902:b906:b029:df:ec2e:b49d with SMTP id bf6-20020a170902b906b02900dfec2eb49dmr4271368plb.77.1611640839662; Mon, 25 Jan 2021 22:00:39 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 4/9] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Date: Tue, 26 Jan 2021 14:00:02 +0800 Message-Id: <20210126060007.12904-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210126060007.12904-1-bmeng.cn@gmail.com> References: <20210126060007.12904-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds the QSPI0 controller to the SoC, and connects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. Since the direct memory-mapped mode is not supported by the SiFive SPI model, the property does not populate the second group which represents the memory mapped address of the SPI flash. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to L2LIM, then U-Boot SPL loads the payload from SPI flash that is combined with OpenSBI fw_dynamic firmware and U-Boot proper. Specify machine property `msel` to 6 to allow booting from the SPI flash. U-Boot spl is directly loaded via `-bios`, and subsequent payload is stored in the SPI flash image. Example command line: $ qemu-system-riscv64 -nographic -M sifive_u,msel=3D6 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=3Dspi-nor.img,if=3Dmtd Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - Correct the "connects" typo in the commit message - Mention in the commit message that property does not populate the second group which represents the memory mapped address of the SPI flash include/hw/riscv/sifive_u.h | 4 +++ hw/riscv/sifive_u.c | 52 +++++++++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 2 ++ 3 files changed, 58 insertions(+) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a9f7b4a084..8824b7c031 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -26,6 +26,7 @@ #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" +#include "hw/ssi/sifive_spi.h" =20 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -45,6 +46,7 @@ typedef struct SiFiveUSoCState { SIFIVEGPIOState gpio; SiFiveUOTPState otp; SiFivePDMAState dma; + SiFiveSPIState spi0; CadenceGEMState gem; =20 uint32_t serial; @@ -82,6 +84,7 @@ enum { SIFIVE_U_DEV_UART0, SIFIVE_U_DEV_UART1, SIFIVE_U_DEV_GPIO, + SIFIVE_U_DEV_QSPI0, SIFIVE_U_DEV_OTP, SIFIVE_U_DEV_DMC, SIFIVE_U_DEV_FLASH0, @@ -120,6 +123,7 @@ enum { SIFIVE_U_PDMA_IRQ5 =3D 28, SIFIVE_U_PDMA_IRQ6 =3D 29, SIFIVE_U_PDMA_IRQ7 =3D 30, + SIFIVE_U_QSPI0_IRQ =3D 51, SIFIVE_U_GEM_IRQ =3D 0x35 }; =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 59b61cea01..43a0e983d2 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -15,6 +15,7 @@ * 5) OTP (One-Time Programmable) memory with stored serial number * 6) GEM (Gigabit Ethernet Controller) and management block * 7) DMA (Direct Memory Access Controller) + * 8) SPI0 connected to an SPI flash * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -44,6 +45,7 @@ #include "hw/char/serial.h" #include "hw/cpu/cluster.h" #include "hw/misc/unimp.h" +#include "hw/ssi/ssi.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" @@ -74,6 +76,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEV_PRCI] =3D { 0x10000000, 0x1000 }, [SIFIVE_U_DEV_UART0] =3D { 0x10010000, 0x1000 }, [SIFIVE_U_DEV_UART1] =3D { 0x10011000, 0x1000 }, + [SIFIVE_U_DEV_QSPI0] =3D { 0x10040000, 0x1000 }, [SIFIVE_U_DEV_GPIO] =3D { 0x10060000, 0x1000 }, [SIFIVE_U_DEV_OTP] =3D { 0x10070000, 0x1000 }, [SIFIVE_U_DEV_GEM] =3D { 0x10090000, 0x2000 }, @@ -342,6 +345,32 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, "sifive,fu540-c000-ccache"); g_free(nodename); =20 + nodename =3D g_strdup_printf("/soc/spi@%lx", + (long)memmap[SIFIVE_U_DEV_QSPI0].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, + 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); + g_free(nodename); + + nodename =3D g_strdup_printf("/soc/spi@%lx/flash@0", + (long)memmap[SIFIVE_U_DEV_QSPI0].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); + qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); + qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); + qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); + g_free(nodename); + phy_phandle =3D phandle++; nodename =3D g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_DEV_GEM].base); @@ -439,6 +468,9 @@ static void sifive_u_machine_init(MachineState *machine) int i; uint32_t fdt_load_addr; uint64_t kernel_entry; + DriveInfo *dinfo; + DeviceState *flash_dev; + qemu_irq flash_cs; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); @@ -571,6 +603,19 @@ static void sifive_u_machine_init(MachineState *machin= e) riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, memmap[SIFIVE_U_DEV_MROM].size, sizeof(reset_vec), kernel_entry); + + /* Connect an SPI flash to SPI0 */ + flash_dev =3D qdev_new("is25wp256"); + dinfo =3D drive_get_next(IF_MTD); + if (dinfo) { + qdev_prop_set_drive_err(flash_dev, "drive", + blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); + + flash_cs =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); } =20 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) @@ -680,6 +725,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); } =20 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) @@ -827,6 +873,12 @@ static void sifive_u_soc_realize(DeviceState *dev, Err= or **errp) =20 create_unimplemented_device("riscv.sifive.u.l2cc", memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); + + sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, + memmap[SIFIVE_U_DEV_QSPI0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IR= Q)); } =20 static Property sifive_u_soc_props[] =3D { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index facb0cbacc..6330297b4e 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -52,9 +52,11 @@ config SIFIVE_U select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_PLIC + select SIFIVE_SPI select SIFIVE_UART select SIFIVE_U_OTP select SIFIVE_U_PRCI + select SSI_M25P80 select UNIMP =20 config SPIKE --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1611641313; cv=none; d=zohomail.com; s=zohoarc; b=cjffYHjGRiNbTM1NMjOC5bIInhwzGv9+KSBnoxvOgoa073CAQAUqN9CyMufOE3PPNNE2+6TDtTQpuxuymGYkSwrV94976aMnd7EFx/b1WXQ8cNztfdbyn/gZ/RJskoE21rI2TJ9NgT9NyZeyu654TvcHYEt/hZ7plXIu+rQxgZc= ARC-Message-Signature: i=1; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id k10sm12471076pfk.0.2021.01.25.22.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 22:00:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dVFk9qSZOIKkBe8R17maG8yviTmhUi6St/B3Dc4DTX0=; b=de0RIZ1/4azwmizO3ZkRvl5l9tGVpD9khEfw+GhKD/KzHX+uFllDova0ELv65RTFe9 Cz1ieolynCoJhdp8w4JVf1JvOpctJc9+BdqckYD2Y+mAzgKg4rd4QmN8FpuHokFNezxL CFhDFXyxLrfqJ9Q7xxKlU3mcOSFSxRczANxrAaub4OQULCQs1BlrnoWxPUEcWYhaYYfb mMRY+UQ6gbcA1BBXGK07El01V/hiRdLdpe2ia7BO3F83LHFiXjC6Dx9bFv8hMdL93KcH PwpM5/us2rJ1tsGbluf87hVFbt6F6w3w8uB1UNAbbTcxjs9Fi2javtKPCqS6Q7OvJZ2B As/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dVFk9qSZOIKkBe8R17maG8yviTmhUi6St/B3Dc4DTX0=; b=t/LwD9POY/knvfOVrOhhvzEjhl20eUa+2pDjpLLUWxFXxt6YTbBVmakxssp+TZ5jKS eAS5DmVik26Yb9q8CjszMno8Gl8f/287n8zDYCxr6GT2wgAdk1yRCSOdj6HkWVTZNTQa cBFyk1cC1HwT3QQr7JCf0yEbZlu/wKWWXTf7lDfe6ojaz3GomnnVMyMEQA/DuVocEYXc WXnKa6uU+dXxMi+ypDD6ZHE6EpzAEkkqLN2iHa4J+JhGJGt+jA54bKE8xP4D+JyYMpNE hJ4ajthIb5gtwQkinBgjAXDZW3TUFhodA3LlDQhGdKObVcH0+r6YZCFXZWz+OkgzoRcJ Jxhg== X-Gm-Message-State: AOAM531A/I1F1lf+qTvrJiiM7Uzft3JHumCBMl3aGZBCrtGWYnD6+weH AXCrQkhWe54Zj3YT9NemSBNrzWA4LgXu8w== X-Google-Smtp-Source: ABdhPJwLgiJceNNaRYbpBZlh5SNaXu7MJDp8kpvK576x8MspajaQr02yhltIwh1uGTYRVsfLEq4VlQ== X-Received: by 2002:a65:5b0c:: with SMTP id y12mr4219357pgq.407.1611640843762; Mon, 25 Jan 2021 22:00:43 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 5/9] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Date: Tue, 26 Jan 2021 14:00:03 +0800 Message-Id: <20210126060007.12904-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210126060007.12904-1-bmeng.cn@gmail.com> References: <20210126060007.12904-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=3D11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=3Dsdcard.img,if=3Dsd Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - Correct the "connects" typo in the commit message include/hw/riscv/sifive_u.h | 3 +++ hw/riscv/sifive_u.c | 43 +++++++++++++++++++++++++++++++++++-- hw/riscv/Kconfig | 1 + 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 8824b7c031..de1464a2ce 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -47,6 +47,7 @@ typedef struct SiFiveUSoCState { SiFiveUOTPState otp; SiFivePDMAState dma; SiFiveSPIState spi0; + SiFiveSPIState spi2; CadenceGEMState gem; =20 uint32_t serial; @@ -85,6 +86,7 @@ enum { SIFIVE_U_DEV_UART1, SIFIVE_U_DEV_GPIO, SIFIVE_U_DEV_QSPI0, + SIFIVE_U_DEV_QSPI2, SIFIVE_U_DEV_OTP, SIFIVE_U_DEV_DMC, SIFIVE_U_DEV_FLASH0, @@ -99,6 +101,7 @@ enum { SIFIVE_U_L2CC_IRQ2 =3D 3, SIFIVE_U_UART0_IRQ =3D 4, SIFIVE_U_UART1_IRQ =3D 5, + SIFIVE_U_QSPI2_IRQ =3D 6, SIFIVE_U_GPIO_IRQ0 =3D 7, SIFIVE_U_GPIO_IRQ1 =3D 8, SIFIVE_U_GPIO_IRQ2 =3D 9, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 43a0e983d2..6c1158a848 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -16,6 +16,7 @@ * 6) GEM (Gigabit Ethernet Controller) and management block * 7) DMA (Direct Memory Access Controller) * 8) SPI0 connected to an SPI flash + * 9) SPI2 connected to an SD card * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -77,6 +78,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEV_UART0] =3D { 0x10010000, 0x1000 }, [SIFIVE_U_DEV_UART1] =3D { 0x10011000, 0x1000 }, [SIFIVE_U_DEV_QSPI0] =3D { 0x10040000, 0x1000 }, + [SIFIVE_U_DEV_QSPI2] =3D { 0x10050000, 0x1000 }, [SIFIVE_U_DEV_GPIO] =3D { 0x10060000, 0x1000 }, [SIFIVE_U_DEV_OTP] =3D { 0x10070000, 0x1000 }, [SIFIVE_U_DEV_GEM] =3D { 0x10090000, 0x2000 }, @@ -345,6 +347,31 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, "sifive,fu540-c000-ccache"); g_free(nodename); =20 + nodename =3D g_strdup_printf("/soc/spi@%lx", + (long)memmap[SIFIVE_U_DEV_QSPI2].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, + 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); + g_free(nodename); + + nodename =3D g_strdup_printf("/soc/spi@%lx/mmc@0", + (long)memmap[SIFIVE_U_DEV_QSPI2].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); + qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); + qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); + g_free(nodename); + nodename =3D g_strdup_printf("/soc/spi@%lx", (long)memmap[SIFIVE_U_DEV_QSPI0].base); qemu_fdt_add_subnode(fdt, nodename); @@ -469,8 +496,8 @@ static void sifive_u_machine_init(MachineState *machine) uint32_t fdt_load_addr; uint64_t kernel_entry; DriveInfo *dinfo; - DeviceState *flash_dev; - qemu_irq flash_cs; + DeviceState *flash_dev, *sd_dev; + qemu_irq flash_cs, sd_cs; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); @@ -616,6 +643,12 @@ static void sifive_u_machine_init(MachineState *machin= e) =20 flash_cs =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); + + /* Connect an SD card to SPI2 */ + sd_dev =3D ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); + + sd_cs =3D qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); } =20 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) @@ -726,6 +759,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); + object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); } =20 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) @@ -879,6 +913,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Err= or **errp) memmap[SIFIVE_U_DEV_QSPI0].base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IR= Q)); + sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, + memmap[SIFIVE_U_DEV_QSPI2].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IR= Q)); } =20 static Property sifive_u_soc_props[] =3D { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 6330297b4e..d139074b02 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -57,6 +57,7 @@ config SIFIVE_U select SIFIVE_U_OTP select SIFIVE_U_PRCI select SSI_M25P80 + select SSI_SD select UNIMP =20 config SPIKE --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Change SIFIVE_U_GEM_IRQ to be consistent. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/sifive_u.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index de1464a2ce..2656b39808 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -127,7 +127,7 @@ enum { SIFIVE_U_PDMA_IRQ6 =3D 29, SIFIVE_U_PDMA_IRQ7 =3D 30, SIFIVE_U_QSPI0_IRQ =3D 51, - SIFIVE_U_GEM_IRQ =3D 0x35 + SIFIVE_U_GEM_IRQ =3D 53 }; =20 enum { --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1611640960; cv=none; d=zohomail.com; s=zohoarc; b=ikNsYnw74+fNpvXtoQif1s6BYvJxtR91slmzfUIaWK72hRD4i96on6NYdS1q7HSm7GDoxxLFGqAZxR5SXd0cBc6+p/JTF0yVpHdZQYWdLfJ4MbjJ1AUZ/VXEMrPOKlkRcNLb/SldhlLkxhyRcFLopxKFTZBVwayNGuVJQjqzk64= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611640960; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gk6VLOJ8dC9W0TNqig3ksBlOBksYube8P0MfFHo64eg=; b=Sp9boAUbRPMsAioa6sCgG6ZZ5uwraKJsP13IpO/cAHxCqDFU1gdj2UDse5KDqqm4+8cjVgiTtcA0Fvfh0Uk1cV2KbxmecjZNhuexownA7E8mQsWAGv8XVEhlvDsdxnBIincPnd4j2POj3mDj1qRi+TTapmjvjCMyJTAHTTJlr8A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611640960700274.4680415853736; Mon, 25 Jan 2021 22:02:40 -0800 (PST) Received: from localhost ([::1]:35610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l4HR1-0002ww-FI for importer@patchew.org; Tue, 26 Jan 2021 01:02:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4HPK-00014a-7k; Tue, 26 Jan 2021 01:00:58 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:41497) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4HPI-0001Xe-4N; Tue, 26 Jan 2021 01:00:53 -0500 Received: by mail-pf1-x42d.google.com with SMTP id q20so9863487pfu.8; Mon, 25 Jan 2021 22:00:51 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) docs/system/targets.rst | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 560783644d..564cea9a9b 100644 --- a/docs/system/targets.rst +++ b/docs/system/targets.rst @@ -7,16 +7,21 @@ various targets are mentioned in the following sections. =20 Contents: =20 +.. + This table of contents should be kept sorted alphabetically + by the title text of each file, which isn't the same ordering + as an alphabetical sort by filename. + .. toctree:: =20 - target-i386 + target-arm + target-avr + target-m68k + target-mips target-ppc + target-rx + target-s390x target-sparc target-sparc64 - target-mips - target-arm - target-m68k + target-i386 target-xtensa - target-s390x - target-rx - target-avr --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id k10sm12471076pfk.0.2021.01.25.22.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 22:00:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UQOMtGdz0w0TywH10TJtkHuiebtl24nbFHb0UeqsueY=; b=eslbq96FPK8v8GxSeLyPiRMiDG+hT/IAO4vDK/bFkiGmeWS4mY2siWeG72sOMxC4UX NdatbiGDshAOPp54aOz75Z1GBXIMMocAayoJEu+edGOvbtUnwsNa4UHLQ58rczNQ89d5 1gVVVWQvgZk2RHiQRYGFUd/8t+LU+x4wdFXmDHMW3wMOeGjfWVQ/kBxDr9z8SI04a32V yFIYWvhwze178V/eoViyt6kqiCvJW4ddultY5uGi+p7awWGMyUElV/tnk/eAQ5Aucu6a 7OV1EpMJmwnns0T/tSQxqHs3wntZrjk5EJMy/yNFd4EnKiqX39Uj3bJKBQPgKYi7oIzg EJ7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UQOMtGdz0w0TywH10TJtkHuiebtl24nbFHb0UeqsueY=; b=oWTZGaBDeNxhoprHpaVOFAfFM/K3NKugZ+jEOiyL9wlcsEp5gkREgvy8ru8hA6MjlX 5dumynTLEXBE8omFTte4sd6SIvnQU6RDTzhAptOWNhkesWgjuQDRfTtD8L1i66/TCxYd eUuQDvSB08l1+eBI3vVBtUW48U1hHYqt0nhyzGlVy9AkuID6lK3DOnHJoHFd00nD6JvM nkvZB1uOWRrAVvvKXiOHNgh4WRtDbQ6uv9aqXR/I3RpuEp6bN/FTR8hlC5Ri2/EiwvHv kYeVAWT/AQg9ravpdFDK+659AcinpucPQhKcHgTfq3aCT4lICKvtXX++mQoFnKBkN0Bh Dtkg== X-Gm-Message-State: AOAM531omoeCbGcG6XG6VhXH5CW8vPpIaopetWsFPTLtyKy8H6w+2g6f QOTR897q+KPhqbMyuWpY0FM= X-Google-Smtp-Source: ABdhPJwvVkRvbzoZK2Zxs1RTSOb7aGHeuf1JPcx6UpktFKwuXH4+Lw7Ulz+6K7QFdmzqP9/aw6OH3w== X-Received: by 2002:a17:902:c40c:b029:dc:9bc9:b98d with SMTP id k12-20020a170902c40cb02900dc9bc9b98dmr4484767plk.19.1611640857114; Mon, 25 Jan 2021 22:00:57 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 8/9] docs/system: Add RISC-V documentation Date: Tue, 26 Jan 2021 14:00:06 +0800 Message-Id: <20210126060007.12904-9-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210126060007.12904-1-bmeng.cn@gmail.com> References: <20210126060007.12904-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng Add RISC-V system emulator documentation for generic information. `Board-specific documentation` and `RISC-V CPU features` are only a placeholder and will be added in the future. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) docs/system/target-riscv.rst | 62 ++++++++++++++++++++++++++++++++++++ docs/system/targets.rst | 1 + 2 files changed, 63 insertions(+) create mode 100644 docs/system/target-riscv.rst diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst new file mode 100644 index 0000000000..9f4b7586e5 --- /dev/null +++ b/docs/system/target-riscv.rst @@ -0,0 +1,62 @@ +.. _RISC-V-System-emulator: + +RISC-V System emulator +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the +``qemu-system-riscv64`` executable to simulate a 64-bit RISC-V machine, +``qemu-system-riscv32`` executable to simulate a 32-bit RISC-V machine. + +QEMU has generally good support for RISC-V guests. It has support for +several different machines. The reason we support so many is that +RISC-V hardware is much more widely varying than x86 hardware. RISC-V +CPUs are generally built into "system-on-chip" (SoC) designs created by +many different companies with different devices, and these SoCs are +then built into machines which can vary still further even if they use +the same SoC. + +For most boards the CPU type is fixed (matching what the hardware has), +so typically you don't need to specify the CPU type by hand, except for +special cases like the ``virt`` board. + +Choosing a board model +---------------------- + +For QEMU's RISC-V system emulation, you must specify which board +model you want to use with the ``-M`` or ``--machine`` option; +there is no default. + +Because RISC-V systems differ so much and in fundamental ways, typically +operating system or firmware images intended to run on one machine +will not run at all on any other. This is often surprising for new +users who are used to the x86 world where every system looks like a +standard PC. (Once the kernel has booted, most user space software +cares much less about the detail of the hardware.) + +If you already have a system image or a kernel that works on hardware +and you want to boot with QEMU, check whether QEMU lists that machine +in its ``-machine help`` output. If it is listed, then you can probably +use that board model. If it is not listed, then unfortunately your image +will almost certainly not boot on QEMU. (You might be able to +extract the file system and use that with a different kernel which +boots on a system that QEMU does emulate.) + +If you don't care about reproducing the idiosyncrasies of a particular +bit of hardware, such as small amount of RAM, no PCI or other hard +disk, etc., and just want to run Linux, the best option is to use the +``virt`` board. This is a platform which doesn't correspond to any +real hardware and is designed for use in virtual machines. You'll +need to compile Linux with a suitable configuration for running on +the ``virt`` board. ``virt`` supports PCI, virtio, recent CPUs and +large amounts of RAM. It also supports 64-bit CPUs. + +Board-specific documentation +---------------------------- + +Unfortunately many of the RISC-V boards QEMU supports are currently +undocumented; you can get a complete list by running +``qemu-system-riscv64 --machine help``, or +``qemu-system-riscv32 --machine help``. + +RISC-V CPU features +------------------- diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 564cea9a9b..75ed1087fd 100644 --- a/docs/system/targets.rst +++ b/docs/system/targets.rst @@ -19,6 +19,7 @@ Contents: target-m68k target-mips target-ppc + target-riscv target-rx target-s390x target-sparc --=20 2.25.1 From nobody Tue Apr 16 22:08:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1611641397; cv=none; d=zohomail.com; s=zohoarc; b=mYkoQkSqT2rFFn+xYcD53QN4c6Svsytzx6GKYwVoE/Fcqg5fXRrNgmrXWsIrp+7mi+tllafJMmS4EZX7F5Tur4Pn76Fa/kfJcxUTWZgCA1OqYrQJNKEmRh80hQZ7oHr7kH5YrOJh4Ipgy6eVl9SmaxRd9K3yMOKneBx8X4+2N0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611641397; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v97D7smHMIUwyVZ3xHv8OaavtvY8DGMN9i4ZZVD+ZOs=; b=WRW0IQpSsFYMu4eSS/QBvpTIrBbGzWxsaIGskTvwdmc39XgNlfPWUU1AVKyVD7FIAOVX4oQ5aakxQc+mSdIPhKi9ny+1XWDXluFYKE8GqMPCQwJMmilP8HaXNkpQ5gHDq+DbWsjlWivr5B2OhoahD3rqd4/G9UQJu0iAGdhC0Oc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611641397561850.4142240360185; Mon, 25 Jan 2021 22:09:57 -0800 (PST) Received: from localhost ([::1]:53708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l4HY4-0002C0-Do for importer@patchew.org; Tue, 26 Jan 2021 01:09:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4HPW-0001DC-Ol; Tue, 26 Jan 2021 01:01:06 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:35913) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4HPS-0001fs-Mc; Tue, 26 Jan 2021 01:01:06 -0500 Received: by mail-pj1-x1035.google.com with SMTP id gx1so1604899pjb.1; Mon, 25 Jan 2021 22:01:01 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id k10sm12471076pfk.0.2021.01.25.22.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 22:01:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v97D7smHMIUwyVZ3xHv8OaavtvY8DGMN9i4ZZVD+ZOs=; b=FJK3OPzw2rImAY7UugurDpQpBR28b7jkl1+ubosI7+FPt7/WIOudvSLKM5Urd7EGbB 2FDDDGXaT8hRrx6gV/5aXqqEvxNCx4qBBoGQLJw7DS9uPQ3rZAGGZMY3IWIWqnYbFsUs bFsVm/NSCT9mKTvRX/Qu+A1rE1mNrYEYE+/Kiaatp4OpOO7AEFe9Zm4DOeRcn+kNT7Nn Oxuow8OGCSrTdBFhnStZAAUhpbnON+c1RSHgy1hia8wzPKBpGv0hUdDo92Zxa9hc4akO +ipKguatccKxw8Eq0zu2ckLL7Iw5kXVuduyPIr/K0DIVrVp7vHVNrgzf3+r499eQ/SEP zMkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v97D7smHMIUwyVZ3xHv8OaavtvY8DGMN9i4ZZVD+ZOs=; b=deppdyxG4DUDqfeFwAYTC1oQybelIoN2dpr5NgJC1kkUP78aEKGWONdMeBDPHnyeN5 /zqDYlJS8VQ+YGW/cmLgfW/yj7DFacfFWM9XEtylSEXo0YoMTVXdr4VmbblM72VBcelh XGSwqysckfGaGiGOYE21cXn8Qu//Uw13ZeUmC9xW841O27CBGANclIguC0RaN30+5njr O6RL1n5yYs+Rqb4KYre6P/ga+bA4MZxtAuPwPTRhEpiQi6IIy2lkkppzRcwoPJmCY2mT dUQbb6YeTjjoJg6k113d2WQfqCKwOHC53iJLnhkRmDFH5jsWbjQkOFHRhIudi2niXW0h mVbg== X-Gm-Message-State: AOAM5325wCq67gImzS1HaP06nQS65I5JFERjm62VqbZdtuzgQJvFLcFO CqqiVLBCL9WvdV6LGZ6irQo= X-Google-Smtp-Source: ABdhPJzxM/lJ4Kd7P6z5HnOJeMxGLL8t/MHqhJCbazAuAKtTi9NVvV02hgujpJsWYGnvWqdWOFwx8Q== X-Received: by 2002:a17:902:ea0f:b029:de:5fd5:abb9 with SMTP id s15-20020a170902ea0fb02900de5fd5abb9mr4278946plg.46.1611640860518; Mon, 25 Jan 2021 22:01:00 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 9/9] docs/system: riscv: Add documentation for sifive_u machine Date: Tue, 26 Jan 2021 14:00:07 +0800 Message-Id: <20210126060007.12904-10-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210126060007.12904-1-bmeng.cn@gmail.com> References: <20210126060007.12904-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds detailed documentation for RISC-V `sifive_u` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Machine-specific options - Running Linux kernel - Running VxWorks kernel - Running U-Boot, and with an alternate configuration Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- Changes in v3: - Convert sifive_u.rst from UTF-8 to ASCII Changes in v2: - Correct several typos in sifive_u.rst - Update doc to mention U-Boot v2021.01 docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 10 + 2 files changed, 346 insertions(+) create mode 100644 docs/system/riscv/sifive_u.rst diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst new file mode 100644 index 0000000000..98e7562848 --- /dev/null +++ b/docs/system/riscv/sifive_u.rst @@ -0,0 +1,336 @@ +SiFive HiFive Unleashed (``sifive_u``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +SiFive HiFive Unleashed Development Board is the ultimate RISC-V developme= nt +board featuring the Freedom U540 multi-core RISC-V processor. + +Supported devices +----------------- + +The ``sifive_u`` machine supports the following devices: + + * 1 E51 / E31 core + * Up to 4 U54 / U34 cores + * Core Level Interruptor (CLINT) + * Platform-Level Interrupt Controller (PLIC) + * Power, Reset, Clock, Interrupt (PRCI) + * L2 Loosely Integrated Memory (L2-LIM) + * DDR memory controller + * 2 UARTs + * 1 GEM Ethernet controller + * 1 GPIO controller + * 1 One-Time Programmable (OTP) memory with stored serial number + * 1 DMA controller + * 2 QSPI controllers + * 1 ISSI 25WP256 flash + * 1 SD card in SPI mode + +Please note the real world HiFive Unleashed board has a fixed configuratio= n of +1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit = mode. +With QEMU, one can create a machine with 1 E51 core and up to 4 U54 cores.= It +is also possible to create a 32-bit variant with the same peripherals exce= pt +that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to he= lp +testing of 32-bit guest software. + +Hardware configuration information +---------------------------------- + +The ``sifive_u`` machine automatically generates a device tree blob ("dtb") +which it passes to the guest. This provides information about the addresse= s, +interrupt lines and other configuration of the various devices in the syst= em. +Guest software should discover the devices that are present in the generat= ed +DTB instead of using a DTB for the real hardware, as some of the devices a= re +not modeled by QEMU and trying to access these devices may cause unexpected +behavior. + +Boot options +------------ + +The ``sifive_u`` machine can start using the standard -kernel functionality +for loading a Linux kernel, a VxWorks kernel, a modified U-Boot bootloader +(S-mode) or ELF executable with the default OpenSBI firmware image as the +-bios. It also supports booting the unmodified U-Boot bootloader using the +standard -bios functionality. + +Machine-specific options +------------------------ + +The following machine-specific options are supported: + +- serial=3Dnnn + + The board serial number. When not given, the default serial number 1 is = used. + + SiFive reserves the first 1 KiB of the 16 KiB OTP memory for internal us= e. + The current usage is only used to store the serial number of the board at + offset 0xfc. U-Boot reads the serial number from the OTP memory, and uses + it to generate a unique MAC address to be programmed to the on-chip GEM + Ethernet controller. When multiple QEMU ``sifive_u`` machines are created + and connected to the same subnet, they all have the same MAC address hen= ce + it creates an unusable network. In such scenario, user should give diffe= rent + values to serial=3D when creating different ``sifive_u`` machines. + +- start-in-flash + + When given, QEMU's ROM codes jump to QSPI memory-mapped flash directly. + Otherwise QEMU will jump to DRAM or L2LIM depending on the msel=3D value. + When not given, it defaults to direct DRAM booting. + +- msel=3D[6|11] + + Mode Select (MSEL[3:0]) pins value, used to control where to boot from. + + The FU540 SoC supports booting from several sources, which are controlled + using the Mode Select pins on the chip. Typically, the boot process runs + through several stages before it begins execution of user-provided progr= ams. + These stages typically include the following: + + 1. Zeroth Stage Boot Loader (ZSBL), which is contained in an on-chip mask + ROM and provided by QEMU. Note QEMU implemented ROM codes are not the + same as what is programmed in the hardware. The QEMU one is a simplif= ied + version, but it provides the same functionality as the hardware. + 2. First Stage Boot Loader (FSBL), which brings up PLLs and DDR memory. + This is U-Boot SPL. + 3. Second Stage Boot Loader (SSBL), which further initializes additional + peripherals as needed. This is U-Boot proper combined with an OpenSBI + fw_dynamic firmware image. + + msel=3D6 means FSBL and SSBL are both on the QSPI flash. msel=3D11 means= FSBL + and SSBL are both on the SD card. + +Running Linux kernel +-------------------- + +Linux mainline v5.10 release is tested at the time of writing. To build a +Linux mainline kernel that can be booted by the ``sifive_u`` machine in +64-bit mode, simply configure the kernel using the defconfig configuration: + +.. code-block:: bash + + $ export ARCH=3Driscv + $ export CROSS_COMPILE=3Driscv64-linux- + $ make defconfig + $ make + +To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -kernel arch/riscv/boot/Image \ + -initrd /path/to/rootfs.ext4 \ + -append "root=3D/dev/ram" + +To build a Linux mainline kernel that can be booted by the ``sifive_u`` ma= chine +in 32-bit mode, use the rv32_defconfig configuration. A patch is required = to +fix the 32-bit boot issue for Linux kernel v5.10. + +.. code-block:: bash + + $ export ARCH=3Driscv + $ export CROSS_COMPILE=3Driscv64-linux- + $ curl https://patchwork.kernel.org/project/linux-riscv/patch/2020121900= 1356.2887782-1-atish.patra@wdc.com/mbox/ > riscv.patch + $ git am riscv.patch + $ make rv32_defconfig + $ make + +Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command +line above to boot the 32-bit Linux kernel. A rootfs image containing 32-b= it +applications shall be used in order for kernel to boot to user space. + +Running VxWorks kernel +---------------------- + +VxWorks 7 SR0650 release is tested at the time of writing. To build a 64-b= it +VxWorks mainline kernel that can be booted by the ``sifive_u`` machine, si= mply +create a VxWorks source build project based on the sifive_generic BSP, and= a +VxWorks image project to generate the bootable VxWorks image, by following= the +BSP documentation instructions. + +A pre-built 64-bit VxWorks 7 image for HiFive Unleashed board is available= as +part of the VxWorks SDK for testing as well. Instructions to download the = SDK: + +.. code-block:: bash + + $ wget https://labs.windriver.com/downloads/wrsdk-vxworks7-sifive-hifive= -1.01.tar.bz2 + $ tar xvf wrsdk-vxworks7-sifive-hifive-1.01.tar.bz2 + $ ls bsps/sifive_generic_1_0_0_0/uboot/uVxWorks + +To boot the VxWorks kernel in QEMU with the ``sifive_u`` machine, use: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -nic tap,ifname=3Dtap0,script=3Dno,downscript=3Dno \ + -kernel /path/to/vxWorks \ + -append "gem(0,0)host:vxWorks h=3D192.168.200.1 e=3D192.168.200.2:ff= ffff00 u=3Dtarget pw=3DvxTarget f=3D0x01" + +It is also possible to test 32-bit VxWorks on the ``sifive_u`` machine. Cr= eate +a 32-bit project to build the 32-bit VxWorks image, and use exact the same +command line options with ``qemu-system-riscv32``. + +Running U-Boot +-------------- + +U-Boot mainline v2021.01 release is tested at the time of writing. To buil= d a +U-Boot mainline bootloader that can be booted by the ``sifive_u`` machine,= use +the sifive_fu540_defconfig with similar commands as described above for Li= nux: + +.. code-block:: bash + + $ export CROSS_COMPILE=3Driscv64-linux- + $ export OPENSBI=3D/path/to/opensbi-riscv64-generic-fw_dynamic.bin + $ make sifive_fu540_defconfig + +You will get spl/u-boot-spl.bin and u-boot.itb file in the build tree. + +To start U-Boot using the ``sifive_u`` machine, prepare an SPI flash image= , or +SD card image that is properly partitioned and populated with correct cont= ents. +genimage_ can be used to generate these images. + +A sample configuration file for a 128 MiB SD card image is: + +.. code-block:: bash + + $ cat genimage_sdcard.cfg + image sdcard.img { + size =3D 128M + + hdimage { + gpt =3D true + } + + partition u-boot-spl { + image =3D "u-boot-spl.bin" + offset =3D 17K + partition-type-uuid =3D 5B193300-FC78-40CD-8002-E86C4558= 0B47 + } + + partition u-boot { + image =3D "u-boot.itb" + offset =3D 1041K + partition-type-uuid =3D 2E54B353-1271-4842-806F-E436D6AF= 6985 + } + } + +SPI flash image has slightly different partition offsets, and the size has= to +be 32 MiB to match the ISSI 25WP256 flash on the real board: + +.. code-block:: bash + + $ cat genimage_spi-nor.cfg + image spi-nor.img { + size =3D 32M + + hdimage { + gpt =3D true + } + + partition u-boot-spl { + image =3D "u-boot-spl.bin" + offset =3D 20K + partition-type-uuid =3D 5B193300-FC78-40CD-8002-E86C4558= 0B47 + } + + partition u-boot { + image =3D "u-boot.itb" + offset =3D 1044K + partition-type-uuid =3D 2E54B353-1271-4842-806F-E436D6AF= 6985 + } + } + +Assume U-Boot binaries are put in the same directory as the config file, +we can generate the image by: + +.. code-block:: bash + + $ genimage --config genimage_.cfg --inputpath . + +Boot U-Boot from SD card, by specifying msel=3D11 and pass the SD card ima= ge +to QEMU ``sifive_u`` machine: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u,msel=3D11 -smp 5 -m 8G \ + -display none -serial stdio \ + -bios /path/to/u-boot-spl.bin \ + -drive file=3D/path/to/sdcard.img,if=3Dsd + +Changing msel=3D value to 6, allows booting U-Boot from the SPI flash: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u,msel=3D6 -smp 5 -m 8G \ + -display none -serial stdio \ + -bios /path/to/u-boot-spl.bin \ + -drive file=3D/path/to/spi-nor.img,if=3Dmtd + +Note when testing U-Boot, QEMU automatically generated device tree blob is +not used because U-Boot itself embeds device tree blobs for U-Boot SPL and +U-Boot proper. Hence the number of cores and size of memory have to match +the real hardware, ie: 5 cores (-smp 5) and 8 GiB memory (-m 8G). + +Above use case is to run upstream U-Boot for the SiFive HiFive Unleashed +board on QEMU ``sifive_u`` machine out of the box. This allows users to +develop and test the recommended RISC-V boot flow with a real world use +case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM, +then U-Boot SPL loads the combined payload image of OpenSBI fw_dynamic +firmware and U-Boot proper. However sometimes we want to have a quick test +of booting U-Boot on QEMU without the needs of preparing the SPI flash or +SD card images, an alternate way can be used, which is to create a U-Boot +S-mode image by modifying the configuration of U-Boot: + +.. code-block:: bash + + $ make menuconfig + +then manually select the following configuration in U-Boot: + + Device Tree Control > Provider of DTB for DT Control > Prior Stage bootl= oader DTB + +This lets U-Boot to use the QEMU generated device tree blob. During the bu= ild, +a build error will be seen below: + +.. code-block:: none + + MKIMAGE u-boot.img + ./tools/mkimage: Can't open arch/riscv/dts/hifive-unleashed-a00.dtb: No = such file or directory + ./tools/mkimage: failed to build FIT + make: *** [Makefile:1440: u-boot.img] Error 1 + +The above errors can be safely ignored as we don't run U-Boot SPL under QE= MU +in this alternate configuration. + +Boot the 64-bit U-Boot S-mode image directly: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -kernel /path/to/u-boot.bin + +It's possible to create a 32-bit U-Boot S-mode image as well. + +.. code-block:: bash + + $ export CROSS_COMPILE=3Driscv64-linux- + $ make sifive_fu540_defconfig + $ make menuconfig + +then manually update the following configuration in U-Boot: + + Device Tree Control > Provider of DTB for DT Control > Prior Stage bootl= oader DTB + RISC-V architecture > Base ISA > RV32I + Boot images > Text Base > 0x80400000 + +Use the same command line options to boot the 32-bit U-Boot S-mode image: + +.. code-block:: bash + + $ qemu-system-riscv32 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -kernel /path/to/u-boot.bin + +.. _genimage: https://github.com/pengutronix/genimage diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 9f4b7586e5..94d99c4c82 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -58,5 +58,15 @@ undocumented; you can get a complete list by running ``qemu-system-riscv64 --machine help``, or ``qemu-system-riscv32 --machine help``. =20 +.. + This table of contents should be kept sorted alphabetically + by the title text of each file, which isn't the same ordering + as an alphabetical sort by filename. + +.. toctree:: + :maxdepth: 1 + + riscv/sifive_u + RISC-V CPU features ------------------- --=20 2.25.1