From nobody Mon May 13 19:38:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) client-ip=209.85.208.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1611572303; cv=none; d=zohomail.com; s=zohoarc; b=gLmozIc5QLFkyoT/7KnWLHwaj+JMsph9B4UPLOcDJsyonlyAQg8gYqdulHRbOfg6WJ41kyoFJuIfGByDwVuxDLrTNBaWIgFkK3K5zljZXwdHWOcEh7R2j35GwkGqxSvjDowkFhcmXu32/qLJZ5snMchNLSh0YTHwtN4L+6U+l54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611572303; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:MIME-Version:Message-ID:Sender:Subject:To; bh=lVLd9SEatVayGs/dkKOOi0UqvIE17Oocj65I1xB5+CU=; b=gj+x9cwSllLTW+eOUmuE/Y3MUUoaf6ImsDEiOLaC+u5vKkC2se11paT6oDwArqq+y25IbIchFTtd8oofEtJjZYU4D9cGjqtvtUQbyGRG+DMu1gL0b+jJcrOj3qf60J6rwO2aiWpMqrqkqgdUjSNjC4M6LVLqd+8hKtM1orWMZcw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) by mx.zohomail.com with SMTPS id 1611572303026842.0628705405097; Mon, 25 Jan 2021 02:58:23 -0800 (PST) Received: by mail-ed1-f48.google.com with SMTP id bx12so14681346edb.8 for ; Mon, 25 Jan 2021 02:58:22 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id p16sm8171485ejz.103.2021.01.25.02.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 02:58:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lVLd9SEatVayGs/dkKOOi0UqvIE17Oocj65I1xB5+CU=; b=fZAYFE7gbjNMzz5EJBN9WdGDfPYo3KzSnyw9fOccinEMAtMF4eg6O7gbN2fvzdUYBB twu0wEs8Jl0VgApMvRYd/u5R9OGFmXUpaXzo/yuN+pm+7nyZhJnrl1yRcNNEQH7cfilY TVdiAYSotqtY8DyMaz5ybpS/dSVlJp8f2d7AKkMWySnrqoScH/652xuttGz3wZG3Layh BKG3l7F+C7bBPYDECzD2S77VtllWkjtLQsluvJFwsVBIa2QWB0teNQPksolSHcuR2VN4 A9i5MhGZElK/zDTReVQz6DkYXDWMZKyADXVl3QbFTR28HZr/hqZoSI8FAr54hWKBrE1L 6bCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=lVLd9SEatVayGs/dkKOOi0UqvIE17Oocj65I1xB5+CU=; b=GmxlIKb3KHcpmhnZ9DG2SQU6jO5I67/jJ0fI+pCD9rC750x8nzlAj7NPTd0Escdov7 lT3VptDg4UgHvPubzf77L+dIusy0kzYQkXLuj4MllC1J1U07BFP2LaXcU2rsZuQ8qkUI U94zVg60fUX2wKGEK4WJ/NXoDZlUJ3+ZsgvYdI9QbwHeU4bKUkernFDwa9mcpXE2q/Gp Tq2WRtDJng0cdKzh1Y0uaWjAHTPKvXsM5p3PEdQznJvXwi/cRM2Y2N730k9POtcFEDHT 4UIQ6AXYyRG+MklISfUnkdQVuxnB3srYQ3PcdnyhYv7Xl/qHRQvkgoylSWawUMFnyzws bv/w== X-Gm-Message-State: AOAM533TRwI+ucCqChK/FFZPRAkIMClapO/rbqt2MqE4GNGv7TuMMAO3 DIcP07jNTz3U9xmkkRNtr8M= X-Google-Smtp-Source: ABdhPJxBu3J6xw3MaUip2G5nDQ4BLLmkN9fE/x7KD/qqnfcscCN7gdmNZp33Tog63axi2NArfVH0HA== X-Received: by 2002:aa7:d94b:: with SMTP id l11mr319039eds.1.1611572301209; Mon, 25 Jan 2021 02:58:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jiaxun Yang , Aleksandar Rikalo , "Emilio G . Cota" , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2] target/mips: fetch code with translator_ld Date: Mon, 25 Jan 2021 11:58:18 +0100 Message-Id: <20210125105818.2707067-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Similarly to commits ae82adc8e29..7f93879e444, use the translator_ld*() API introduced in commit 409c1a0bf0f to fetch the code on the MIPS target. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2: Restrict to translator path =3D) --- target/mips/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a5cf1742a8b..a6e835809aa 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -26,7 +26,7 @@ #include "cpu.h" #include "internal.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "hw/semihosting/semihost.h" @@ -13911,7 +13911,7 @@ static void decode_i64_mips16(DisasContext *ctx, =20 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + int extend =3D translator_lduw(env, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; int16_t imm, offset; =20 @@ -14161,7 +14161,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + offset =3D translator_lduw(env, ctx->base.pc_next + 2); offset =3D (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; @@ -16295,7 +16295,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; =20 - insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + insn =3D translator_lduw(env, ctx->base.pc_next + 2); ctx->opcode =3D (ctx->opcode << 16) | insn; =20 rt =3D (ctx->opcode >> 21) & 0x1f; @@ -21350,7 +21350,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) int offset; int imm; =20 - insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + insn =3D translator_lduw(env, ctx->base.pc_next + 2); ctx->opcode =3D (ctx->opcode << 16) | insn; =20 rt =3D extract32(ctx->opcode, 21, 5); @@ -21469,7 +21469,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) break; case NM_P48I: { - insn =3D cpu_lduw_code(env, ctx->base.pc_next + 4); + insn =3D translator_lduw(env, ctx->base.pc_next + 4); target_long addr_off =3D extract32(ctx->opcode, 0, 16) | insn = << 16; switch (extract32(ctx->opcode, 16, 5)) { case NM_LI48: @@ -29087,17 +29087,17 @@ static void mips_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cs) =20 is_slot =3D ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); insn_bytes =3D decode_nanomips_opc(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_ldl(env, ctx->base.pc_next); insn_bytes =3D 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); insn_bytes =3D decode_micromips_opc(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); insn_bytes =3D decode_mips16_opc(env, ctx); } else { gen_reserved_instruction(ctx); --=20 2.26.2