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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id u17sm16189542wmj.35.2021.01.23.18.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 18:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vCib2bK8ZRs2GnL3ZDKcV/vqIXCDzjV3kKl0ikqzRig=; b=LLMgbORQec2Dr4WSi01vJWcBOvpgSpJQ2j3cj/NkQnSiXBP9kzw6HoB+MtzPw6zqVO gvftycDy3K+tD1XWM8vIR0Q/3NiggDJOnzpk1LOW8n6SlI8sDuqS/9kheDr335tPxOki BoCFY12rRUPOP9Jer+05qAkJpEWYxD0pj/trXJYNfTpuNygLws1vP65r7emrWeANfio4 TqU4lwf3NgjjuULU6miWOBI3GgzJ/aJXL4Zr/QmT7NNzTKxGnVn54I6NN26jwd5QSBdW 6WFDUc8UBk2cW89q7B6jAx7e/X+Qj8hNDbwJssNXVB5z8IkAbnGj+cJhItpLCXr1DeZd kV7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vCib2bK8ZRs2GnL3ZDKcV/vqIXCDzjV3kKl0ikqzRig=; b=S7AiAA+KVculMg+6ChsI+xhh91uZ2G/hgLH0Rt16IXiSMzsQMh6MslTxRR8+4JOlOH HfaAsLdurp/Q0ZNeMaxmCkNu7yK/DwrL02xVEjHGa5ptgbca+dFD92xYrezLo4w5bVNe VnTyzSCHavlvja2OnYu3k7eahtTDR5Tyok2CXPW2bUzv8eVsFflwtjlm2PfYYh5pnXdd 6+jAT6CgbRHmh8npzdFAGrD2ICNOj1dZKVRCi1QyLleDL5ZBMFq1rGvDJn5OZ9dwsU42 ASXfvYPAPwDRhrukH/xkw2hRrW6ecY+ImL06mg8LsAo/K3K0zBrny02yzbRyMjMsV6xT UsPQ== X-Gm-Message-State: AOAM530AwxhiQfiFTe2Ywmfg0pIKIRCcGMgsqLL09v0cxj2n6K9k1HWg fIuOxK/V7Bbne4Xu3b1C/yhxgA== X-Google-Smtp-Source: ABdhPJyNzHATEC8dTuxFUFwDmfDzPV0676+iaT56j2ywiTDUteFdiwPgkdyO690XmVXalsZNHW+2bg== X-Received: by 2002:a5d:6588:: with SMTP id q8mr1091823wru.294.1611456790038; Sat, 23 Jan 2021 18:53:10 -0800 (PST) From: Leif Lindholm To: qemu-arm@nongnu.org Subject: [RFC PATCH 2/4] hw/intc: add helper function to determine gicv3 redistributor size Date: Sun, 24 Jan 2021 02:53:04 +0000 Message-Id: <20210124025306.3949-3-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210124025306.3949-1-leif@nuviainc.com> References: <20210124025306.3949-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=leif@nuviainc.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Shashi Mallela , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" GICv3 sets aside 128K for each redistributor block, whereas GICv4 sets aside 256K. To enable use of the gicv3 model for gicv4, abstract this away as the helper function gicv3_redist_size() and replace the current hardcoded locations with calls to this function. Signed-off-by: Leif Lindholm Reviewed-by: Peter Maydell --- hw/intc/arm_gicv3_common.c | 2 +- hw/intc/arm_gicv3_redist.c | 13 +++++++++---- include/hw/intc/arm_gicv3_common.h | 3 +++ 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 7365d24873..a8510b39a1 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -299,7 +299,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_h= andler handler, =20 memory_region_init_io(&s->iomem_redist[i], OBJECT(s), ops ? &ops[1] : NULL, s, name, - s->redist_region_count[i] * GICV3_REDIST_SIZ= E); + s->redist_region_count[i] * gicv3_redist_siz= e(s)); sysbus_init_mmio(sbd, &s->iomem_redist[i]); g_free(name); } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 8645220d61..544f4d82ff 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -14,6 +14,11 @@ #include "trace.h" #include "gicv3_internal.h" =20 +int gicv3_redist_size(GICv3State *s) +{ + return (s->revision =3D=3D 3 ? GICV3_REDIST_SIZE : GICV4_REDIST_SIZE); +} + static uint32_t mask_group(GICv3CPUState *cs, MemTxAttrs attrs) { /* Return a 32-bit mask which should be applied for this set of 32 @@ -429,8 +434,8 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offs= et, uint64_t *data, * want to allow splitting of redistributor pages into several * blocks so we can support more CPUs. */ - cpuidx =3D offset / 0x20000; - offset %=3D 0x20000; + cpuidx =3D offset / gicv3_redist_size(s); + offset %=3D gicv3_redist_size(s); assert(cpuidx < s->num_cpu); =20 cs =3D &s->cpu[cpuidx]; @@ -486,8 +491,8 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr off= set, uint64_t data, * want to allow splitting of redistributor pages into several * blocks so we can support more CPUs. */ - cpuidx =3D offset / 0x20000; - offset %=3D 0x20000; + cpuidx =3D offset / gicv3_redist_size(s); + offset %=3D gicv3_redist_size(s); assert(cpuidx < s->num_cpu); =20 cs =3D &s->cpu[cpuidx]; diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 91491a2f66..ab88d14867 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -37,6 +37,7 @@ #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) =20 #define GICV3_REDIST_SIZE 0x20000 +#define GICV4_REDIST_SIZE (GICV3_REDIST_SIZE + 0x20000) =20 /* Number of SGI target-list bits */ #define GICV3_TARGETLIST_BITS 16 @@ -295,4 +296,6 @@ struct ARMGICv3CommonClass { void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, const MemoryRegionOps *ops, Error **errp); =20 +int gicv3_redist_size(GICv3State *s); + #endif --=20 2.20.1