From nobody Mon Feb 9 20:12:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1611405703; cv=none; d=zohomail.com; s=zohoarc; b=FH89690uJ2yop42E2DVbsIabIJk1CWStAjhqw0Otb/T+odoqGY0qSj7L5el8GGxG7X/Q77TUUTsk7wt/nvH/UZpmg/ThTPaYgYz1FYCoQqXV+JXGqdjOsKudBYIRELlQfLjhimSgNEvnBUznzfLdax+1sz9/lZlPvhaQFnMRle0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611405703; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ydsvi5ikONDSbX6xlvZJwLYOwrAMpKD6NRMW3cP1B+Q=; b=Fs17jSFxgn/CtAPTwTTlqgVTTpSBGj8nmMZ8Ma8VQw00ZfrRO3VGGiD6CeR9TvgwN9Ci7qGRjYOjQXOfDZdtpBHbyp6Th30xsR9LuocAc2XjBaXNNpn83UrlZljNX6oCZoQ13e3P2mUNFGSY/UvQiNgIM12HIZDkhOqTMn9JBl4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611405703093715.9869621295728; Sat, 23 Jan 2021 04:41:43 -0800 (PST) Received: from localhost ([::1]:33840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3IEX-0002Y8-Vq for importer@patchew.org; Sat, 23 Jan 2021 07:41:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3Hxt-0003Nb-Di for qemu-devel@nongnu.org; Sat, 23 Jan 2021 07:24:29 -0500 Received: from mx2.suse.de ([195.135.220.15]:59490) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3Hxn-00074O-PC for qemu-devel@nongnu.org; Sat, 23 Jan 2021 07:24:29 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 8C0AFAF32; Sat, 23 Jan 2021 12:24:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v13 14/22] cpu: move debug_check_watchpoint to tcg_ops Date: Sat, 23 Jan 2021 13:23:51 +0100 Message-Id: <20210123122359.4147-15-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210123122359.4147-1-cfontana@suse.de> References: <20210123122359.4147-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" commit 568496c0c0f1 ("cpu: Add callback to check architectural") and commit 3826121d9298 ("target-arm: Implement checking of fired") introduced an ARM-specific hack for cpu_check_watchpoint. Make debug_check_watchpoint optional, and move it to tcg_ops. Signed-off-by: Claudio Fontana --- include/hw/core/cpu.h | 9 ++++++--- accel/tcg/user-exec.c | 3 ++- hw/core/cpu.c | 9 --------- softmmu/physmem.c | 4 ++-- target/arm/cpu.c | 4 ++-- 5 files changed, 12 insertions(+), 17 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d6c6d32865..406e8a8606 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -143,6 +143,12 @@ typedef struct TcgCpuOperations { */ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); =20 + /** + * @debug_check_watchpoint: return true if the architectural + * watchpoint whose address has matched should really fire, used by ARM + */ + bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); + #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ =20 @@ -183,8 +189,6 @@ typedef struct TcgCpuOperations { * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @debug_check_watchpoint: Callback: return true if the architectural - * watchpoint whose address has matched should really fire. * @write_elf64_note: Callback for writing a CPU-specific ELF note to a * 64-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF @@ -238,7 +242,6 @@ struct CPUClass { int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); - bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); =20 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5509dd53e9..9e6e188d19 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -187,7 +187,8 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, clear_helper_retaddr(); =20 cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false= , pc); + cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, + MMU_USER_IDX, false, pc); g_assert_not_reached(); } =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 3d5bf9fe02..00330ba07d 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -186,14 +186,6 @@ static int cpu_common_gdb_write_register(CPUState *cpu= , uint8_t *buf, int reg) return 0; } =20 -static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint= *wp) -{ - /* If no extra check is required, QEMU watchpoint match can be conside= red - * as an architectural match. - */ - return true; -} - static bool cpu_common_virtio_is_big_endian(CPUState *cpu) { return target_words_bigendian(); @@ -415,7 +407,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; - k->debug_check_watchpoint =3D cpu_common_debug_check_watchpoint; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 1443621579..121ff36c88 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -917,8 +917,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, wp->hitaddr =3D MAX(addr, wp->vaddr); wp->hitattrs =3D attrs; if (!cpu->watchpoint_hit) { - if (wp->flags & BP_CPU && - !cc->debug_check_watchpoint(cpu, wp)) { + if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoi= nt && + !cc->tcg_ops.debug_check_watchpoint(cpu, wp)) { wp->flags &=3D ~BP_WATCHPOINT_HIT; continue; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2a14431065..c9a66d3103 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2280,12 +2280,12 @@ static void arm_cpu_class_init(ObjectClass *oc, voi= d *data) cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; cc->tcg_ops.debug_excp_handler =3D arm_debug_excp_handler; - cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; #if !defined(CONFIG_USER_ONLY) + cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; cc->tcg_ops.do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->tcg_ops.do_unaligned_access =3D arm_cpu_do_unaligned_access; cc->tcg_ops.adjust_watchpoint_address =3D arm_adjust_watchpoint_addres= s; - cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; + cc->tcg_ops.debug_check_watchpoint =3D arm_debug_check_watchpoint; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ } --=20 2.26.2