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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/33] target/arm: add arm_is_el2_enabled() helper
Date: Tue, 19 Jan 2021 15:10:36 +0000
Message-Id: <20210119151104.16264-6-peter.maydell@linaro.org>
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From: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
This checks if EL2 is enabled (meaning EL2 registers take effects) in
the current security context.
Signed-off-by: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-2-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f58aada4104..0bdda90914a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2148,6 +2148,18 @@ static inline bool arm_is_secure(CPUARMState *env)
return arm_is_secure_below_el3(env);
}
=20
+/*
+ * Return true if the current security state has AArch64 EL2 or AArch32 Hy=
p.
+ * This corresponds to the pseudocode EL2Enabled()
+ */
+static inline bool arm_is_el2_enabled(CPUARMState *env)
+{
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ return !arm_is_secure_below_el3(env);
+ }
+ return false;
+}
+
#else
static inline bool arm_is_secure_below_el3(CPUARMState *env)
{
@@ -2158,6 +2170,11 @@ static inline bool arm_is_secure(CPUARMState *env)
{
return false;
}
+
+static inline bool arm_is_el2_enabled(CPUARMState *env)
+{
+ return false;
+}
#endif
=20
/**
--=20
2.20.1