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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 21/33] target/arm: enable Secure EL2 in max CPU
Date: Tue, 19 Jan 2021 15:10:52 +0000
Message-Id: <20210119151104.16264-22-peter.maydell@linaro.org>
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From: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
Signed-off-by: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-18-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index dbd06ccc24c..5e851028c59 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -665,6 +665,7 @@ static void aarch64_max_initfn(Object *obj)
t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1);
t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
+ t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
cpu->isar.id_aa64pfr0 =3D t;
=20
t =3D cpu->isar.id_aa64pfr1;
--=20
2.20.1