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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/33] target/arm: Define isar_feature function to test for
presence of SEL2
Date: Tue, 19 Jan 2021 15:10:40 +0000
Message-Id: <20210119151104.16264-10-peter.maydell@linaro.org>
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From: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
Signed-off-by: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-6-remi.denis.courmont@huawei.com
[PMM: tweaked commit message to match reduced scope of patch
following rebase]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 66e36032949..22a3c8a4cfb 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4011,6 +4011,11 @@ static inline bool isar_feature_aa64_sve(const ARMIS=
ARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0;
}
=20
+static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0;
+}
+
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0;
--=20
2.20.1