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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.29; envelope-from=its@irrelevant.dk; helo=out5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Klaus Jensen , Stefan Hajnoczi , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen In the interest of supporting both CMB and PMR to be enabled on the same device, move the MSI-X table and pending bit array out of BAR 4 and into BAR 0. This is a simplified version of the patch contributed by Andrzej Jakowski (see [1]). Leaving the CMB at offset 0 removes the need for changes to CMB address mapping code. [1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-3-andrzej.ja= kowski@linux.intel.com/ Signed-off-by: Klaus Jensen Reviewed-by: Minwoo Im Tested-by: Minwoo Im --- hw/block/nvme.h | 1 + hw/block/nvme.c | 23 +++++++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 65540b650e1d..2a25bc84f3f9 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -126,6 +126,7 @@ typedef struct NvmeFeatureVal { =20 typedef struct NvmeCtrl { PCIDevice parent_obj; + MemoryRegion bar0; MemoryRegion iomem; MemoryRegion ctrl_mem; NvmeBar bar; diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 606006c549bc..ec2104fcf3b6 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -4230,6 +4230,8 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci= _dev) static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { uint8_t *pci_conf =3D pci_dev->config; + uint64_t bar_size, msix_table_size, msix_pba_size; + unsigned msix_table_offset, msix_pba_offset; int ret; =20 Error *err =3D NULL; @@ -4248,11 +4250,28 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev, Error **errp) pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); =20 + bar_size =3D QEMU_ALIGN_UP(n->reg_size, 4 * KiB); + msix_table_offset =3D bar_size; + msix_table_size =3D PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize; + + bar_size +=3D msix_table_size; + bar_size =3D QEMU_ALIGN_UP(bar_size, 4 * KiB); + msix_pba_offset =3D bar_size; + msix_pba_size =3D QEMU_ALIGN_UP(n->params.msix_qsize, 64) / 8; + + bar_size +=3D msix_pba_size; + bar_size =3D pow2ceil(bar_size); + + memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); + memory_region_add_subregion(&n->bar0, 0, &n->iomem); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | - PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - ret =3D msix_init_exclusive_bar(pci_dev, n->params.msix_qsize, 4, &err= ); + PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); + ret =3D msix_init(pci_dev, n->params.msix_qsize, + &n->bar0, 0, msix_table_offset, + &n->bar0, 0, msix_pba_offset, 0, &err); if (ret < 0) { if (ret =3D=3D -ENOTSUP) { warn_report_err(err); --=20 2.30.0