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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id t16sm17315602wmi.3.2021.01.16.10.13.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Jan 2021 10:13:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=5hkYxRzzzf/lZUMcVCjwrAkxVlbeEGk3O/gOAw0Gz6o=; b=b3wjStiRsgqSqKFj0IMMaqxaQzbjei8/nu4MH7Sy4OUTdGr452m58cZfTD+eFv+Nob W+1eZG5TLVHh/2pc+I//aMFDjabBEvQmoOrcawQ9ZoKE5Cy+gV80F7kQTTNi9q1nHqvb ehQweQa0za52TyLq1WnEm4qCrxQBqhPPfzda9Szp91/GHBgPwy2+soEjsf78LVj0IBnP 0UvZAcVcr/N8NVS3GdPRAuHHNGUHfjGnyCh875To8d8MB1IeUGXayDTOZDXeo18DT1OC oPdfG59WAc3jqMFPfVuAz4PN4DorBJCDuZbFfx+ZABzx2HcyavlmLCs7EWUZlBZX9yi0 agCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=5hkYxRzzzf/lZUMcVCjwrAkxVlbeEGk3O/gOAw0Gz6o=; b=VXL8M9/7GJI1GO+n08igcoAvaBj1ug8NJxkRQgKIL68OESPhYyhuicIYABQEchCn9B jlRn0SthNhcKq8sbmk0wKImxzaPlIXLXFEmSplMW/yJsqmNoFKYQzOeiaeFQNvKN+cUr s5LzRcfEYRdFTHAjZGW38k4qAiZ1l+u54fTLrkP1lCa331PSBzoo1cvUGmq2rScbYciD Nj67PfXncxMS++ryftGjLaA7it69n7J68UyfbXF5YIUzonLnXgarrlxEPDQCAmXjayNx msq/r8YKU7HJazpMUU97jz1NEgTORpqRd3tQUjrY7UqBdAkpoJ6ojdz21L3beP+lIYsS 9hYw== X-Gm-Message-State: AOAM531QSLC+NCd+VAWG33Ct7nPORkOuERbrrNPvp6PwkUnB0XQ2Yf+s T1E3FSb1xEtQuz5g3S0WjIs= X-Google-Smtp-Source: ABdhPJzxlsLx5h9vqp6irAi19uwBCmK2JxzxeitnOdl+hSVC6qINfxzAs6L0iJ9A4XPqqQMb7BIyyg== X-Received: by 2002:a5d:4683:: with SMTP id u3mr19020864wrq.19.1610820811017; Sat, 16 Jan 2021 10:13:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , "Emilio G . Cota" , Aleksandar Rikalo , Jiaxun Yang , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] target/mips: fetch code with translator_ld Date: Sat, 16 Jan 2021 19:13:28 +0100 Message-Id: <20210116181328.3890849-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Similarly to commits ae82adc8e29..7f93879e444, use the translator_ld*() API introduced in commit 409c1a0bf0f to fetch the code on the MIPS target. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang=C2=A0 --- target/mips/tlb_helper.c | 16 ++++++++-------- target/mips/translate.c | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 082c17928d3..f855453ca4d 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 @@ -526,9 +526,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, = int entry_size, return false; } if (entry_size =3D=3D 64) { - *pte =3D cpu_ldq_code(env, vaddr); + *pte =3D translator_ldq(env, vaddr); } else { - *pte =3D cpu_ldl_code(env, vaddr); + *pte =3D translator_ldl(env, vaddr); } return true; } @@ -941,14 +941,14 @@ static inline void set_badinstr_registers(CPUMIPSStat= e *env) { if (env->insn_flags & ISA_NANOMIPS32) { if (env->CP0_Config3 & (1 << CP0C3_BI)) { - uint32_t instr =3D (cpu_lduw_code(env, env->active_tc.PC)) << = 16; + uint32_t instr =3D (translator_lduw(env, env->active_tc.PC)) <= < 16; if ((instr & 0x10000000) =3D=3D 0) { - instr |=3D cpu_lduw_code(env, env->active_tc.PC + 2); + instr |=3D translator_lduw(env, env->active_tc.PC + 2); } env->CP0_BadInstr =3D instr; =20 if ((instr & 0xFC000000) =3D=3D 0x60000000) { - instr =3D cpu_lduw_code(env, env->active_tc.PC + 4) << 16; + instr =3D translator_lduw(env, env->active_tc.PC + 4) << 1= 6; env->CP0_BadInstrX =3D instr; } } @@ -960,11 +960,11 @@ static inline void set_badinstr_registers(CPUMIPSStat= e *env) return; } if (env->CP0_Config3 & (1 << CP0C3_BI)) { - env->CP0_BadInstr =3D cpu_ldl_code(env, env->active_tc.PC); + env->CP0_BadInstr =3D translator_ldl(env, env->active_tc.PC); } if ((env->CP0_Config3 & (1 << CP0C3_BP)) && (env->hflags & MIPS_HFLAG_BMASK)) { - env->CP0_BadInstrP =3D cpu_ldl_code(env, env->active_tc.PC - 4); + env->CP0_BadInstrP =3D translator_ldl(env, env->active_tc.PC - 4); } } =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index a5cf1742a8b..a6e835809aa 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -26,7 +26,7 @@ #include "cpu.h" #include "internal.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "hw/semihosting/semihost.h" @@ -13911,7 +13911,7 @@ static void decode_i64_mips16(DisasContext *ctx, =20 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + int extend =3D translator_lduw(env, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; int16_t imm, offset; =20 @@ -14161,7 +14161,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + offset =3D translator_lduw(env, ctx->base.pc_next + 2); offset =3D (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; @@ -16295,7 +16295,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; =20 - insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + insn =3D translator_lduw(env, ctx->base.pc_next + 2); ctx->opcode =3D (ctx->opcode << 16) | insn; =20 rt =3D (ctx->opcode >> 21) & 0x1f; @@ -21350,7 +21350,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) int offset; int imm; =20 - insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + insn =3D translator_lduw(env, ctx->base.pc_next + 2); ctx->opcode =3D (ctx->opcode << 16) | insn; =20 rt =3D extract32(ctx->opcode, 21, 5); @@ -21469,7 +21469,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) break; case NM_P48I: { - insn =3D cpu_lduw_code(env, ctx->base.pc_next + 4); + insn =3D translator_lduw(env, ctx->base.pc_next + 4); target_long addr_off =3D extract32(ctx->opcode, 0, 16) | insn = << 16; switch (extract32(ctx->opcode, 16, 5)) { case NM_LI48: @@ -29087,17 +29087,17 @@ static void mips_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cs) =20 is_slot =3D ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); insn_bytes =3D decode_nanomips_opc(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_ldl(env, ctx->base.pc_next); insn_bytes =3D 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); insn_bytes =3D decode_micromips_opc(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); insn_bytes =3D decode_mips16_opc(env, ctx); } else { gen_reserved_instruction(ctx); --=20 2.26.2