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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id k6sm3681616ejb.84.2021.01.15.07.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4fJWv7T8ni1UgNw8omgysewBjnwqG7EbsoSKPeXsii8=; b=lzifNm3cJxOPtWGXFvfLqIGNzR8hJHhy9rToFJfvGcE97KyWAgQnlDexulLCWYSjEd VwA/bcttwCqYYJJryfLNGVtyqGdV6xPaQdcNr+8nzKNHCO6nLojpqsQfim9mzsajXUbu xJ1Vrj1eA1P8YHHic+Enie56T79CIK6NjSGD5ET3CYWg3bp5sY4UZaXji23E3cEBMgG7 zIa3zouHEIDt0k+A0UIgPlJ31r//wokYZmx+cHEyAlPXl5uWi3OBj5froQzEff3RphoK mPH20NWxM4UClN5VoxzPwIW5eshFDV3TD8dQapL1/MD7AWvlflknqFyarNdQT1IoFY8C gvlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4fJWv7T8ni1UgNw8omgysewBjnwqG7EbsoSKPeXsii8=; b=fAnBcRRis0KO4wYJ8og/xMd/ZfcE8IkfdgMUIleXGfpi3Rb8MS8yq1+QGEhQut2DmG Ju2bSkO4hCCH8MUwu2phVwyo/TJgBD1WO5VmCVH79BFyzCEVGzxLBZg2iX0bHQ0vNJLF MIIpEyrBGBI4Grk1GAjZcmQYtj3wCUzeYC7RGog64HAqVR9GjuH7oHR++A1tTOPX3crD j1y5bCp2jNK34CZFvRoAgsrBlI3VYBiFP/hc3sDk0nOyvjlP88Lrzs027VQCl1fA2Hh+ J1y+5vG6Uqgq/SH4vPaNCSjQH9V+55wQg9vZ3ZcpmUxq2Yk+/pcvCzU5qTL0B8v0hhW7 vnUw== X-Gm-Message-State: AOAM532QgdaAWGJygwIpJvTb+UMMCgkj5T5kkDKYUFa164sQ2gKEZ/g3 FcdX2W9t8jqv9OPYW6cZdJo= X-Google-Smtp-Source: ABdhPJzZmXzxRol0w1xttkBVBhbTSTguYFnzG3SCxDBpOO2WQ86RWctTz2Zm/N0EmMRnnqpg8G7UKA== X-Received: by 2002:a17:906:aec6:: with SMTP id me6mr9090264ejb.542.1610724695528; Fri, 15 Jan 2021 07:31:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 8/9] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Fri, 15 Jan 2021 16:30:48 +0100 Message-Id: <20210115153049.3353008-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in secon= d word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in secon= d word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. =3D> sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, tota= l 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210112145526.31095-6-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index b79304d93d9..707defb8b3f 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -191,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) =20 DPRINTF("data tx:0x%08x\n", tx); =20 - tx_burst =3D MIN(s->burst_length, 32); + tx_burst =3D (s->burst_length % 32) ? : 32; =20 rx =3D 0; =20 --=20 2.26.2