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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id rl7sm3713330ejb.107.2021.01.15.07.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=55dYkHbl/cwpKN2kA/sZVcE4jjUL5RKiblFskzBR/GA=; b=LM0eThwHGM0htSwCiVS/1dNHnUU8+1cGq4s8BGwylgNVjgcWSt5LgHY+ANj3HSh8yJ sFHFdSdOVu6gssGcdGEt5YlPL17YTgZA4gSelQA79xe1koS7V4kxV+3oSimEOhuimGRK OC2VTHB7UJMCHxfrZMJxM+EBp+KfZil1kT9EVpflQGueoWWsKbcpCZMDXHSZRAMmw0jK edKC4TF80SwELmBR98tVjXs72Eti4ePqPeR7UIu28YaNj8w1KbpHHZ9JFSHhqd+44V0S KX0q2hm+ZwtJfd8zLvvHzD8M4cfPs9ESKBuXh0W2pypiSjKltD83HP7VrEmL/2VV4DMk 705A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=55dYkHbl/cwpKN2kA/sZVcE4jjUL5RKiblFskzBR/GA=; b=KM4Omc0CP+Ka0HzpKsAIg6N7V1AD5imqJXmpIj6RV8shl3Y5zye5Q3RjPk+7kCjdi2 CAMWZJ7g4YCVSKx5A2/QAX5leVpho6UDRenZR4d0xHJpgidZ1ycgJz6lTDMTEpm6qDAT m/AR80ccMPLTga+76Jei2FZilwdJC7kM4y0dCy1x58nJMegnAeVD1YOXEQZcaPuIH8n3 VQlHiP2riD3RduVHHip2/vyVlk05KEbBHsJIeeBZUKSP0FdWQyQiHYSMM5uEKqK0nr15 ppD//vLSALudQrWo2RD7WHU1cuA76sA+ci2aTD16qNfaVSi8G4Fc+IXplRFA5d2550sb aH3A== X-Gm-Message-State: AOAM531oKz6era27mJK34VcC44GpY5IZl5PCL0CkXW/d2dSA/cYeEDoq 6rLAq9fCXc0NkeM7HetGJvY= X-Google-Smtp-Source: ABdhPJzE2HLxi/PzuMR3uNE6yeTL2wjXoccf9fn/f7hQDo//uPoqL92nPqvIKAuqAzK+coYdt/O/RQ== X-Received: by 2002:a05:6402:5246:: with SMTP id t6mr10038334edd.62.1610724684744; Fri, 15 Jan 2021 07:31:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , Xuzhou Cheng , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 6/9] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Fri, 15 Jan 2021 16:30:46 +0100 Message-Id: <20210115153049.3353008-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ssi/imx_spi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index f06bbf317e2..c132f99ba5b 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -254,6 +254,10 @@ static void imx_spi_reset(DeviceState *dev) =20 imx_spi_update_irq(s); =20 + for (i =3D 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length =3D 0; } =20 --=20 2.26.2