From nobody Sun May 12 06:56:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1610674239; cv=none; d=zohomail.com; s=zohoarc; b=f/hE1Dbm9Y0vgEzb0CHxZTZkDO5ugSl9vXVJ9AruRERABUzGDy4r/HX0Fghh16TDIOmvXbpneqqMBFVA+yWb4w44h/cJ0kkk4YP967gP3wE2+y0be8SV94sT7WBwqaFFLs14BmATgrebSF9DryxMjvrqRPXhNxx/sAsNLGJbW8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610674239; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gJOpfYQ+3/ux5JjgNo5bdRGQSC7COkS1z8eg7Sv1OBE=; b=iC0rXojccpJxL20mYXspr1oeThFnhoKBWt1kxV/aJxiKc4pagdjCTBEKq5heneoyzg9S9RdqtP2TTRdY9klUFcdC0VE3VxEskAwSaMctujeQCP8oUEwXDtCIOfX6NUJjLqZg6K8AyGDWEuBIzTqKTvBi6GVusIBOCXMUlgWEQy4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610674239952669.6039265068833; Thu, 14 Jan 2021 17:30:39 -0800 (PST) Received: from localhost ([::1]:39494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l0Dwk-0006yw-DW for importer@patchew.org; Thu, 14 Jan 2021 20:30:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Dux-0006A6-PB; Thu, 14 Jan 2021 20:28:48 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:2638) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Dut-00029H-Ca; Thu, 14 Jan 2021 20:28:47 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4DH3Sx5h79z7VMM; Fri, 15 Jan 2021 09:27:29 +0800 (CST) Received: from huawei.com (10.174.186.236) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.498.0; Fri, 15 Jan 2021 09:28:24 +0800 From: Yifei Jiang To: , Subject: [PATCH v3 1/1] target-riscv: support QMP dump-guest-memory Date: Fri, 15 Jan 2021 09:28:19 +0800 Message-ID: <20210115012819.2053-2-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20210115012819.2053-1-jiangyifei@huawei.com> References: <20210115012819.2053-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.236] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=jiangyifei@huawei.com; helo=szxga07-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, limingwang@huawei.com, Yifei Jiang , Alistair.Francis@wdc.com, palmer@dabbelt.com, fanliang@huawei.com, wu.wubin@huawei.com, dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add the support needed for creating prstatus elf notes. Now elf notes only contains user_regs. This allows us to use QMP dump-guest-memory. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt --- target/riscv/arch_dump.c | 202 +++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.c | 2 + target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 1 + target/riscv/meson.build | 1 + 5 files changed, 210 insertions(+) create mode 100644 target/riscv/arch_dump.c diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c new file mode 100644 index 0000000000..6ad8f25920 --- /dev/null +++ b/target/riscv/arch_dump.c @@ -0,0 +1,202 @@ +/* Support for writing ELF notes for RISC-V architectures + * + * Copyright (C) 2020 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "elf.h" +#include "sysemu/dump.h" + +/* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */ +struct riscv64_user_regs { + uint64_t pc; + uint64_t regs[31]; +} QEMU_PACKED; + +QEMU_BUILD_BUG_ON(sizeof(struct riscv64_user_regs) !=3D 256); + +/* struct elf_prstatus from include/uapi/linux/elfcore.h */ +struct riscv64_elf_prstatus { + char pad1[32]; /* 32 =3D=3D offsetof(struct elf_prstatus, pr_pid) */ + uint32_t pr_pid; + char pad2[76]; /* 76 =3D=3D offsetof(struct elf_prstatus, pr_reg) - + offsetof(struct elf_prstatus, pr_ppid) */ + struct riscv64_user_regs pr_reg; + char pad3[8]; +} QEMU_PACKED; + +QEMU_BUILD_BUG_ON(sizeof(struct riscv64_elf_prstatus) !=3D 376); + +struct riscv64_note { + Elf64_Nhdr hdr; + char name[8]; /* align_up(sizeof("CORE"), 4) */ + struct riscv64_elf_prstatus prstatus; +} QEMU_PACKED; + +#define RISCV64_NOTE_HEADER_SIZE offsetof(struct riscv64_note, prstatus) +#define RISCV64_PRSTATUS_NOTE_SIZE \ + (RISCV64_NOTE_HEADER_SIZE + sizeof(struct riscv64_elf_prstatus= )) + +static void riscv64_note_init(struct riscv64_note *note, DumpState *s, + const char *name, Elf64_Word namesz, + Elf64_Word type, Elf64_Word descsz) +{ + memset(note, 0, sizeof(*note)); + + note->hdr.n_namesz =3D cpu_to_dump32(s, namesz); + note->hdr.n_descsz =3D cpu_to_dump32(s, descsz); + note->hdr.n_type =3D cpu_to_dump32(s, type); + + memcpy(note->name, name, namesz); +} + +int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, + int cpuid, void *opaque) +{ + struct riscv64_note note; + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + DumpState *s =3D opaque; + int ret, i =3D 0; + const char name[] =3D "CORE"; + + riscv64_note_init(¬e, s, name, sizeof(name), + NT_PRSTATUS, sizeof(note.prstatus)); + + note.prstatus.pr_pid =3D cpu_to_dump32(s, cpuid); + + note.prstatus.pr_reg.pc =3D cpu_to_dump64(s, env->pc); + + for (i =3D 0; i < 31; i++) { + note.prstatus.pr_reg.regs[i] =3D cpu_to_dump64(s, env->gpr[i + 1]); + } + + ret =3D f(¬e, RISCV64_PRSTATUS_NOTE_SIZE, s); + if (ret < 0) { + return -1; + } + + return ret; +} + +struct riscv32_user_regs { + uint32_t pc; + uint32_t regs[31]; +} QEMU_PACKED; + +QEMU_BUILD_BUG_ON(sizeof(struct riscv32_user_regs) !=3D 128); + +struct riscv32_elf_prstatus { + char pad1[24]; /* 24 =3D=3D offsetof(struct elf_prstatus, pr_pid) */ + uint32_t pr_pid; + char pad2[44]; /* 44 =3D=3D offsetof(struct elf_prstatus, pr_reg) - + offsetof(struct elf_prstatus, pr_ppid) */ + struct riscv32_user_regs pr_reg; + char pad3[4]; +} QEMU_PACKED; + +QEMU_BUILD_BUG_ON(sizeof(struct riscv32_elf_prstatus) !=3D 204); + +struct riscv32_note { + Elf32_Nhdr hdr; + char name[8]; /* align_up(sizeof("CORE"), 4) */ + struct riscv32_elf_prstatus prstatus; +} QEMU_PACKED; + +#define RISCV32_NOTE_HEADER_SIZE offsetof(struct riscv32_note, prstatus) +#define RISCV32_PRSTATUS_NOTE_SIZE \ + (RISCV32_NOTE_HEADER_SIZE + sizeof(struct riscv32_elf_prstatus= )) + +static void riscv32_note_init(struct riscv32_note *note, DumpState *s, + const char *name, Elf32_Word namesz, + Elf32_Word type, Elf32_Word descsz) +{ + memset(note, 0, sizeof(*note)); + + note->hdr.n_namesz =3D cpu_to_dump32(s, namesz); + note->hdr.n_descsz =3D cpu_to_dump32(s, descsz); + note->hdr.n_type =3D cpu_to_dump32(s, type); + + memcpy(note->name, name, namesz); +} + +int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, + int cpuid, void *opaque) +{ + struct riscv32_note note; + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + DumpState *s =3D opaque; + int ret, i; + const char name[] =3D "CORE"; + + riscv32_note_init(¬e, s, name, sizeof(name), + NT_PRSTATUS, sizeof(note.prstatus)); + + note.prstatus.pr_pid =3D cpu_to_dump32(s, cpuid); + + note.prstatus.pr_reg.pc =3D cpu_to_dump32(s, env->pc); + + for (i =3D 0; i < 31; i++) { + note.prstatus.pr_reg.regs[i] =3D cpu_to_dump32(s, env->gpr[i + 1]); + } + + ret =3D f(¬e, RISCV32_PRSTATUS_NOTE_SIZE, s); + if (ret < 0) { + return -1; + } + + return ret; +} + +int cpu_get_dump_info(ArchDumpInfo *info, + const GuestPhysBlockList *guest_phys_blocks) +{ + RISCVCPU *cpu; + CPURISCVState *env; + + if (first_cpu =3D=3D NULL) { + return -1; + } + cpu =3D RISCV_CPU(first_cpu); + env =3D &cpu->env; + + info->d_machine =3D EM_RISCV; + +#if defined(TARGET_RISCV64) + info->d_class =3D ELFCLASS64; +#else + info->d_class =3D ELFCLASS32; +#endif + + info->d_endian =3D (env->mstatus & MSTATUS_UBE) !=3D 0 + ? ELFDATA2MSB : ELFDATA2LSB; + + return 0; +} + +ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +{ + size_t note_size; + + if (class =3D=3D ELFCLASS64) { + note_size =3D RISCV64_PRSTATUS_NOTE_SIZE; + } else { + note_size =3D RISCV32_PRSTATUS_NOTE_SIZE; + } + + return note_size * nr_cpus; +} diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8227d7aea9..eebc35b53e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -591,6 +591,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; + cc->write_elf64_note =3D riscv_cpu_write_elf64_note; + cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif #ifdef CONFIG_TCG cc->tcg_initialize =3D riscv_translate_init; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6339e84819..2649949924 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -321,6 +321,10 @@ extern const char * const riscv_intr_names[]; =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); void riscv_cpu_do_interrupt(CPUState *cpu); +int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, + int cpuid, void *opaque); +int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, + int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b41e8836c3..24b2fa9b72 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -368,6 +368,7 @@ #define MSTATUS_MIE 0x00000008 #define MSTATUS_UPIE 0x00000010 #define MSTATUS_SPIE 0x00000020 +#define MSTATUS_UBE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 #define MSTATUS_MPP 0x00001800 diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 14a5c62dac..88ab850682 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -26,6 +26,7 @@ riscv_ss.add(files( =20 riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( + 'arch_dump.c', 'pmp.c', 'monitor.c', 'machine.c' --=20 2.19.1