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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 192 +++++++++++++++++++-------------------- 1 file changed, 92 insertions(+), 100 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0fd11264544..59bd196994f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1747,15 +1747,23 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) =20 static void tcg_out_epilogue(TCGContext *s); =20 -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2, a3, a4, a5; - int c; + int c, c2; + + /* Hoist the loads of the most common arguments. */ + a0 =3D args[0]; + a1 =3D args[1]; + a2 =3D args[2]; + a3 =3D args[3]; + c2 =3D const_args[2]; =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, a0); tcg_out_epilogue(s); break; case INDEX_op_goto_tb: @@ -1765,7 +1773,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, TCGReg base =3D TCG_REG_PC; =20 tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); - ptr =3D (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + ar= gs[0]); + ptr =3D (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0= ); dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; dil =3D sextract32(dif, 0, 12); if (dif !=3D dil) { @@ -1778,74 +1786,68 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, tcg_out_movi32(s, COND_AL, base, ptr - dil); } tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); - set_jmp_reset_offset(s, args[0]); + set_jmp_reset_offset(s, a0); } break; case INDEX_op_goto_ptr: - tcg_out_bx(s, COND_AL, args[0]); + tcg_out_bx(s, COND_AL, a0); break; case INDEX_op_br: - tcg_out_goto_label(s, COND_AL, arg_label(args[0])); + tcg_out_goto_label(s, COND_AL, arg_label(a0)); break; =20 case INDEX_op_ld8u_i32: - tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld8u(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld8s_i32: - tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld8s(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld16u_i32: - tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld16u(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld16s_i32: - tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld16s(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld_i32: - tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld32u(s, COND_AL, a0, a1, a2); break; case INDEX_op_st8_i32: - tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st8(s, COND_AL, a0, a1, a2); break; case INDEX_op_st16_i32: - tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st16(s, COND_AL, a0, a1, a2); break; case INDEX_op_st_i32: - tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st32(s, COND_AL, a0, a1, a2); break; =20 case INDEX_op_movcond_i32: /* Constraints mean that v2 is always in the same register as dest, * so we only need to do "if condition passed, move v1 to dest". */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a1, a2, c2); tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, - ARITH_MVN, args[0], 0, args[3], const_args[3]); + ARITH_MVN, a0, 0, a3, const_args[3]); break; case INDEX_op_add_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2, c2); break; case INDEX_op_sub_i32: if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + if (c2) { + tcg_out_movi32(s, COND_AL, a0, a1 - a2); } else { - tcg_out_dat_rI(s, COND_AL, ARITH_RSB, - args[0], args[2], args[1], 1); + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, a0, a2, a1, 1); } } else { - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, a0, a1, a2, = c2); } break; case INDEX_op_and_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2, c2); break; case INDEX_op_andc_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, a0, a1, a2, c2); break; case INDEX_op_or_i32: c =3D ARITH_ORR; @@ -1854,11 +1856,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, c =3D ARITH_EOR; /* Fall through. */ gen_arith: - tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_arg= s[2]); + tcg_out_dat_rI(s, COND_AL, c, a0, a1, a2, c2); break; case INDEX_op_add2_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; - a3 =3D args[3], a4 =3D args[4], a5 =3D args[5]; + a4 =3D args[4], a5 =3D args[5]; if (a0 =3D=3D a3 || (a0 =3D=3D a5 && !const_args[5])) { a0 =3D TCG_REG_TMP; } @@ -1866,15 +1867,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, a0, a2, a4, const_args[4]); tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, a1, a3, a5, const_args[5]); - tcg_out_mov_reg(s, COND_AL, args[0], a0); + tcg_out_mov_reg(s, COND_AL, a0, a0); break; case INDEX_op_sub2_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; - a3 =3D args[3], a4 =3D args[4], a5 =3D args[5]; + a4 =3D args[4], a5 =3D args[5]; if ((a0 =3D=3D a3 && !const_args[3]) || (a0 =3D=3D a5 && !const_ar= gs[5])) { a0 =3D TCG_REG_TMP; } - if (const_args[2]) { + if (c2) { if (const_args[4]) { tcg_out_movi32(s, COND_AL, a0, a4); a4 =3D a0; @@ -1884,7 +1884,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]= ); } - if (const_args[3]) { + if (const_a3) { if (const_args[5]) { tcg_out_movi32(s, COND_AL, a1, a5); a5 =3D a1; @@ -1894,69 +1894,64 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, a1, a3, a5, const_args[5]); } - tcg_out_mov_reg(s, COND_AL, args[0], a0); + tcg_out_mov_reg(s, COND_AL, a0, a0); break; case INDEX_op_neg_i32: - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a1, 0); break; case INDEX_op_not_i32: - tcg_out_dat_reg(s, COND_AL, - ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); + tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)= ); break; case INDEX_op_mul_i32: - tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); + tcg_out_mul32(s, COND_AL, a0, a1, a2); break; case INDEX_op_mulu2_i32: - tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_umull32(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_muls2_i32: - tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_smull32(s, COND_AL, a0, a1, a2, a3); break; - /* XXX: Perhaps args[2] & 0x1f is wrong */ + /* XXX: Perhaps a2 & 0x1f is wrong */ case INDEX_op_shl_i32: - c =3D const_args[2] ? - SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); + c =3D c2 ? SHIFT_IMM_LSL(a2 & 0x1f) : SHIFT_REG_LSL(a2); goto gen_shift32; case INDEX_op_shr_i32: - c =3D const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0= x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); + c =3D c2 ? (a2 & 0x1f) ? SHIFT_IMM_LSR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(a2); goto gen_shift32; case INDEX_op_sar_i32: - c =3D const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0= x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); + c =3D c2 ? (a2 & 0x1f) ? SHIFT_IMM_ASR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(a2); goto gen_shift32; case INDEX_op_rotr_i32: - c =3D const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0= x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); + c =3D c2 ? (a2 & 0x1f) ? SHIFT_IMM_ROR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(a2); /* Fall through. */ gen_shift32: - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, c); break; =20 case INDEX_op_rotl_i32: - if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], - ((0x20 - args[2]) & 0x1f) ? - SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : + if (c2) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, + ((0x20 - a2) & 0x1f) ? + SHIFT_IMM_ROR((0x20 - a2) & 0x1f) : SHIFT_IMM_LSL(0)); } else { - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0= x20); - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, a2, 0x20); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(TCG_REG_TMP)); } break; =20 case INDEX_op_ctz_i32: - tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); + tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); a1 =3D TCG_REG_TMP; goto do_clz; =20 case INDEX_op_clz_i32: - a1 =3D args[1]; do_clz: - a0 =3D args[0]; - a2 =3D args[2]; - c =3D const_args[2]; + c =3D c2; if (c && a2 =3D=3D 32) { tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); break; @@ -1970,17 +1965,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, =20 case INDEX_op_brcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[0], args[1], const_args[1]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], - arg_label(args[3])); + a0, a1, const_args[1]); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[a2], arg_label(a3)); break; case INDEX_op_setcond_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], - ARITH_MOV, args[0], 0, 0); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a1, a2, c2); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[a3], + ARITH_MOV, a0, 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(a3)], + ARITH_MOV, a0, 0, 0); break; =20 case INDEX_op_brcond2_i32: @@ -1989,9 +1982,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; case INDEX_op_setcond2_i32: c =3D tcg_out_cmp2(s, args + 1, const_args + 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0,= 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, a0, 0, 1); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], - ARITH_MOV, args[0], 0, 0); + ARITH_MOV, a0, 0, 0); break; =20 case INDEX_op_qemu_ld_i32: @@ -2008,63 +2001,62 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_bswap16_i32: - tcg_out_bswap16(s, COND_AL, args[0], args[1]); + tcg_out_bswap16(s, COND_AL, a0, a1); break; case INDEX_op_bswap32_i32: - tcg_out_bswap32(s, COND_AL, args[0], args[1]); + tcg_out_bswap32(s, COND_AL, a0, a1); break; =20 case INDEX_op_ext8s_i32: - tcg_out_ext8s(s, COND_AL, args[0], args[1]); + tcg_out_ext8s(s, COND_AL, a0, a1); break; case INDEX_op_ext16s_i32: - tcg_out_ext16s(s, COND_AL, args[0], args[1]); + tcg_out_ext16s(s, COND_AL, a0, a1); break; case INDEX_op_ext16u_i32: - tcg_out_ext16u(s, COND_AL, args[0], args[1]); + tcg_out_ext16u(s, COND_AL, a0, a1); break; =20 case INDEX_op_deposit_i32: - tcg_out_deposit(s, COND_AL, args[0], args[2], - args[3], args[4], const_args[2]); + tcg_out_deposit(s, COND_AL, a0, a2, a3, args[4], c2); break; case INDEX_op_extract_i32: - tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_extract(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_sextract_i32: - tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_sextract(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_extract2_i32: /* ??? These optimization vs zero should be generic. */ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. = */ if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); + if (c2) { + tcg_out_movi(s, TCG_TYPE_REG, a0, 0); } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, + a2, SHIFT_IMM_LSL(32 - a3)); } - } else if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[1], SHIFT_IMM_LSR(args[3])); + } else if (c2) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, + a1, SHIFT_IMM_LSR(a3)); } else { /* We can do extract2 in 2 insns, vs the 3 required otherwise.= */ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); - tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, - args[1], SHIFT_IMM_LSR(args[3])); + a2, SHIFT_IMM_LSL(32 - a3)); + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, TCG_REG_TMP, + a1, SHIFT_IMM_LSR(a3)); } break; =20 case INDEX_op_div_i32: - tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); + tcg_out_sdiv(s, COND_AL, a0, a1, a2); break; case INDEX_op_divu_i32: - tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); + tcg_out_udiv(s, COND_AL, a0, a1, a2); break; =20 case INDEX_op_mb: - tcg_out_mb(s, args[0]); + tcg_out_mb(s, a0); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.26.2 From nobody Sat Apr 20 11:51:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610558713; cv=none; d=zohomail.com; s=zohoarc; b=HeqefZswPa7rD0utaZ3MmhXEhrQbIqtHOn++4FkYBneprJXK4hM6Colgi/SfLCF2IfrFUC87iwE30VOJz/xxF4D//Kiwe7kZ25GyHq/4H8i0XVeyJaao4lK5MRaajNFc0d1ep8vGm7q0MrOe2v8Gwvww5dsFn/FMRJ8REwRmIYg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610558713; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=usrEFBYIAmEVHDsTWIk9Dyh2ylL3MFnazze4ohg6L4U=; b=F9GL1zAaMODGggYiq9m41p2QR46pdk20NKO2q/3J8eAqQlWrlRgGl3BkFl7WvnvATg+KaMYtQ7JDPh48hvqaLCQGw7ycGkIjLw/FqE6IC6gMcKAWOE8kVLUXrxKg+EEHefzBCVO/Ys4Ceu10ov9k29Y7AN+pMq09TcgSicAdWvw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 16105587137621008.2648264763174; Wed, 13 Jan 2021 09:25:13 -0800 (PST) Received: by mail-wm1-f52.google.com with SMTP id 3so2328461wmg.4 for ; Wed, 13 Jan 2021 09:25:13 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 59bd196994f..0ffb2b13d14 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1947,10 +1947,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ctz_i32: tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); a1 =3D TCG_REG_TMP; - goto do_clz; - + /* Fall through. */ case INDEX_op_clz_i32: - do_clz: c =3D c2; if (c && a2 =3D=3D 32) { tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); --=20 2.26.2 From nobody Sat Apr 20 11:51:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/ppc/tcg-target.c.inc | 188 ++++++++++++++++++--------------------- 1 file changed, 85 insertions(+), 103 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 19a4a12f155..70b747a8a30 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2357,15 +2357,22 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCLR | BO_ALWAYS); } =20 -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; - int c; + int c, c2; + + /* Hoist the loads of the most common arguments. */ + a0 =3D args[0]; + a1 =3D args[1]; + a2 =3D args[2]; + c2 =3D const_args[2]; =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, a0); tcg_out_b(s, 0, tcg_code_gen_epilogue); break; case INDEX_op_goto_tb: @@ -2389,11 +2396,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, /* Indirect jump. */ tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D NULL); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, - (intptr_t)(s->tb_jmp_insn_offset + args[0])); + (intptr_t)(s->tb_jmp_insn_offset + a0)); } tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); - set_jmp_reset_offset(s, args[0]); + set_jmp_reset_offset(s, a0); if (USE_REG_TB) { /* For the unlinked case, need to reset TCG_REG_TB. */ tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, @@ -2403,7 +2410,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, case INDEX_op_goto_ptr: tcg_out32(s, MTSPR | RS(args[0]) | CTR); if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); tcg_out32(s, BCCTR | BO_ALWAYS); @@ -2424,49 +2431,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, break; case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2); break; case INDEX_op_ld8s_i32: case INDEX_op_ld8s_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2); tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0])); break; case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i64: - tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LHZ, LHZX, a0, a1, a2); break; case INDEX_op_ld16s_i32: case INDEX_op_ld16s_i64: - tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LHA, LHAX, a0, a1, a2); break; case INDEX_op_ld_i32: case INDEX_op_ld32u_i64: - tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LWZ, LWZX, a0, a1, a2); break; case INDEX_op_ld32s_i64: - tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LWA, LWAX, a0, a1, a2); break; case INDEX_op_ld_i64: - tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LD, LDX, a0, a1, a2); break; case INDEX_op_st8_i32: case INDEX_op_st8_i64: - tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STB, STBX, a0, a1, a2); break; case INDEX_op_st16_i32: case INDEX_op_st16_i64: - tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STH, STHX, a0, a1, a2); break; case INDEX_op_st_i32: case INDEX_op_st32_i64: - tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STW, STWX, a0, a1, a2); break; case INDEX_op_st_i64: - tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STD, STDX, a0, a1, a2); break; =20 case INDEX_op_add_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { do_addi_32: tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); @@ -2475,7 +2481,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } break; case INDEX_op_sub_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[1]) { if (const_args[2]) { tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); @@ -2491,7 +2496,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; =20 case INDEX_op_and_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_andi32(s, a0, a1, a2); } else { @@ -2499,7 +2503,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } break; case INDEX_op_and_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_andi64(s, a0, a1, a2); } else { @@ -2508,7 +2511,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; case INDEX_op_or_i64: case INDEX_op_or_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_ori32(s, a0, a1, a2); } else { @@ -2517,7 +2519,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; case INDEX_op_xor_i64: case INDEX_op_xor_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_xori32(s, a0, a1, a2); } else { @@ -2525,7 +2526,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } break; case INDEX_op_andc_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_andi32(s, a0, a1, ~a2); } else { @@ -2533,7 +2533,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } break; case INDEX_op_andc_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_andi64(s, a0, a1, ~a2); } else { @@ -2542,57 +2541,52 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, break; case INDEX_op_orc_i32: if (const_args[2]) { - tcg_out_ori32(s, args[0], args[1], ~args[2]); + tcg_out_ori32(s, a0, a1, ~args[2]); break; } /* FALLTHRU */ case INDEX_op_orc_i64: - tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); + tcg_out32(s, ORC | SAB(args[1], a0, a2)); break; case INDEX_op_eqv_i32: if (const_args[2]) { - tcg_out_xori32(s, args[0], args[1], ~args[2]); + tcg_out_xori32(s, a0, a1, ~args[2]); break; } /* FALLTHRU */ case INDEX_op_eqv_i64: - tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); + tcg_out32(s, EQV | SAB(args[1], a0, a2)); break; case INDEX_op_nand_i32: case INDEX_op_nand_i64: - tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); + tcg_out32(s, NAND | SAB(args[1], a0, a2)); break; case INDEX_op_nor_i32: case INDEX_op_nor_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); + tcg_out32(s, NOR | SAB(args[1], a0, a2)); break; =20 case INDEX_op_clz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, a0, a1, a2, const_args[2]); break; case INDEX_op_ctz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, a0, a1, a2, const_args[2]); break; case INDEX_op_ctpop_i32: - tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); + tcg_out32(s, CNTPOPW | SAB(args[1], a0, 0)); break; =20 case INDEX_op_clz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, a0, a1, a2, const_args[2]); break; case INDEX_op_ctz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, a0, a1, a2, const_args[2]); break; case INDEX_op_ctpop_i64: - tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); + tcg_out32(s, CNTPOPD | SAB(args[1], a0, 0)); break; =20 case INDEX_op_mul_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out32(s, MULLI | TAI(a0, a1, a2)); } else { @@ -2601,27 +2595,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, break; =20 case INDEX_op_div_i32: - tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVW | TAB(args[0], a1, a2)); break; =20 case INDEX_op_divu_i32: - tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVWU | TAB(args[0], a1, a2)); break; =20 case INDEX_op_shl_i32: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn.= */ - tcg_out_shli32(s, args[0], args[1], args[2] & 31); + tcg_out_shli32(s, a0, a1, a2 & 31); } else { - tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SLW | SAB(args[1], a0, a2)); } break; case INDEX_op_shr_i32: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn.= */ - tcg_out_shri32(s, args[0], args[1], args[2] & 31); + tcg_out_shri32(s, a0, a1, a2 & 31); } else { - tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRW | SAB(args[1], a0, a2)); } break; case INDEX_op_sar_i32: @@ -2629,33 +2623,32 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, /* Limit immediate shift count lest we create an illegal insn.= */ tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & = 31)); } else { - tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRAW | SAB(args[1], a0, a2)); } break; case INDEX_op_rotl_i32: if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); + tcg_out_rlw(s, RLWINM, a0, a1, a2, 0, 31); } else { - tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) + tcg_out32(s, RLWNM | SAB(args[1], a0, a2) | MB(0) | ME(31)); } break; case INDEX_op_rotr_i32: if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); + tcg_out_rlw(s, RLWINM, a0, a1, 32 - a2, 0, 31); } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); - tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) - | MB(0) | ME(31)); + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, a2, 32)); + tcg_out32(s, RLWNM | SAB(args[1], a0, TCG_REG_R0) | MB(0) | ME= (31)); } break; =20 case INDEX_op_brcond_i32: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], + tcg_out_brcond(s, a2, a0, a1, const_args[1], arg_label(args[3]), TCG_TYPE_I32); break; case INDEX_op_brcond_i64: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], + tcg_out_brcond(s, a2, a0, a1, const_args[1], arg_label(args[3]), TCG_TYPE_I64); break; case INDEX_op_brcond2_i32: @@ -2669,11 +2662,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, =20 case INDEX_op_not_i32: case INDEX_op_not_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); + tcg_out32(s, NOR | SAB(args[1], a0, a1)); break; =20 case INDEX_op_add_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { do_addi_64: tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); @@ -2682,7 +2674,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } break; case INDEX_op_sub_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[1]) { if (const_args[2]) { tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); @@ -2700,17 +2691,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, case INDEX_op_shl_i64: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn.= */ - tcg_out_shli64(s, args[0], args[1], args[2] & 63); + tcg_out_shli64(s, a0, a1, a2 & 63); } else { - tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SLD | SAB(args[1], a0, a2)); } break; case INDEX_op_shr_i64: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn.= */ - tcg_out_shri64(s, args[0], args[1], args[2] & 63); + tcg_out_shri64(s, a0, a1, a2 & 63); } else { - tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRD | SAB(args[1], a0, a2)); } break; case INDEX_op_sar_i64: @@ -2718,27 +2709,26 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, int sh =3D SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh); } else { - tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRAD | SAB(args[1], a0, a2)); } break; case INDEX_op_rotl_i64: if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); + tcg_out_rld(s, RLDICL, a0, a1, a2, 0); } else { - tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); + tcg_out32(s, RLDCL | SAB(args[1], a0, a2) | MB64(0)); } break; case INDEX_op_rotr_i64: if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); + tcg_out_rld(s, RLDICL, a0, a1, 64 - a2, 0); } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); - tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(= 0)); + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, a2, 64)); + tcg_out32(s, RLDCL | SAB(args[1], a0, TCG_REG_R0) | MB64(0)); } break; =20 case INDEX_op_mul_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out32(s, MULLI | TAI(a0, a1, a2)); } else { @@ -2746,10 +2736,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, } break; case INDEX_op_div_i64: - tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVD | TAB(args[0], a1, a2)); break; case INDEX_op_divu_i64: - tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVDU | TAB(args[0], a1, a2)); break; =20 case INDEX_op_qemu_ld_i32: @@ -2781,16 +2771,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, tcg_out32(s, c | RS(args[1]) | RA(args[0])); break; case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, args[0], args[1]); + tcg_out_ext32u(s, a0, a1); break; =20 case INDEX_op_setcond_i32: - tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2= ], - const_args[2]); + tcg_out_setcond(s, TCG_TYPE_I32, args[3], a0, a1, a2, const_args[2= ]); break; case INDEX_op_setcond_i64: - tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2= ], - const_args[2]); + tcg_out_setcond(s, TCG_TYPE_I64, args[3], a0, a1, a2, const_args[2= ]); break; case INDEX_op_setcond2_i32: tcg_out_setcond2(s, args, const_args); @@ -2798,7 +2786,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: - a0 =3D args[0], a1 =3D args[1]; /* a1 =3D abcd */ if (a0 !=3D a1) { /* a0 =3D (a1 r<< 24) & 0xff # 000c */ @@ -2818,7 +2805,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: /* Stolen from gcc's builtin_bswap32 */ - a1 =3D args[1]; a0 =3D args[0] =3D=3D a1 ? TCG_REG_R0 : args[0]; =20 /* a1 =3D args[1] # abcd */ @@ -2835,7 +2821,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; =20 case INDEX_op_bswap64_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D TCG_REG_R0; + a2 =3D TCG_REG_R0; if (a0 =3D=3D a1) { a0 =3D TCG_REG_R0; a2 =3D a1; @@ -2869,36 +2855,34 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, case INDEX_op_deposit_i32: if (const_args[2]) { uint32_t mask =3D ((2u << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi32(s, args[0], args[0], ~mask); + tcg_out_andi32(s, a0, a0, ~mask); } else { - tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], + tcg_out_rlw(s, RLWIMI, a0, a2, args[3], 32 - args[3] - args[4], 31 - args[3]); } break; case INDEX_op_deposit_i64: if (const_args[2]) { uint64_t mask =3D ((2ull << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi64(s, args[0], args[0], ~mask); + tcg_out_andi64(s, a0, a0, ~mask); } else { - tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], - 64 - args[3] - args[4]); + tcg_out_rld(s, RLDIMI, a0, a2, args[3], 64 - args[3] - args[4]= ); } break; =20 case INDEX_op_extract_i32: - tcg_out_rlw(s, RLWINM, args[0], args[1], - 32 - args[2], 32 - args[3], 31); + tcg_out_rlw(s, RLWINM, a0, a1, 32 - a2, 32 - args[3], 31); break; case INDEX_op_extract_i64: - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3= ]); + tcg_out_rld(s, RLDICL, a0, a1, 64 - a2, 64 - args[3]); break; =20 case INDEX_op_movcond_i32: - tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2= ], + tcg_out_movcond(s, TCG_TYPE_I32, args[5], a0, a1, a2, args[3], args[4], const_args[2]); break; case INDEX_op_movcond_i64: - tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2= ], + tcg_out_movcond(s, TCG_TYPE_I64, args[5], a0, a1, a2, args[3], args[4], const_args[2]); break; =20 @@ -2910,14 +2894,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, /* Note that the CA bit is defined based on the word size of the environment. So in 64-bit mode it's always carry-out of bit 63. The fallback code using deposit works just as well for 32-bit. = */ - a0 =3D args[0], a1 =3D args[1]; if (a0 =3D=3D args[3] || (!const_args[5] && a0 =3D=3D args[5])) { a0 =3D TCG_REG_R0; } if (const_args[4]) { - tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); + tcg_out32(s, ADDIC | TAI(a0, a2, args[4])); } else { - tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); + tcg_out32(s, ADDC | TAB(a0, a2, args[4])); } if (const_args[5]) { tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); @@ -2934,14 +2917,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, #else case INDEX_op_sub2_i32: #endif - a0 =3D args[0], a1 =3D args[1]; if (a0 =3D=3D args[5] || (!const_args[3] && a0 =3D=3D args[3])) { a0 =3D TCG_REG_R0; } if (const_args[2]) { - tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); + tcg_out32(s, SUBFIC | TAI(a0, args[4], a2)); } else { - tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); + tcg_out32(s, SUBFC | TAB(a0, args[4], a2)); } if (const_args[3]) { tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]= )); @@ -2954,20 +2936,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, break; =20 case INDEX_op_muluh_i32: - tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHWU | TAB(args[0], a1, a2)); break; case INDEX_op_mulsh_i32: - tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHW | TAB(args[0], a1, a2)); break; case INDEX_op_muluh_i64: - tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHDU | TAB(args[0], a1, a2)); break; case INDEX_op_mulsh_i64: - tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHD | TAB(args[0], a1, a2)); break; =20 case INDEX_op_mb: - tcg_out_mb(s, args[0]); + tcg_out_mb(s, a0); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.26.2 From nobody Sat Apr 20 11:51:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610558724; cv=none; d=zohomail.com; s=zohoarc; b=fSpxdfMpzcXN3DgXjOAAIcSu67wEhgXlkQj2eK+jcl1KmKhp6WrpHju3dFVpJVbK1jrfgYakw59vyIbUrVqVI1Y+SGHXcJTVJW/hfqaTY03lYTvKGhoVi54zuFYqG15+Zj0xkqYqhFkfYc3IWJlcK4Wk1AhQnzJVijwuKCOiiZQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610558724; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zq1vr3q6gndSZYUaWX6IMZKeocghiG32Kg2SuEHDROY=; b=FySYPVA9yisgIZANjJ4NbYHUnggj0iWYXtR1K02Zh5NY2bcaIFpGRjCFQGf7pOKt8l1w5Y7HdMnUuiLhhJBQXnAvgC0w27jdu+z57Lrl1OGIkZYhDSCED7U29/HBxHNGymz3gS04quG55hi2r7ysGa1nudQWnnnMVsry/JxUENI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.zohomail.com with SMTPS id 161055872459230.927294955168577; Wed, 13 Jan 2021 09:25:24 -0800 (PST) Received: by mail-wm1-f44.google.com with SMTP id i63so2306712wma.4 for ; Wed, 13 Jan 2021 09:25:23 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id s19sm1013485wrf.72.2021.01.13.09.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Zq1vr3q6gndSZYUaWX6IMZKeocghiG32Kg2SuEHDROY=; b=QbnLjn+k8wPIgmq7eclVXhR7pKsm67tcS6AbdCJF3750mVlN+akp1RPOKfHTZmhOxO hueb4D4BnU93a3O75Hi+faT/CxNyALcKQd1JXlvbZSdiudiftbMyqBNux3YZWbg4wOZZ ZZPtfDV+qCOd2Io8hb29qqUkUtCGvtfxrgIoHpvBf4b5sEZ3YAxNomr8hnqv8Wt5CHsE Kl2W7vZmBHoAV1WVaCq9JVQ2CxNFA0aPujMnuKvPI2W47lgQr/j8QD/61zJ2Nzrqk2kP NHCbrdrwj2GBtapYj8iIpN3bhMY39wQUUyM5Us3krNZjucFEfr0M/3lAJ0CS7BOD1rq2 cBtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Zq1vr3q6gndSZYUaWX6IMZKeocghiG32Kg2SuEHDROY=; b=RJyTuOo4kNmFvdDRIow4iql3iSP83fn+4rhhhze/YGs+pQjoFTdB4Ye9d2OCGjwZSu nm5UgMyCFiECjIlH2rBJcB8I+duv4iqXBwUVo07S75HbOZGJzPCkUdfACVewiSaqMIjU NVykc7lSIPJDQdCIMqYGi7ztu24cq7GdGSUWeQoUTfrUjCOMZNpT/5qGwF5wxZr6SixQ Lxg15AS8/TrfRQdOQNkI6PxMJkit2MyFbawYvHG27HpVTu7Pesrh32mKlkBKX3ukr2XP UndEIiOinnOvwSsyaDyliVhyw0MqQt9OtJ0jg5bukBFocKvTIK49wAXfOM2C/U7c7T6C F/2A== X-Gm-Message-State: AOAM530V8V8HXYXpniTHrUczG0z/LXNRWiyn/ZGbalAnGHjPOPuUxXZc N0vrY5bL83XXTprE1BlsQnc= X-Google-Smtp-Source: ABdhPJxDqIRMWT+0VphR7aasWzGWhf4ZAl+ewm1Zz6UCJU7uHqNstOyHD8XDWTjeFiKRngan5h30ow== X-Received: by 2002:a1c:3d86:: with SMTP id k128mr296155wma.66.1610558722601; Wed, 13 Jan 2021 09:25:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 4/6] tcg/s390: Hoist common argument loads in tcg_out_op() Date: Wed, 13 Jan 2021 18:24:57 +0100 Message-Id: <20210113172459.2481060-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/s390/tcg-target.c.inc | 222 ++++++++++++++++++-------------------- 1 file changed, 107 insertions(+), 115 deletions(-) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index d7ef0790556..ec202e79cfc 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1732,15 +1732,22 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg d= ata_reg, TCGReg addr_reg, case glue(glue(INDEX_op_,x),_i64) =20 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { S390Opcode op, op2; - TCGArg a0, a1, a2; + TCGArg a0, a1, a2, a4; + int c2; + + a0 =3D args[0]; + a1 =3D args[1]; + a2 =3D args[2]; + a4 =3D args[4]; + c2 =3D const_args[2]; =20 switch (opc) { case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ - a0 =3D args[0]; if (a0 =3D=3D 0) { tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); } else { @@ -1750,7 +1757,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; =20 case INDEX_op_goto_tb: - a0 =3D args[0]; if (s->tb_jmp_insn_offset) { /* * branch displacement must be aligned for atomic patching; @@ -1784,7 +1790,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; =20 case INDEX_op_goto_ptr: - a0 =3D args[0]; if (USE_REG_TB) { tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } @@ -1794,44 +1799,42 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, OP_32_64(ld8u): /* ??? LLC (RXY format) is only present with the extended-immediate facility, whereas LLGC is always present. */ - tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2= ]); + tcg_out_mem(s, 0, RXY_LLGC, a0, a1, TCG_REG_NONE, a2); break; =20 OP_32_64(ld8s): /* ??? LB is no smaller than LGB, so no point to using it. */ - tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]= ); + tcg_out_mem(s, 0, RXY_LGB, a0, a1, TCG_REG_NONE, a2); break; =20 OP_32_64(ld16u): /* ??? LLH (RXY format) is only present with the extended-immediate facility, whereas LLGH is always present. */ - tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2= ]); + tcg_out_mem(s, 0, RXY_LLGH, a0, a1, TCG_REG_NONE, a2); break; =20 case INDEX_op_ld16s_i32: - tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, arg= s[2]); + tcg_out_mem(s, RX_LH, RXY_LHY, a0, a1, TCG_REG_NONE, a2); break; =20 case INDEX_op_ld_i32: - tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); break; =20 OP_32_64(st8): - tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_STC, RXY_STCY, a0, a1, TCG_REG_NONE, a2); break; =20 OP_32_64(st16): - tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_STH, RXY_STHY, a0, a1, TCG_REG_NONE, a2); break; =20 case INDEX_op_st_i32: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); break; =20 case INDEX_op_add_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; + a2 =3D (int32_t)args[2]; if (const_args[2]) { do_addi_32: if (a0 =3D=3D a1) { @@ -1852,9 +1855,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; case INDEX_op_sub_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; + a2 =3D (int32_t)args[2]; if (const_args[2]) { - a2 =3D -a2; + a2 =3D -args[2]; goto do_addi_32; } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, SR, a0, a2); @@ -1864,7 +1867,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; =20 case INDEX_op_and_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; + a2 =3D (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_andi(s, TCG_TYPE_I32, a0, a2); @@ -1875,7 +1878,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; case INDEX_op_or_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; + a2 =3D (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_ori(s, TCG_TYPE_I32, a0, a2); @@ -1886,45 +1889,45 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } break; case INDEX_op_xor_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; + a2 =3D (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_xori(s, TCG_TYPE_I32, a0, a2); } else if (a0 =3D=3D a1) { - tcg_out_insn(s, RR, XR, args[0], args[2]); + tcg_out_insn(s, RR, XR, a0, a2); } else { tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; =20 case INDEX_op_neg_i32: - tcg_out_insn(s, RR, LCR, args[0], args[1]); + tcg_out_insn(s, RR, LCR, a0, a1); break; =20 case INDEX_op_mul_i32: if (const_args[2]) { if ((int32_t)args[2] =3D=3D (int16_t)args[2]) { - tcg_out_insn(s, RI, MHI, args[0], args[2]); + tcg_out_insn(s, RI, MHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSFI, a0, a2); } } else { - tcg_out_insn(s, RRE, MSR, args[0], args[2]); + tcg_out_insn(s, RRE, MSR, a0, a2); } break; =20 case INDEX_op_div2_i32: - tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RR, DR, TCG_REG_R2, a4); break; case INDEX_op_divu2_i32: - tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RRE, DLR, TCG_REG_R2, a4); break; =20 case INDEX_op_shl_i32: op =3D RS_SLL; op2 =3D RSY_SLLK; do_shift32: - a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; + a2 =3D (int32_t)args[2]; if (a0 =3D=3D a1) { if (const_args[2]) { tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); @@ -1952,110 +1955,107 @@ static inline void tcg_out_op(TCGContext *s, TCGO= pcode opc, case INDEX_op_rotl_i32: /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol.= */ if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[= 2]); + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); + tcg_out_sh64(s, RSY_RLL, a0, a1, a2, 0); } break; case INDEX_op_rotr_i32: if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], - TCG_REG_NONE, (32 - args[2]) & 31); + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_REG_NONE, (32 - a2) & 31); } else { - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_TMP0, 0); } break; =20 case INDEX_op_ext8s_i32: - tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext8s(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext16s_i32: - tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext16s(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext8u_i32: - tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext8u(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext16u_i32: - tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext16u(s, TCG_TYPE_I32, a0, a1); break; =20 OP_32_64(bswap16): /* The TCG bswap definition requires bits 0-47 already be zero. Thus we don't need the G-type insns to implement bswap16_i64. = */ - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); - tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16); + tcg_out_insn(s, RRE, LRVR, a0, a1); + tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); break; OP_32_64(bswap32): - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); + tcg_out_insn(s, RRE, LRVR, a0, a1); break; =20 case INDEX_op_add2_i32: if (const_args[4]) { - tcg_out_insn(s, RIL, ALFI, args[0], args[4]); + tcg_out_insn(s, RIL, ALFI, a0, a4); } else { - tcg_out_insn(s, RR, ALR, args[0], args[4]); + tcg_out_insn(s, RR, ALR, a0, a4); } - tcg_out_insn(s, RRE, ALCR, args[1], args[5]); + tcg_out_insn(s, RRE, ALCR, a1, args[5]); break; case INDEX_op_sub2_i32: if (const_args[4]) { - tcg_out_insn(s, RIL, SLFI, args[0], args[4]); + tcg_out_insn(s, RIL, SLFI, a0, a4); } else { - tcg_out_insn(s, RR, SLR, args[0], args[4]); + tcg_out_insn(s, RR, SLR, a0, a4); } - tcg_out_insn(s, RRE, SLBR, args[1], args[5]); + tcg_out_insn(s, RRE, SLBR, a1, args[5]); break; =20 case INDEX_op_br: - tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); + tgen_branch(s, S390_CC_ALWAYS, arg_label(a0)); break; =20 case INDEX_op_brcond_i32: - tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); + tgen_brcond(s, TCG_TYPE_I32, a2, a0, + a1, const_args[1], arg_label(args[3])); break; case INDEX_op_setcond_i32: - tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], - args[2], const_args[2]); + tgen_setcond(s, TCG_TYPE_I32, args[3], a0, a1, a2, const_args[2]); break; case INDEX_op_movcond_i32: - tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + tgen_movcond(s, TCG_TYPE_I32, args[5], a0, a1, + a2, const_args[2], args[3], const_args[3]); break; =20 case INDEX_op_qemu_ld_i32: /* ??? Technically we can use a non-extending instruction. */ case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2]); + tcg_out_qemu_ld(s, a0, a1, a2); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2]); + tcg_out_qemu_st(s, a0, a1, a2); break; =20 case INDEX_op_ld16s_i64: - tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]= ); + tcg_out_mem(s, 0, RXY_LGH, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld32u_i64: - tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2= ]); + tcg_out_mem(s, 0, RXY_LLGF, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld32s_i64: - tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]= ); + tcg_out_mem(s, 0, RXY_LGF, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld_i64: - tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); + tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); break; =20 case INDEX_op_st32_i64: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); break; case INDEX_op_st_i64: - tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); break; =20 case INDEX_op_add_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { do_addi_64: if (a0 =3D=3D a1) { @@ -2084,7 +2084,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; case INDEX_op_sub_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { a2 =3D -a2; goto do_addi_64; @@ -2096,18 +2095,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_and_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); + tgen_andi(s, TCG_TYPE_I64, a0, a2); } else if (a0 =3D=3D a1) { - tcg_out_insn(s, RRE, NGR, args[0], args[2]); + tcg_out_insn(s, RRE, NGR, a0, a2); } else { tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_ori(s, TCG_TYPE_I64, a0, a2); @@ -2118,7 +2115,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; case INDEX_op_xor_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_xori(s, TCG_TYPE_I64, a0, a2); @@ -2130,21 +2126,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_neg_i64: - tcg_out_insn(s, RRE, LCGR, args[0], args[1]); + tcg_out_insn(s, RRE, LCGR, a0, a1); break; case INDEX_op_bswap64_i64: - tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); + tcg_out_insn(s, RRE, LRVGR, a0, a1); break; =20 case INDEX_op_mul_i64: if (const_args[2]) { - if (args[2] =3D=3D (int16_t)args[2]) { - tcg_out_insn(s, RI, MGHI, args[0], args[2]); + if (a2 =3D=3D (int16_t)args[2]) { + tcg_out_insn(s, RI, MGHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSGFI, a0, a2); } } else { - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + tcg_out_insn(s, RRE, MSGR, a0, a2); } break; =20 @@ -2153,10 +2149,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, into R3 with this definition, but as we do in fact always produce both quotient and remainder using INDEX_op_div_i64 instead requires jumping through even more hoops. */ - tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, a4); break; case INDEX_op_divu2_i64: - tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, a4); break; case INDEX_op_mulu2_i64: tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]); @@ -2166,9 +2162,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, op =3D RSY_SLLG; do_shift64: if (const_args[2]) { - tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_sh64(s, op, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, op, args[0], args[1], args[2], 0); + tcg_out_sh64(s, op, a0, a1, a2, 0); } break; case INDEX_op_shr_i64: @@ -2180,87 +2176,83 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, =20 case INDEX_op_rotl_i64: if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); + tcg_out_sh64(s, RSY_RLLG, a0, a1, a2, 0); } break; case INDEX_op_rotr_i64: if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, (64 - args[2]) & 63); + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_REG_NONE, (64 - a2) & 63= ); } else { /* We can use the smaller 32-bit negate because only the low 6 bits are examined for the rotate. */ - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_TMP0, 0); } break; =20 case INDEX_op_ext8s_i64: - tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext8s(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext16s_i64: - tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext16s(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: - tgen_ext32s(s, args[0], args[1]); + tgen_ext32s(s, a0, a1); break; case INDEX_op_ext8u_i64: - tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext8u(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext16u_i64: - tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext16u(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: - tgen_ext32u(s, args[0], args[1]); + tgen_ext32u(s, a0, a1); break; =20 case INDEX_op_add2_i64: if (const_args[4]) { - if ((int64_t)args[4] >=3D 0) { - tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); + if ((int64_t)a4 >=3D 0) { + tcg_out_insn(s, RIL, ALGFI, a0, a4); } else { - tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); + tcg_out_insn(s, RIL, SLGFI, a0, -a4); } } else { - tcg_out_insn(s, RRE, ALGR, args[0], args[4]); + tcg_out_insn(s, RRE, ALGR, a0, a4); } - tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); + tcg_out_insn(s, RRE, ALCGR, a1, args[5]); break; case INDEX_op_sub2_i64: if (const_args[4]) { - if ((int64_t)args[4] >=3D 0) { - tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); + if ((int64_t)a4 >=3D 0) { + tcg_out_insn(s, RIL, SLGFI, a0, a4); } else { - tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); + tcg_out_insn(s, RIL, ALGFI, a0, -a4); } } else { - tcg_out_insn(s, RRE, SLGR, args[0], args[4]); + tcg_out_insn(s, RRE, SLGR, a0, a4); } - tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); + tcg_out_insn(s, RRE, SLBGR, a1, args[5]); break; =20 case INDEX_op_brcond_i64: - tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); + tgen_brcond(s, TCG_TYPE_I64, a2, a0, + a1, const_args[1], arg_label(args[3])); break; case INDEX_op_setcond_i64: - tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], - args[2], const_args[2]); + tgen_setcond(s, TCG_TYPE_I64, args[3], a0, a1, a2, const_args[2]); break; case INDEX_op_movcond_i64: - tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + tgen_movcond(s, TCG_TYPE_I64, args[5], a0, a1, + a2, const_args[2], args[3], const_args[3]); break; =20 OP_32_64(deposit): - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[1]) { - tgen_deposit(s, a0, a2, args[3], args[4], 1); + tgen_deposit(s, a0, a2, args[3], a4, 1); } else { /* Since we can't support "0Z" as a constraint, we allow a1 in any register. Fix things up as if a matching constraint. = */ @@ -2272,22 +2264,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } tcg_out_mov(s, type, a0, a1); } - tgen_deposit(s, a0, a2, args[3], args[4], 0); + tgen_deposit(s, a0, a2, args[3], a4, 0); } break; =20 OP_32_64(extract): - tgen_extract(s, args[0], args[1], args[2], args[3]); + tgen_extract(s, a0, a1, a2, args[3]); break; =20 case INDEX_op_clz_i64: - tgen_clz(s, args[0], args[1], args[2], const_args[2]); + tgen_clz(s, a0, a1, a2, const_args[2]); break; =20 case INDEX_op_mb: /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ - if (args[0] & TCG_MO_ST_LD) { + if (a0 & TCG_MO_ST_LD) { tcg_out_insn(s, RR, BCR, s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15= , 0); } --=20 2.26.2 From nobody Sat Apr 20 11:51:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1610558730; cv=none; d=zohomail.com; s=zohoarc; b=hIj4No5L8eziHNqRbbcjfG+cGrW6Jru31192YHLWIcVAGhZhKv62cKdezB+wyjk5RwIxmnS5HwLc3aUqET7eV9PGeyaYu1ZQG9ZdCTnkSYeqnLbjkyRfjg8r63Z8wmbGdZWCsosclENtjHlbzKgLNoxVMeUBCqHZ1nVYTn4gNVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610558730; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nbTY58aO/0J5mVZOizL8/L5H+yZ4rt3Ds459buh/Uo4=; b=Vbf0EKT4nMUvR79ocle/ul+BjhP0bS3+DyFZTrfJDOgVj3bdmNhkIJRN0UHyuZdjuE/zumuuD95WuiQfrFMC7NDCsi6iKcDIgBrAfxoo5r/P6Zi79gmc2TENE5Fgq1KYWMxg60O0Tlgk/tOMUs927ccTY4sZ8FvgspHXJFjD4X0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 1610558730518490.08958763166686; Wed, 13 Jan 2021 09:25:30 -0800 (PST) Received: by mail-wm1-f52.google.com with SMTP id e25so2347529wme.0 for ; Wed, 13 Jan 2021 09:25:28 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id 125sm3862219wmc.27.2021.01.13.09.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nbTY58aO/0J5mVZOizL8/L5H+yZ4rt3Ds459buh/Uo4=; b=uoa946qK+eG5eMCIzS2cz6yzKuNu/TbYio49p1yhcciT51de1vXX8hnCRTN6lZxLdh 2CPDKNODcNGqKK0ZMIUo3lLiFGnqCz95hUZSZdEggWPdpRPlKUlm/ccrw2XniCjE/cCo xWJyBtNpoYNy2Ro8lrTqpIF9QiRdAALofRFxiIVAqiiFUQT7Cw8NeZfu3yHdWoysQNB9 uIlLcQcfiMaxFiNjjkcXv3CU5tS4iiSi4+ZvpZO4VAnBtlxELdaNOFdMYqt4rlqFr+4u Mznwtep1Hp5wvKAA1Xukf28WicT5hAO2ARCgWEI8wAPIoLPN5D0AFijUCTjpAGivhv4b yAxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nbTY58aO/0J5mVZOizL8/L5H+yZ4rt3Ds459buh/Uo4=; b=Frzn5tRhNv8h9gzt/U6g9H3p6nzHZiAuikqmiQnD4KEhPJP5ZeDRPduwJVZq5JXKrf 1RjnQcJaW7jRuBKLi+wYxr00VyraZk8vqY+1MuwJ0KxFHODeFvKjUSgpWVBEsDOZ/OTy Jet1+z4Q5cejgO+5WqV2lFahjKZYEqvOJyjRQT7w9Lq5ZL7v4L3M46zNRm5JBkF2D479 ntSflRNhL1zhNyxuZjIiOZCVxJM00zxjxER0oCQhl1ckm+kXlByx9wgrGqgcMFOw3uzn DYgxG05ZTVGq+yp5LMFF0CaZ5sb5qR5GpnibXUmQw2RWrf1rcU7zMrm/F+X1guhytcir FsWw== X-Gm-Message-State: AOAM532zTX38D/DPDduT/JaEN6KLJMpFRHg4kyPNi5w5AU3dwX6zOE/L r2Qr3mJCKwLZ4QygjAdUo1o= X-Google-Smtp-Source: ABdhPJxR03gA0wrsFd/XfrZXq8/5cAsQbe8rZGIFSVwI83fvnhK3DyuI357dOUM4Sy7cVHORHVggqg== X-Received: by 2002:a1c:a583:: with SMTP id o125mr258893wme.91.1610558727675; Wed, 13 Jan 2021 09:25:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 5/6] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements Date: Wed, 13 Jan 2021 18:24:58 +0100 Message-Id: <20210113172459.2481060-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) tcg_reg_alloc_op() allocates arrays of TCG_MAX_OP_ARGS elements. The Aarch64 target already does this since commit 8d8db193f25 ("tcg-aarch64: Hoist common argument loads in tcg_out_op"), SPARC since commit b357f902bff ("tcg-sparc: Hoist common argument loads in tcg_out_op"). RISCV missed it upon introduction in commit bdf503819ee ("tcg/riscv: Add the out op decoder"), MIPS since commit 22ee3a987d5 ("tcg-mips: Hoist args loads") and i386 since commit 42d5b514928 ("tcg/i386: Hoist common arguments in tcg_out_op"). Provide this information as a hint to the compiler in the function prototype, and update the funtion definitions. This fixes this warning (using GCC 11): tcg/aarch64/tcg-target.c.inc:1855:37: error: argument 3 of type 'const = TCGArg[16]' {aka 'const long unsigned int[16]'} with mismatched bound [-Wer= ror=3Darray-parameter=3D] tcg/aarch64/tcg-target.c.inc:1856:34: error: argument 4 of type 'const = int[16]' with mismatched bound [-Werror=3Darray-parameter=3D] Reported-by: Miroslav Rezanina Reviewed-by: Miroslav Rezanina Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 5 +++-- tcg/i386/tcg-target.c.inc | 3 ++- tcg/mips/tcg-target.c.inc | 3 ++- tcg/riscv/tcg-target.c.inc | 3 ++- tcg/tci/tcg-target.c.inc | 5 +++-- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 472bf1755bf..97d074d8fab 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -110,8 +110,9 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args); +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #if TCG_TARGET_MAYBE_vec static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 46e856f4421..d121dca8789 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2215,7 +2215,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) } =20 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; int c, const_a2, vexop, rexw =3D 0; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index add157f6c32..b9bb54f0ecc 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1691,7 +1691,8 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2= , MIPSInsn opcv6, } =20 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c60b91ba58f..5bf0d069532 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1238,7 +1238,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) static const tcg_insn_unit *tb_ret_addr; =20 static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0 =3D args[0]; TCGArg a1 =3D args[1]; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d5a4d9d37cf..60464524f3d 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -553,8 +553,9 @@ static inline void tcg_out_call(TCGContext *s, const tc= g_insn_unit *arg) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { uint8_t *old_code_ptr =3D s->code_ptr; =20 --=20 2.26.2 From nobody Sat Apr 20 11:51:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610558734; cv=none; d=zohomail.com; s=zohoarc; b=n3MJV5V75a7iw7sbnhKd9ocP45X+7ZuzPsJO9r7XpdJeeGSs55FrtLQYSYHcQHSd2Dpj6uGIayxLBi+l23MfUwTsGgl+N580yubty3rNhztC1aAB+tt16g7EzjNMNhKJO6w1piBg759cfFe5zODcDl+PPjRILw53dnCAJGhSZ+0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610558734; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CsrU5PzWJOqWBM621BtsUfkniXFxs+sJ0jZIwq4bvko=; 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Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 14 ++++++++------ tcg/aarch64/tcg-target.c.inc | 3 ++- tcg/i386/tcg-target.c.inc | 3 ++- tcg/ppc/tcg-target.c.inc | 3 ++- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 97d074d8fab..3a20327f9cb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -120,9 +120,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType ty= pe, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset); static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg dst, tcg_target_long arg); -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, - const int *const_args); +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #else static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned v= ece, TCGReg dst, TCGReg src) @@ -139,9 +140,10 @@ static inline void tcg_out_dupi_vec(TCGContext *s, TCG= Type type, { g_assert_not_reached(); } -static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned v= ecl, - unsigned vece, const TCGArg *args, - const int *const_args) +static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { g_assert_not_reached(); } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ab199b143f3..32811976e78 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2276,7 +2276,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const AArch64Insn cmp_insn[16] =3D { [TCG_COND_EQ] =3D I3616_CMEQ, diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d121dca8789..87bf75735a1 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2654,7 +2654,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static int const add_insn[4] =3D { OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 70b747a8a30..b8f5f8a53e1 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3137,7 +3137,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType t= ype, unsigned vece, =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const uint32_t add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, --=20 2.26.2