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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id m82sm5648226wmf.29.2021.01.12.13.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 13:02:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+QdnWeeWowM8n1JNeLbHcjqIuTxoeMtPbLfQb8+zPm8=; b=TLQ1/h3rE8KxzNHZBPmQ/fnOOISfg8okPY4C1+X+ah17vHkdW2A4LeqEcZhNSbAI+G yHN7G+MbJDgjSTBLd4D0bcMsIQr3+fWHGskSYJWwjfhJmckgTtCTwcGEqNfma0R+FoHF ZPQjT3+dXDglfYkivVCGvtpX6vTyFlhLD7UnjZLsZPVMdVebnMzKnfxnYRmn5UgfrWF1 1BiQ9CoVHIx2KuD29Jx8YU5WkPoluzk1f84p6HsZFRIs7oCkWKAfGcaEr9YIOgCbGUe6 uR1bYzRLSnMqjZqmlSCqrbqW9k2SitXWvdHjj70hV8HxzWs8AH/ojTbksB9vaU7H1rnO UoFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+QdnWeeWowM8n1JNeLbHcjqIuTxoeMtPbLfQb8+zPm8=; b=M6xOnC0otfy6mWvUj6Ptok2oryIJa6oJHOU22Id3CJcmMuGZjjhOdr1abunm7AEeUR juZ/4MC8x6u+r0tbzkhTVfGP62W2+2r4IaCaW1mcHIJqF1zJ34U5NDVqqGfXJwESjhu4 A+ewhXZ3QA9tW70Ubel0rNGTiT0qctH/IZP2MEtN5lbt3tKZmF8ibGiOOe1Yxrr/Rq8y qvA3p974m5HsKcBfzcLK9LwX8rCuEs3DyH4T5JFaVJmMXTt7qTT8PMz2S/vpxyhBB7W4 1HYu2M973ClC5yyrWhy8GhwJB7WWMAc1UM8/TAnfEGyYFEnQRHpCVs67iIOhOSHkV2u7 ofgg== X-Gm-Message-State: AOAM532qs7O/iP3wHUCkaSjFfN6OExaPtvy3j7sB56CC/uHrviguLUJ9 r5rOEp7feSrwrWYRNeY6aSU= X-Google-Smtp-Source: ABdhPJzBCBdhNkxg15ZYGTmNJD9EM95DNfukzwBx9e/11Ij+KNE0H71hqG/AzpuT04ZQ7cUwY/JwFQ== X-Received: by 2002:a5d:60ca:: with SMTP id x10mr693195wrt.242.1610485331204; Tue, 12 Jan 2021 13:02:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Aleksandar Rikalo Subject: [PATCH 3/3] target/mips: Remove vendor specific CPU definitions Date: Tue, 12 Jan 2021 22:01:52 +0100 Message-Id: <20210112210152.2072996-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112210152.2072996-1-f4bug@amsat.org> References: <20210112210152.2072996-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Vendor specific CPU definitions are not very useful. Use the ISA definitions instead, which are more helpful when looking at the various CPU definitions. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 5 ----- target/mips/cpu-defs.c.inc | 12 +++++++----- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 3704db85532..0a12d982a72 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -60,9 +60,6 @@ #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) -#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) -#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) -#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 #define CPU_MIPS64 (ISA_MIPS3) =20 @@ -86,8 +83,6 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 -#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_L= EXT) - /* * Strictly follow the architecture standard: * - Disallow "special" instruction handling for PMON/SPIM. diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 9f7bac87932..e03b2a998cd 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -531,7 +531,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 32, - .insn_flags =3D CPU_VR54XX, + .insn_flags =3D CPU_MIPS4 | INSN_VR54XX, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -781,7 +781,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 40, - .insn_flags =3D CPU_LOONGSON2E, + .insn_flags =3D CPU_MIPS3 | INSN_LOONGSON2E, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -801,7 +801,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 40, - .insn_flags =3D CPU_LOONGSON2F, + .insn_flags =3D CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -830,7 +830,8 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 42, .PABITS =3D 48, - .insn_flags =3D CPU_LOONGSON3A, + .insn_flags =3D CPU_MIPS64R2 | INSN_LOONGSON3A | + ASE_LMMI | ASE_LEXT, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -887,7 +888,8 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_LOONGSON3A, + .insn_flags =3D CPU_MIPS64R2 | INSN_LOONGSON3A | + ASE_LMMI | ASE_LEXT, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.26.2