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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id k15sm1503481ejc.79.2021.01.12.10.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3oL8bC8x9VFwiA/xc6ZokDU2TIJ+D0ZdajpMhJAtRjE=; b=pzLiDzMgO2qqe2xY1cGknoalgMmhRxSV1G3RrQhEbCujzyXMOPbxqRLBBZh8ioK+QC JSOBJWrEv+/WfBDGtrj1o1uuMDav0IQXvK7K21u4+v2oY0ZivsHgnRik7wkYZsWRzazS AdWAY7UqPK2MnePUxrTKaZUP99Fhc1XAvhzraM52iOTf85rv9T2a0WlKugOgfoK2AGnO MEt/uV9mlP0iyoS0pLf/uf5qVldhU+eNCHg4khq7OuA6dddSVlDGrbm/pHqL3od20eY1 Dt4hKixGQrE9LYy/JTomthxBKyfCQ00mwDxYDtpU8NbRXfrNWuGkTYg4QfZriqo8VWXJ J6Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3oL8bC8x9VFwiA/xc6ZokDU2TIJ+D0ZdajpMhJAtRjE=; b=m9yU3LWc4fntflhj3dUPrYETB6EuEFfyM5YsAkEi5pU4inKyhuFm8HZtdFRRwbnzUK pu8EUqpUNHdf68ZM9o3A8IHLhKzN8KAc7ZOcSzGtmFFynFxzpVQ2a86GqpVr8uoXdT++ NCc8MtlkR4VABMfB3VOSSY9XFAdrLt32Enz3fp1nCTdNIjebXZvOWlOxvIM3bnxbCa4V YY4VHglP0cfgGUx+40aOW+txWENoRYWeD4LCvcNgR9F4EO8NcUuzBn21ra/LRuFu8loI HsO+SYiyk4iw2MMw7fVASnHo8s2IMrZVzqBa3rzNOu+AAoQz8nhD6B44Wg/zQy4dyItC xQxA== X-Gm-Message-State: AOAM531wv83TnZNMEFOdALKgJIPaObfXRv/Vh4JBx1GbFpHbBNpeyZyd kB7Ts1gdEE0LNnBflC5nhLbmCjWpqYM= X-Google-Smtp-Source: ABdhPJzNVjPNHTWfdTDu4WsmxLITpifXl/wpM6+l3N1UEWB9deJNBPNSw+YabAM7dHGcuTVg3j30VQ== X-Received: by 2002:a17:906:90d6:: with SMTP id v22mr139279ejw.88.1610476588169; Tue, 12 Jan 2021 10:36:28 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , Xuzhou Cheng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 08/11] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 12 Jan 2021 19:35:26 +0100 Message-Id: <20210112183529.2011863-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ssi/imx_spi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 801daa5cbfa..2f9e800dd3a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -255,6 +255,10 @@ static void imx_spi_reset(DeviceState *dev) =20 imx_spi_update_irq(s); =20 + for (i =3D 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length =3D 0; } =20 --=20 2.26.2