From nobody Tue Feb 10 03:15:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1610475368; cv=none; d=zohomail.com; s=zohoarc; b=diYu+JdrlMHJHLzCTltFJ2Jf7HqimA8Ha6eVxq7J1vW2KnT8mqh4zH71wchGWZ+8rHaxYH2kUNtKU06NkuG/bRCN83r3R0R5gO9DZTZVd+IzezxJL3z/Sd6Gt6IntakxRb0PTltOhy05eXoo7es+bPqYZKTvrZ6I7Bfze+beXqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610475368; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eaOWRfoLdqPBC6G5xbgrzfD4AooFHm/ySpMCp8CUNAU=; b=DDiFJRZCCL0eHrAxfNwirJZhEKyvIsWl9SpgfWp+eVwWff/uNESoNWDnT1lMJhK50wezjycYrfgF5GeKi92obaH1RGjU1imMUYctfuTPSRNGOYTdoC0VIEUORuo6FfgfHJleu6pN2mMHGAADssKpLXaYNztFcKdBKSk6yPMTSmg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161047536836060.43029056990849; Tue, 12 Jan 2021 10:16:08 -0800 (PST) Received: from localhost ([::1]:51230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzOD9-0001gI-2G for importer@patchew.org; Tue, 12 Jan 2021 13:16:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzO1L-0005T1-7o for qemu-devel@nongnu.org; Tue, 12 Jan 2021 13:03:55 -0500 Received: from mx2.suse.de ([195.135.220.15]:33798) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzO17-0004wW-HH for qemu-devel@nongnu.org; Tue, 12 Jan 2021 13:03:54 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 56A95AC5B; Tue, 12 Jan 2021 18:03:29 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v12 13/22] cpu: move adjust_watchpoint_address to tcg_ops Date: Tue, 12 Jan 2021 19:03:03 +0100 Message-Id: <20210112180312.26043-14-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112180312.26043-1-cfontana@suse.de> References: <20210112180312.26043-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs") introduced this ARM-specific, TCG-specific hack to adjust the address, before checking it with cpu_check_watchpoint. Make adjust_watchpoint_address optional and move it to tcg_ops. Signed-off-by: Claudio Fontana --- include/hw/core/cpu.h | 7 ++++++- hw/core/cpu.c | 6 ------ softmmu/physmem.c | 5 ++++- target/arm/cpu.c | 2 +- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 95ff2c9eb0..d6c6d32865 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -137,6 +137,12 @@ typedef struct TcgCpuOperations { void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); + + /** + * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM + */ + vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); + #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ =20 @@ -249,7 +255,6 @@ struct CPUClass { const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); =20 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); - vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); =20 const char *deprecation_note; /* Keep non-pointer data at the end to minimize holes. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 57542b6906..3d5bf9fe02 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -383,11 +383,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } =20 -static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int = len) -{ - return addr; -} - static Property cpu_common_props[] =3D { #ifndef CONFIG_USER_ONLY /* Create a memory property for softmmu CPU object, @@ -421,7 +416,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->gdb_write_register =3D cpu_common_gdb_write_register; k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; k->debug_check_watchpoint =3D cpu_common_debug_check_watchpoint; - k->adjust_watchpoint_address =3D cpu_adjust_watchpoint_address; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 9e7c50e0db..1443621579 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -894,7 +894,10 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, v= addr len, return; } =20 - addr =3D cc->adjust_watchpoint_address(cpu, addr, len); + if (cc->tcg_ops.adjust_watchpoint_address) { + /* this is currently used only by ARM BE32 */ + addr =3D cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len); + } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (watchpoint_address_matches(wp, addr, len) && (wp->flags & flags)) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 36c3e7fb55..e478d21a19 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2271,7 +2271,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #if !defined(CONFIG_USER_ONLY) cc->tcg_ops.do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->tcg_ops.do_unaligned_access =3D arm_cpu_do_unaligned_access; - cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; + cc->tcg_ops.adjust_watchpoint_address =3D arm_adjust_watchpoint_addres= s; cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ --=20 2.26.2