From nobody Mon Feb 9 23:39:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1610474989; cv=none; d=zohomail.com; s=zohoarc; b=A02ukh1OJGchWsa/SJYsJoExLKU0CCYDJOLMGvauzWNEdzRSZpUIC2fC6BPxu9OL+BC1cEk5gzEy1zj7RAEC/AZ7KHeULgwjS7By1IwRIEWx62Ofc11arLbJcXNh+Na25KSfzjrZqf8jtnOEDESu4r6frV5wSHy8lUDo9SHcxbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610474989; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BfP2yJqtWNQoRJuAXUgo5A66UL03F/4u7BscJvLVOJA=; b=e5jDC388UrkPue3fAYGgqTOsHAFNTX3G56BRg4Sy835TyUjf7RhuDYIGNVrHA5BFEs5PN2FFP/ECPfUGGYbvaRJQOFmf//6FdehFLydZIHoFq/EoZc+unsde9/Jgg1/2RBIi4u9ZzkdUUVjNPcjfMyUBmuvxTZ6uFOqpNPaR8y8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610474989862325.8450912940666; Tue, 12 Jan 2021 10:09:49 -0800 (PST) Received: from localhost ([::1]:33818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzO72-0002h3-7n for importer@patchew.org; Tue, 12 Jan 2021 13:09:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzO0x-0005Jr-Pp for qemu-devel@nongnu.org; Tue, 12 Jan 2021 13:03:31 -0500 Received: from mx2.suse.de ([195.135.220.15]:33646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzO0s-0004w0-CA for qemu-devel@nongnu.org; Tue, 12 Jan 2021 13:03:31 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 2A709AD62; Tue, 12 Jan 2021 18:03:25 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v12 09/22] cpu: move cc->do_interrupt to tcg_ops Date: Tue, 12 Jan 2021 19:02:59 +0100 Message-Id: <20210112180312.26043-10-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112180312.26043-1-cfontana@suse.de> References: <20210112180312.26043-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- accel/tcg/cpu-exec.c | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/arm/cpu_tcg.c | 9 ++++----- target/avr/cpu.c | 2 +- target/avr/helper.c | 4 ++-- target/cris/cpu.c | 12 ++++++------ target/cris/helper.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 ++-- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 27 files changed, 41 insertions(+), 42 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index a0e040c617..8fcdd55494 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,6 +104,8 @@ typedef struct TcgCpuOperations { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @do_interrupt: Callback for interrupt handling. */ + void (*do_interrupt)(CPUState *cpu); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -129,7 +131,6 @@ typedef struct TcgCpuOperations { * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @do_interrupt: Callback for interrupt handling. * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #TARGET_ALIGNED_ONLY. * @do_transaction_failed: Callback for handling failed memory transactions @@ -199,7 +200,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - void (*do_interrupt)(CPUState *cpu); void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b4d863b927..d44e11d7d2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -540,7 +540,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) loop */ #if defined(TARGET_I386) CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->do_interrupt(cpu); + cc->tcg_ops.do_interrupt(cpu); #endif *ret =3D cpu->exception_index; cpu->exception_index =3D -1; @@ -549,7 +549,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (replay_exception()) { CPUClass *cc =3D CPU_GET_CLASS(cpu); qemu_mutex_lock_iothread(); - cc->do_interrupt(cpu); + cc->tcg_ops.do_interrupt(cpu); qemu_mutex_unlock_iothread(); cpu->exception_index =3D -1; =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 9f36f824fd..66f1166672 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -217,7 +217,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; - cc->do_interrupt =3D alpha_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D alpha_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e0dfa9ca4e..8c9ca29025 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -590,7 +590,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) found: cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); return true; } =20 @@ -2248,7 +2248,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_cpu_do_interrupt; cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->vmsd =3D &vmstate_arm_cpu; @@ -2273,6 +2272,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #if !defined(CONFIG_USER_ONLY) cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; + cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif } diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index f2e565166e..d9c160f1ac 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -34,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } return ret; @@ -666,12 +666,11 @@ static void arm_v7m_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(oc); =20 acc->info =3D data; +#ifdef CONFIG_TCG + cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; #ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D arm_v7m_cpu_do_interrupt; #endif - -#ifdef CONFIG_TCG - cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; #endif /* CONFIG_TCG */ =20 cc->gdb_core_xml_file =3D "arm-m-profile.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index d6e93049b4..476e645b37 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -198,7 +198,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->class_by_name =3D avr_cpu_class_by_name; =20 cc->has_work =3D avr_cpu_has_work; - cc->do_interrupt =3D avr_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D avr_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D avr_cpu_exec_interrupt; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; diff --git a/target/avr/helper.c b/target/avr/helper.c index d96d14372b..69d3b6181f 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -34,7 +34,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (interrupt_request & CPU_INTERRUPT_RESET) { if (cpu_interrupts_enabled(env)) { cs->exception_index =3D EXCP_RESET; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); =20 cs->interrupt_request &=3D ~CPU_INTERRUPT_RESET; =20 @@ -45,7 +45,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (cpu_interrupts_enabled(env) && env->intsrc !=3D 0) { int index =3D ctz32(env->intsrc); cs->exception_index =3D EXCP_INT(index); - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); =20 env->intsrc &=3D env->intsrc - 1; /* clear the interrupt */ cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9222717f3e..b65743e8ca 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -199,7 +199,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void= *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 8; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -210,7 +210,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void= *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 9; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -221,7 +221,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 10; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -232,7 +232,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 11; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -243,7 +243,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 17; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -268,7 +268,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; - cc->do_interrupt =3D cris_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D cris_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D cris_cpu_exec_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; diff --git a/target/cris/helper.c b/target/cris/helper.c index ed45c3d9b7..1f4d6f7d45 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -299,7 +299,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } if (interrupt_request & CPU_INTERRUPT_NMI) { @@ -311,7 +311,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) } if ((env->pregs[PR_CCS] & m_flag_archval)) { cs->exception_index =3D EXCP_NMI; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d5a25014e8..68233acf53 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -140,7 +140,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; - cc->do_interrupt =3D hppa_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D hppa_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6c1ebbdcc6..4a53cd89e2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -59,7 +59,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, =20 void tcg_cpu_common_class_init(CPUClass *cc) { - cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D x86_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bbe1405e32..fb3761b749 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -222,7 +222,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; - cc->do_interrupt =3D lm32_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D lm32_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index e38e4d5456..69093a621f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -465,7 +465,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; - cc->do_interrupt =3D m68k_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D m68k_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 68df0c20d8..b0b133b5be 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -318,7 +318,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; - cc->do_interrupt =3D mb_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D mb_cpu_do_interrupt; cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 85b3161b25..d72ddc3b21 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -477,7 +477,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; - cc->do_interrupt =3D mips_cpu_do_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; @@ -491,10 +490,11 @@ static void mips_cpu_class_init(ObjectClass *c, void = *data) cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D mips_tcg_init; + cc->tcg_ops.do_interrupt =3D mips_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; -#endif +#endif /* CONFIG_TCG */ =20 cc->gdb_num_core_regs =3D 73; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 1177d092c1..36bef4d357 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -107,7 +107,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D moxie_cpu_class_by_name; =20 cc->has_work =3D moxie_cpu_has_work; - cc->do_interrupt =3D moxie_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; cc->tcg_ops.tlb_fill =3D moxie_cpu_tlb_fill; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 1384836de0..b5fe779ceb 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -221,7 +221,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; - cc->do_interrupt =3D nios2_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D nios2_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 9857bfde23..1a31f7564f 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,7 +186,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; - cc->do_interrupt =3D openrisc_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D openrisc_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05c97e7e73..86ca452479 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -570,7 +570,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; - cc->do_interrupt =3D riscv_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D riscv_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 77609728b8..e79f009cbd 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -186,7 +186,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) =20 cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; - cc->do_interrupt =3D rx_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D rx_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 8ade66178e..e6cf933594 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -496,7 +496,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; #ifdef CONFIG_TCG - cc->do_interrupt =3D s390_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D s390_cpu_do_interrupt; #endif cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1f6c687c3c..f69360fc16 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -219,7 +219,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; - cc->do_interrupt =3D superh_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D superh_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 19e90a414d..871b2a83c6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -863,7 +863,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; - cc->do_interrupt =3D sparc_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D sparc_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 75b3a4bae3..7d4ead4ef1 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -147,7 +147,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; - cc->do_interrupt =3D tilegx_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D tilegx_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index a57d315d2f..e27ffc571a 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -131,7 +131,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; - cc->do_interrupt =3D uc32_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D uc32_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index b6f13ceb32..3ff025f0fe 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -194,7 +194,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; - cc->do_interrupt =3D xtensa_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D xtensa_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 1e0fc5ac3d..b16430a9d4 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,7 +10845,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->class_by_name =3D ppc_cpu_class_by_name; cc->has_work =3D ppc_cpu_has_work; - cc->do_interrupt =3D ppc_cpu_do_interrupt; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; @@ -10883,6 +10882,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D ppc_translate_init; cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; + cc->tcg_ops.do_interrupt =3D ppc_cpu_do_interrupt; cc->tcg_ops.tlb_fill =3D ppc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; --=20 2.26.2