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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/21] target/arm: ARMv8.4-TTST extension
Date: Tue, 12 Jan 2021 16:57:30 +0000
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From: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
This adds for the Small Translation tables extension in AArch64 state.
Signed-off-by: R=C3=A9mi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
target/arm/helper.c | 15 +++++++++++++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7e6c881a7e2..ad37ff61c62 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3936,6 +3936,11 @@ static inline bool isar_feature_aa64_uao(const ARMIS=
ARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0;
}
=20
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0;
+}
+
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d077dd9ef51..5ab3f5ace36 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10842,7 +10842,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env=
, uint64_t va,
{
uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr;
bool epd, hpd, using16k, using64k;
- int select, tsz, tbi;
+ int select, tsz, tbi, max_tsz;
=20
if (!regime_has_2_ranges(mmu_idx)) {
select =3D 0;
@@ -10877,7 +10877,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en=
v, uint64_t va,
hpd =3D extract64(tcr, 42, 1);
}
}
- tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
+
+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
+ max_tsz =3D 48 - using64k;
+ } else {
+ max_tsz =3D 39;
+ }
+
+ tsz =3D MIN(tsz, max_tsz);
tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
=20
/* Present TBI as a composite with TBID. */
@@ -11096,6 +11103,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, u=
int64_t address,
if (!aarch64 || stride =3D=3D 9) {
/* AArch32 or 4KB pages */
startlevel =3D 2 - sl0;
+
+ if (cpu_isar_feature(aa64_st, cpu)) {
+ startlevel &=3D 3;
+ }
} else {
/* 16KB or 64KB pages */
startlevel =3D 3 - sl0;
--=20
2.20.1