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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.57.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:57:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RT64QSt/nocPy3bcUDYbqKLfp0TF6hHQCydKZeSEBxo=; b=u9w6qhq8HUoUQH472nC8PhkgXn0ySnJDddSnWpBkobIhhStDtoB24XsrTJTpaiorcb zYrMaQFJ+auZZBN4l3mHWVX369a87cTBQ+synx2btvjGG/wGUKQMJHtweXmFoPUfvcT7 bdeCjAjuEeWUYkAcjINqrmoHhTlK5XjFJDXMibpZBFFW8DAufI1FGDZDsYrvX/iOw6e7 kda8uAmMEoLGeVfGqvyaLJwij/awYN2B6kqJIPBMIZly8FVaYgTdokusDMTgn4BfezCY nItxIJE6i7pt34KGlf9WFnlhCScw1lJXgy/3MHjhjW/RCND8yDcCvRytVtiEVEZAh5xc tIrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RT64QSt/nocPy3bcUDYbqKLfp0TF6hHQCydKZeSEBxo=; b=rKE2EwjGh4wbsaKwhRsuR0nkaZcZ6OLsGnTBT5r3/F8y/2Ql5Y+Rh4syKI8YP4n7zh aIRU1wpW+klzxUG76smsu37v5m84nR0YqAOJxpi9vTDYaSXesDbOzlwZJf2SP+13RAf+ yRlf6oHFtP0X9YLSRIJU4MWR2TCcXoYlvsKHblwnURhMk5fdSDhsGMAgnD5BXTzSqvmv tad0itznHAvfJ6V1LD+dC1CTvye589cI4CI5r993ZX4LO8JUpum530bQSrfgfeB/y4wf 0fUUQPfrHPc2e0rfBC2mH2uBAqlxpGnSZtV1ruWuxKAGw1OJ4tCaCidcTm5oIeKmRG4x NwNg== X-Gm-Message-State: AOAM5327Sbb1XD5rBLaNbJBc4mutdaAvDblPfv0mI4agFvHIJWJ+/o6F tZHl8Kk2J9OVn4cf61HvzIDvcrnP09EmMg== X-Google-Smtp-Source: ABdhPJyEkFLpH0aoHDD1kt4YYmJlcwrQLrtvBx9+PjhroSkdgtYXfF97QFFBJoLrVlMW+kWYdppjBQ== X-Received: by 2002:a5d:4d03:: with SMTP id z3mr3605150wrt.280.1610470673394; Tue, 12 Jan 2021 08:57:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/21] target/arm: ARMv8.4-TTST extension Date: Tue, 12 Jan 2021 16:57:30 +0000 Message-Id: <20210112165750.30475-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: R=C3=A9mi Denis-Courmont This adds for the Small Translation tables extension in AArch64 state. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 15 +++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e2..ad37ff61c62 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3936,6 +3936,11 @@ static inline bool isar_feature_aa64_uao(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; } =20 +static inline bool isar_feature_aa64_st(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index d077dd9ef51..5ab3f5ace36 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10842,7 +10842,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; bool epd, hpd, using16k, using64k; - int select, tsz, tbi; + int select, tsz, tbi, max_tsz; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -10877,7 +10877,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, hpd =3D extract64(tcr, 42, 1); } } - tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ + + if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + max_tsz =3D 48 - using64k; + } else { + max_tsz =3D 39; + } + + tsz =3D MIN(tsz, max_tsz); tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ =20 /* Present TBI as a composite with TBID. */ @@ -11096,6 +11103,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, u= int64_t address, if (!aarch64 || stride =3D=3D 9) { /* AArch32 or 4KB pages */ startlevel =3D 2 - sl0; + + if (cpu_isar_feature(aa64_st, cpu)) { + startlevel &=3D 3; + } } else { /* 16KB or 64KB pages */ startlevel =3D 3 - sl0; --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610470891; cv=none; d=zohomail.com; s=zohoarc; b=nRk7kt08rZ7Yo1QL4oticcHgZf33sjt3fC/BaxFxCiHx84EOR1O4WJPxM2zJMLw0G5loEKeGCU1ygihtAPq6YkXMBik/FvH1Dglx2Jyj6dyj4ufGjPvH5EgGxDTzcbUkwZG090kxoKebrukJ2FRLLqryY7vLxwy9CfnsDnoDzXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610470891; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t9mHNHYfhgucBJqyH8TdMdoSYXb99VvjrbQmZv5BKGc=; b=hxuMqEKF2PzPuJLbkJWuFiAOaxB36p+zjftQNAqwvGf+aV7vBGEwOYUAYpK4PTelThTO7AML6Bz/vCLtGUA+8zfNw7TnC+1um7I6vRsmE1cO1ghOZYD+v4dc+n7K3nypWYlATLhEVw7D4QKEVDFrFb/xjZeV1IWLvhwPO/Guoa0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610470891929568.0941456002288; Tue, 12 Jan 2021 09:01:31 -0800 (PST) Received: from localhost ([::1]:35106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzN2w-0003FT-8b for importer@patchew.org; Tue, 12 Jan 2021 12:01:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzW-0001QC-Cp for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:57:58 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:40350) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzU-0006w6-UT for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:57:58 -0500 Received: by mail-wr1-x42b.google.com with SMTP id 91so3237145wrj.7 for ; Tue, 12 Jan 2021 08:57:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.57.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:57:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=t9mHNHYfhgucBJqyH8TdMdoSYXb99VvjrbQmZv5BKGc=; b=tuWtxsHYqdvuxemNZpRRgzVvmuilXLuEcFj2AY++YIZH00zNEBEigaTlko+PT/qqCi Jf1kZjNohGlw2jUth+2WKe/oFnVbl9dnQIS0ashTrsQFO7nKqiBVir6CkgrWW0NqGlT6 RjHtohsv22YkUTNs/Qs5Xa8Nhh236W1fAnMfmi7py1UDlMouaBjqG5ufOSOJy329yWbE IK3Ou0IZ3K8mEQPU5wETiLzoeTTbEo1avhbE+4hsKY+4BN3JpFfr1w3oUYE+hOSMMCD0 jNgUUWqxHQHrQzN88OvURUwKQijHhzDmvVT8yv5Vx1JReAz/yq2CQq0cMo8rmVAL/kVv SDug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t9mHNHYfhgucBJqyH8TdMdoSYXb99VvjrbQmZv5BKGc=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7cf9fc4bc61..da24f94baa2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ cpu->isar.id_aa64mmfr2 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610471089; cv=none; d=zohomail.com; s=zohoarc; b=S/aTR7ffCOwOR1NRbNag+Xb8Q8eP+dDWqNFB8nF5i4vPi595ueTdP0vWkCEXyDVpVzzFSRjBylQ5LN5XINIHUmyPqPQA9GjZXcLtWk21wUnVKMEbcxoVdPwWfl4aQqX0DHGf2l/qWrAS1Zv1Ec8IYHwBOk1VWSR98In5R7N89cY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610471089; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.57.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:57:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SOiul1QpeOOwd39s2BaIyL3jusMnSNt/3sMWzu/GZ6M=; b=ckHxN+ZzVftUsB06Jgj6LzBCCKV1zXGJs8OcHIhwbBF1ipxn34PmWF6X7bqRlz39GE 5RtRRz9Keeub7Ya7HXr+TXMghiQEjLQNvSsZD3KvQgl/Q7KYJUXoHJiehfhk2FhSpzm0 hWVLJVWy0IbSNEP2BWC4RdZZ6T8V7RvsWeT+eojAVpKtDw9a5jQMZ+JTQGggwRUdvMQl Eu1ZkCCNfQQYZBuDDVPYFtJKQHyBtHlbuL4gRVKZ8p6VgsXnAaHq+/VBPEG7WebfDvXg 9evC6W04PNLlArNHfdch9tLvv3p8M7jT2ZccGngoT+GJF8cinojg3co9VwTFZfzSM1gB 7g+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SOiul1QpeOOwd39s2BaIyL3jusMnSNt/3sMWzu/GZ6M=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Leif Lindholm SBSS -> SSBS Signed-off-by: Leif Lindholm Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 20210108185154.8108-2-leif@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad37ff61c62..ed3e9fe2e4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1883,7 +1883,7 @@ FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) =20 FIELD(ID_AA64PFR1, BT, 0, 4) -FIELD(ID_AA64PFR1, SBSS, 4, 4) +FIELD(ID_AA64PFR1, SSBS, 4, 4) FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) =20 --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.57.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zq1EFVs9ZUsELBHVmtcyccZKM3D0LKUF7TXBeHh40+Y=; b=ANI5qk8VXfLn9JNEO1S3U7b27FDFfptBIRmdIUVb10WeJ64V4gr0RRHLFuWft7rRcc dvDyBj7UFbHuCc6CPQfCCsHWSnWjiLbkODuEtcQhDsUpWcMfQ2bDYxnn7Bzok29QM95N BEMAzGDXg+fvavvp/HVsvth3k0Zkk4Lx/HgcH03ep/3wjftgE+3e9R8bNk7ZTq3EZrCK 9lUNVhIOFripxJOTLNcZF1rGlnvgjDNkG7utxVlzc9E3z4rdDwQTxe6odmuFnz0pWAEn S15LR5GGQneMjtBNHCFuSZl8ix5QOnKa+DoXyhTT7cPm7oQmJuBxDhLIRviOKA1WYyww Jonw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zq1EFVs9ZUsELBHVmtcyccZKM3D0LKUF7TXBeHh40+Y=; b=Eg8BZ16GzD/O4IUEPJav8u0pS4+2Pf6+d7YZnYeuiQtxRxiNxNTh068oCcjdVkvn9f NpHevNPkC7c7zkwc0t6aTEaW6QEV4UqsLzyrufFCNbBMrH1b/1SliSIpRmOzIpWMzU9l Z8rYJrs1R4qsXHN79lqE4L0E7FdaAO+TIC9PH4pzzu6lcupbWSD8pJYHlFMsrwA3CgWj wKxDkgw0CZxnNzVZprag4ROrhrmlhOEFak+T4RA9Tku0YW+O9wCFb9beA3iSEgYqb7oQ yPO12qdnsRS+23+3sA6vk8c6MVxvfdgQXM+iYtea6AGOb/kPg9SJD88fDsfL+QBtk7Tz cEDg== X-Gm-Message-State: AOAM532zlazD39RZDu6gx+IYFUfme+peLk0e69Uek0P1oIdFBgTIydP+ KeGs/gB1sSPd2BZzGu8fWXnMpjDHQbPa0g== X-Google-Smtp-Source: ABdhPJwZUIZFQVSFq7qOQ8WT2WSP7rbq+7/eFaodlPqvRGGfeVDMRiFJEI2fzygP1/pMAomoe1n5ww== X-Received: by 2002:a1c:5406:: with SMTP id i6mr154752wmb.137.1610470676909; Tue, 12 Jan 2021 08:57:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/21] target/arm: make ARMCPU.clidr 64-bit Date: Tue, 12 Jan 2021 16:57:33 +0000 Message-Id: <20210112165750.30475-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Leif Lindholm The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Signed-off-by: Leif Lindholm Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 20210108185154.8108-3-leif@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ed3e9fe2e4e..fdbfcec2b09 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -938,7 +938,7 @@ struct ARMCPU { uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t clidr; + uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610471510; cv=none; d=zohomail.com; s=zohoarc; b=J3Nef13QSJxcpLVarb/81keLb0+jNcHTY7O720LaWzpTalLS8hloO2+jx+zzMt9B7VDXeX92ST3x2xXECd0zVKRuWl0pAoVdD3b2v7SPM627eLJMtl7f/1fAeH72iYZth/KCPMfcfZe6tBcyrmOkEsh2gbRqsI18fhwkBopxrsk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610471510; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E9f67EoxTBsbFvikJJ/TTwZHVpUMqRmi4LByom0Aj1c=; b=JSyXsLLZ0WkM/dIAa9Hhu9VuJuHjm586MH5ane5j4ZaOBhun7ibEWrYfAI/IM47LeNknfFoQic7fKZ2OhIMYZ6gD3U+B3BD6sSA4JChUJx3Kmj+H9ZodvllejEizNFCvp7zslU31joucMhAPDC6BMjWPaL4abofDQN/K4sWf6VI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610471510116718.5437973462077; Tue, 12 Jan 2021 09:11:50 -0800 (PST) Received: from localhost ([::1]:60206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzNCu-0006g5-IC for importer@patchew.org; Tue, 12 Jan 2021 12:11:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzY-0001SE-Ra for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:00 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:46817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzX-0006xO-E5 for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:00 -0500 Received: by mail-wr1-x436.google.com with SMTP id d13so3209623wrc.13 for ; Tue, 12 Jan 2021 08:57:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.57.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:57:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=E9f67EoxTBsbFvikJJ/TTwZHVpUMqRmi4LByom0Aj1c=; b=BqDuAlvEV7Htnn6IfcFA+KXMRHuVBupNLCQvmbhu4GTj3zb/A/iHNmILhp1tK6KoAM 0mgQVmDf+ojO0FoqVR9dcj95ZUWalAa4zqDqfOZlaYwNOnUg4D4tIOpc6zUHh4daGddZ 7ILD5NFZPeS3yOcpcKI3SX+a7X9dUgRSZmSmOj2geH6XSMfat3XtDJuGRKIQC44jTYv6 LAgvcEqVYFOISxoVszl16gNIUtX5yNYtZ2m2zCfTEmZxysHz3BVN40e6RT+8nzuWb+eH 0flM6RFvS8QlpOe446rtCps6BJyvOqt0T2Oh6LMs7I6Am6g/dJFf/qKawj4bVAmsXM0l OWYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E9f67EoxTBsbFvikJJ/TTwZHVpUMqRmi4LByom0Aj1c=; b=WUETBF66xZljcXusy78yjqm9SWR7nOAPwVRfApDB6tCuR2y6tBAt6HYmDpFxXjvhF7 9HuoTTIn2C4P21p++lrbjxUqawCX2fnKNhy+nPCJhx8iSYR/JuPSN3L8f3YnHAcg074B Eh3PMU7DOwppb98YQz43gbtIanl2xmz8h+1aU+rtD0M1ku49f0obc+jshg7DomEieJfH 6kfVxkTwXTmxer8fZEWbwrVSbTP1gIunzbdx0GB9DWchruXWb0Ym7UJ7tCKib4G7QK1u +dwJ0pCho8zDicxZqwl75/cX9uN0RhJY5gsrl8CScy5Lu0pqERwCmoaCyv7wtCMnTfEi Ej0A== X-Gm-Message-State: AOAM532452emFb0HEDYIfgM0t0uao7bjwKVjHjwINtXoAXbkFRTK4WaA DWJn3mAjhZLEFEtFoUcndDPgKRL2Gu31jA== X-Google-Smtp-Source: ABdhPJzgEP/H4nLm0zLru+mKKnBnY932moC8FHPIkBpAWAq+SZBBs8gjIuJQwrIWQmuZWfoW0d+6sw== X-Received: by 2002:a5d:4905:: with SMTP id x5mr5229355wrq.75.1610470677936; Tue, 12 Jan 2021 08:57:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/21] target/arm: make ARMCPU.ctr 64-bit Date: Tue, 12 Jan 2021 16:57:34 +0000 Message-Id: <20210112165750.30475-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Leif Lindholm When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the TminLine field in bits [37:32]. Extend the ctr field to be able to hold this context. Signed-off-by: Leif Lindholm Reviewed-by: Hao Wu Reviewed-by: Richard Henderson Reviewed-by: Laurent Desnogues Message-id: 20210108185154.8108-4-leif@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fdbfcec2b09..0795c4cc06a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -931,7 +931,7 @@ struct ARMCPU { uint64_t midr; uint32_t revidr; uint32_t reset_fpsid; - uint32_t ctr; + uint64_t ctr; uint32_t reset_sctlr; uint64_t pmceid0; uint64_t pmceid1; --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610470898; cv=none; d=zohomail.com; s=zohoarc; b=iG48XdfzhSqujhc9g7rfEJ0VhSpRYq43piOa3oMWXu73zIqeur5aevqm49itDzKU4aa2TmQhCYnf2ki/ma6IySyQzfgFut1vGRVj4P9DA66G8Wvdd2+MmoVqiIGz5yNnhhSKlQc2BP8p6syvzpOJYHb4vCpEp+Zrn82CTZpu+j4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610470898; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J4L022TzDpwIjVuY3iJsZtRyyv98RdYaVw0aN/TPG5k=; b=FgjGBKcXfUhKVUPdc4rJScGKIeC6xndzDAS3+8hzJCfmCUrb/6gQoohNYiW0pKBUjk27QKtgPPw3Vdp5YUw1DdZsjzbNgLcQoGb79tNFjfNzQGs8JsECrbh7G3G4IBgvIZ0nd+ACm9qdHtuMJh+vt6yWsy/A2O0JqqQ7ZkaSAqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610470898656332.3220165675906; Tue, 12 Jan 2021 09:01:38 -0800 (PST) Received: from localhost ([::1]:35336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzN33-0003Ng-6n for importer@patchew.org; Tue, 12 Jan 2021 12:01:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMza-0001Tr-3s for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:02 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:50590) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzY-0006xW-Jb for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:01 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 190so2526133wmz.0 for ; Tue, 12 Jan 2021 08:58:00 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.57.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:57:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=J4L022TzDpwIjVuY3iJsZtRyyv98RdYaVw0aN/TPG5k=; b=ajHua4KodR4yKG/LcKBdAsCfamQif8CdhDH3tD+EMT1NvcYsQAfRd3n5+hWzWgzpqP HJhlQ6sk7OmWt7MMdwCBebAKp9ms92eoc2fhhO/VcM1C2j7KJW3qdnW7FiWgQzJKIBbl Gtlacfc7aJ9RHi8ahjzlIJKyLMLxN96/amxRRuwwGmmKtaf4BwSPGOmkdBKpcKyJeGo9 PbkAQaGR+tnVYv3NRtDhe3d5/ZmeNufGMCLuLwHws4sVqcoQcOcr84t6tm4vY23/YH8/ fPuKI2M75PhxXNMTGZ72c9WBVpTg131xFgnhl0V9Kz85TIcJYmWFfz/8faGhqGS5H6KT /xrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J4L022TzDpwIjVuY3iJsZtRyyv98RdYaVw0aN/TPG5k=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Leif Lindholm Signed-off-by: Leif Lindholm Reviewed-by: Laurent Desnogues Message-id: 20210108185154.8108-5-leif@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0795c4cc06a..9c1872f2686 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1736,6 +1736,37 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) /* * System register ID fields. */ +FIELD(CLIDR_EL1, CTYPE1, 0, 3) +FIELD(CLIDR_EL1, CTYPE2, 3, 3) +FIELD(CLIDR_EL1, CTYPE3, 6, 3) +FIELD(CLIDR_EL1, CTYPE4, 9, 3) +FIELD(CLIDR_EL1, CTYPE5, 12, 3) +FIELD(CLIDR_EL1, CTYPE6, 15, 3) +FIELD(CLIDR_EL1, CTYPE7, 18, 3) +FIELD(CLIDR_EL1, LOUIS, 21, 3) +FIELD(CLIDR_EL1, LOC, 24, 3) +FIELD(CLIDR_EL1, LOUU, 27, 3) +FIELD(CLIDR_EL1, ICB, 30, 3) + +/* When FEAT_CCIDX is implemented */ +FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) +FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) +FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) + +/* When FEAT_CCIDX is not implemented */ +FIELD(CCSIDR_EL1, LINESIZE, 0, 3) +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) +FIELD(CCSIDR_EL1, NUMSETS, 13, 15) + +FIELD(CTR_EL0, IMINLINE, 0, 4) +FIELD(CTR_EL0, L1IP, 14, 2) +FIELD(CTR_EL0, DMINLINE, 16, 4) +FIELD(CTR_EL0, ERG, 20, 4) +FIELD(CTR_EL0, CWG, 24, 4) +FIELD(CTR_EL0, IDC, 28, 1) +FIELD(CTR_EL0, DIC, 29, 1) +FIELD(CTR_EL0, TMINLINE, 32, 6) + FIELD(MIDR_EL1, REVISION, 0, 4) FIELD(MIDR_EL1, PARTNUM, 4, 12) FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.57.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:57:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YmJipAg+O6Dy+TutSAvdqlDacqJcXiWHQ54CqTsqao8=; b=CRxqQL3x7XK4ekrrdgQXXHxEAyh9F1JjY/H582hFmo/Z1ZyjoiG4Q2hlUKnEfLDImy Fw2Ugf7+4v/tBBNvsKlPTmdDoxUEF2gyrEFh0RPMVPDEb6jY8a4ZNqxuu8bZMatS6twA 9RBNgICpu7pky2hxIysLU7x8y/09RwjJfb4aPLOhmTxtWMREz31qnOuAlgCXrwXsccmD evT9jt4JBK6r4A3T/T1quKevTdqJ/VpGiqsP699DkjpmvJNQqhTorKbK73vMEoRsZRZH 65yp2tIZ/+u1xyVkewK3EzaWLiWKx8kCjksWGHnriFDYK4BklQ7fonec7BxFAXuE05/w dkgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YmJipAg+O6Dy+TutSAvdqlDacqJcXiWHQ54CqTsqao8=; b=EqcfigY4Ef86xXiKlImKZgfQOvidjeMHa3KSPb0GAUPX4gdQC6JKJr7ZlOK54lfWl+ vXd/tP0kJRln8HFzRAMRzgO9MkRN/N00cR9rCoPFKZ5TzsJzevFM0s7Pztoe75aV8tb6 g8n7+5UUfr+ulh3PQeGhXBKzo7isYeWYtrUHfc79LSt4sAu+NBJgUd+RbhQyR5E2GjIE V5YonYWJfT3yOLTjmux2o7YKN/+KplZxM4lmfG5YmMnfhma4Us8Zua/fkmhUNLl4msvn CIn39Kz1t9mHjNy1MRt+reH3EAzwb6WMzgjtviULB15LT3NjtQYBiY6sEVvI43Nl6NI7 dHkQ== X-Gm-Message-State: AOAM530uTC81V0K217p8r6JMiSkpe1qRz92lcxv80DCKoSIuWpkTm8Q4 XLQE7axQIlUTm/8AOK1LapWmzz7UEzdDiQ== X-Google-Smtp-Source: ABdhPJyCqIQ4llshMkSbhVOhn6etMsNElWU8xeZhMNjEpaigQrmL7l9mpx834/iJeowlIr4CVztNPg== X-Received: by 2002:a1c:a706:: with SMTP id q6mr185127wme.7.1610470680003; Tue, 12 Jan 2021 08:58:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h Date: Tue, 12 Jan 2021 16:57:36 +0000 Message-Id: <20210112165750.30475-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Leif Lindholm Add entries present in ARM DDI 0487F.c (August 2020). Signed-off-by: Leif Lindholm Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 20210108185154.8108-6-leif@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c1872f2686..d8fb8c845ca 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1902,6 +1902,9 @@ FIELD(ID_AA64ISAR1, GPI, 28, 4) FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) FIELD(ID_AA64ISAR1, SB, 36, 4) FIELD(ID_AA64ISAR1, SPECRES, 40, 4) +FIELD(ID_AA64ISAR1, BF16, 44, 4) +FIELD(ID_AA64ISAR1, DGH, 48, 4) +FIELD(ID_AA64ISAR1, I8MM, 52, 4) =20 FIELD(ID_AA64PFR0, EL0, 0, 4) FIELD(ID_AA64PFR0, EL1, 4, 4) @@ -1912,11 +1915,18 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, SEL2, 36, 4) +FIELD(ID_AA64PFR0, MPAM, 40, 4) +FIELD(ID_AA64PFR0, AMU, 44, 4) +FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) =20 FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SSBS, 4, 4) FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) +FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) =20 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -1930,6 +1940,8 @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) FIELD(ID_AA64MMFR0, EXS, 44, 4) +FIELD(ID_AA64MMFR0, FGT, 56, 4) +FIELD(ID_AA64MMFR0, ECV, 60, 4) =20 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) @@ -1939,6 +1951,8 @@ FIELD(ID_AA64MMFR1, LO, 16, 4) FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR1, TWED, 32, 4) +FIELD(ID_AA64MMFR1, ETS, 36, 4) =20 FIELD(ID_AA64MMFR2, CNP, 0, 4) FIELD(ID_AA64MMFR2, UAO, 4, 4) @@ -1965,6 +1979,7 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) FIELD(ID_AA64DFR0, PMSVER, 32, 4) FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) +FIELD(ID_AA64DFR0, MTPMU, 48, 4) =20 FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610470900; cv=none; d=zohomail.com; s=zohoarc; b=kDv4uxE2zHw/lns5sx9dq0b0ZmxjuArA1M2kCV3UEhGeKVUFkvJOCKOkELJO6Eh7ONxWqoc+bq2HOHgroT9hAfZz/D+4sZS7D3gBLJ7x10UUGFmgG/GCsgT0u3+MhgF3HM1ZufZFbTyvAtNLovrvWUbNYmaS2oXM+w3k9km38l4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610470900; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1dXUdK68h8mQB0EcDIIjKiAW9VItxuUaUHaQgWP73tA=; b=VksMpcc5nD97bJ37pj2GOZp7MCHRbpvJgNo/WOhIxKud0+I6Rrupa6eAW9xPd8A7VFFcQa2CaBlG0B15UaqIY8P9fF+UWYRUnFSfc5fCoEYD8LSe6BEbP72+jvyK2HVZUA6lER+29XHMBAMyEq2Qnw297FmU/KfqHOyOoxfOskY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610470900964298.2120180801152; Tue, 12 Jan 2021 09:01:40 -0800 (PST) Received: from localhost ([::1]:35592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzN35-0003Ui-HI for importer@patchew.org; Tue, 12 Jan 2021 12:01:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzg-0001ZH-AN for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:08 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:52692) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzb-0006yf-8Y for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:04 -0500 Received: by mail-wm1-x32c.google.com with SMTP id a6so2528272wmc.2 for ; Tue, 12 Jan 2021 08:58:02 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1dXUdK68h8mQB0EcDIIjKiAW9VItxuUaUHaQgWP73tA=; b=SKugNu4rc1NSWxjzGL2iRmWgNlyxE56iMCmngw2mlyRh7rYT9s3UbMMS2fZYz5jcSw DEZHEYVdiOp2JtWbmFkZbFDdn2dsI/WoRKR2w4BxBOul/g3qu/h0ginP7Nr151Vx2byQ qRbLTbO6piOa+u1WlXHz7Us39D1rVjNWNkmYpo8zMD32cNV6xKzw2VTl+9btqCzb3mLz SssIXjuR/h9A8+gqkSskgQunOWld6iNePL0XgF/VNosGEB8MVE1qsDRBs+fkbJeaXi63 0jKrv4//3kRSCysqUk8TEcVPdQp+pfAKUcCqdLmFiRAdwsR2doP1nORbXjwXQT/3/iNj U5vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1dXUdK68h8mQB0EcDIIjKiAW9VItxuUaUHaQgWP73tA=; b=p94wWr41/E13j6GIv5yUS9uP2x7+znZVsntlk8eSd5g0vm1fuVAhwcFg9I5TjXZfOL KEUxsVnTEp+PvttQpp6nRlXU1AQZjnGCy/k9FCHr4he2vysLNa9IUHGY1fTZh36e4ckp UU1h03eJjUjHdOIiUG48jCU74+MgtRKbkNMs8sVYKEkBdChzb+WqhFiCWqIwSkPotJrN JovL5AE0aBcePkEu9wTjIVbf8UnfyrxD21kubyXs30Qj6xEdszoAfQdZgXEhVw85/zvR CJyRt/fKPKuMrvoT+8lStCUwewETcpSJK4NM//gvCKQUBK+eXsi+qI37biP4Iq6DThg8 4eKQ== X-Gm-Message-State: AOAM530F6VJUnLhrQGA/Iu1vQ+wJgSbJEaE2CSwQ1Y+NMDryU7sG63+p SaIOWohfnzi9vSogTJoISQiuKbhHvpDA/A== X-Google-Smtp-Source: ABdhPJxPjSapxKw5CM3WSAf0Ca6Xgign6aVp7Oa+J39Q0g8nUdCV7JRBk+urrZwlNYEsq75tzF3yaQ== X-Received: by 2002:a05:600c:4152:: with SMTP id h18mr215698wmm.110.1610470681728; Tue, 12 Jan 2021 08:58:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h Date: Tue, 12 Jan 2021 16:57:37 +0000 Message-Id: <20210112165750.30475-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Leif Lindholm Add entries present in ARM DDI 0487F.c (August 2020). Signed-off-by: Leif Lindholm Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 20210108185154.8108-7-leif@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d8fb8c845ca..f3bca73d987 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1830,6 +1830,8 @@ FIELD(ID_ISAR6, DP, 4, 4) FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_ISAR6, BF16, 20, 4) +FIELD(ID_ISAR6, I8MM, 24, 4) =20 FIELD(ID_MMFR0, VMSA, 0, 4) FIELD(ID_MMFR0, PMSA, 4, 4) @@ -1840,6 +1842,24 @@ FIELD(ID_MMFR0, AUXREG, 20, 4) FIELD(ID_MMFR0, FCSE, 24, 4) FIELD(ID_MMFR0, INNERSHR, 28, 4) =20 +FIELD(ID_MMFR1, L1HVDVA, 0, 4) +FIELD(ID_MMFR1, L1UNIVA, 4, 4) +FIELD(ID_MMFR1, L1HVDSW, 8, 4) +FIELD(ID_MMFR1, L1UNISW, 12, 4) +FIELD(ID_MMFR1, L1HVD, 16, 4) +FIELD(ID_MMFR1, L1UNI, 20, 4) +FIELD(ID_MMFR1, L1TSTCLN, 24, 4) +FIELD(ID_MMFR1, BPRED, 28, 4) + +FIELD(ID_MMFR2, L1HVDFG, 0, 4) +FIELD(ID_MMFR2, L1HVDBG, 4, 4) +FIELD(ID_MMFR2, L1HVDRNG, 8, 4) +FIELD(ID_MMFR2, HVDTLB, 12, 4) +FIELD(ID_MMFR2, UNITLB, 16, 4) +FIELD(ID_MMFR2, MEMBARR, 20, 4) +FIELD(ID_MMFR2, WFISTALL, 24, 4) +FIELD(ID_MMFR2, HWACCFLG, 28, 4) + FIELD(ID_MMFR3, CMAINTVA, 0, 4) FIELD(ID_MMFR3, CMAINTSW, 4, 4) FIELD(ID_MMFR3, BPMAINT, 8, 4) @@ -1858,6 +1878,8 @@ FIELD(ID_MMFR4, LSM, 20, 4) FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) =20 +FIELD(ID_MMFR5, ETS, 0, 4) + FIELD(ID_PFR0, STATE0, 0, 4) FIELD(ID_PFR0, STATE1, 4, 4) FIELD(ID_PFR0, STATE2, 8, 4) @@ -1876,6 +1898,10 @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4) FIELD(ID_PFR1, VIRT_FRAC, 24, 4) FIELD(ID_PFR1, GIC, 28, 4) =20 +FIELD(ID_PFR2, CSV3, 0, 4) +FIELD(ID_PFR2, SSBS, 4, 4) +FIELD(ID_PFR2, RAS_FRAC, 8, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) @@ -1990,6 +2016,8 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) =20 +FIELD(ID_DFR1, MTPMU, 0, 4) + FIELD(DBGDIDR, SE_IMP, 12, 1) FIELD(DBGDIDR, NSUHD_IMP, 14, 1) FIELD(DBGDIDR, VERSION, 16, 4) --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610471100; cv=none; d=zohomail.com; s=zohoarc; b=NIsb/u0ujXTtmm7n60fn3sQ3sOU+FCo34BHYd3rGHT5HUiKRgoolk2b9Tv6YT1Dmu5fbyZFbowzBh/oqiwPprufz/CE6oieePEKspLZM9FAG0tndCQwwUOEjQBZNM+LxYGJWWj+979myAh8hCI4oOjX3PGTUqamxin66gnTpL0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610471100; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+x0GRYuxDvnfEkeYpYvCTsDtGQEJLh4PF7p7x0+/Bzg=; b=POGB2pNkd9iq4OW7F4uko/ZfzkFpM4yJ+odqZAB1FxRpbl4SCR1rDOYFoCGit76fH4v3hwhecDzx622vJwcR8diAZNWrOWXaBrc2kED1wQYq29W9KcCQScALvVWSljYRTpmqwevA12AYnhQlYBl9B7heQBqv8sj66NKjrJ8/5Xk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610471100462324.1694210739256; Tue, 12 Jan 2021 09:05:00 -0800 (PST) Received: from localhost ([::1]:43868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzN6I-0007Ys-RY for importer@patchew.org; Tue, 12 Jan 2021 12:04:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzk-0001jE-1X for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:12 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:55959) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzc-0006zA-Cs for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:11 -0500 Received: by mail-wm1-x32a.google.com with SMTP id c124so2504978wma.5 for ; Tue, 12 Jan 2021 08:58:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+x0GRYuxDvnfEkeYpYvCTsDtGQEJLh4PF7p7x0+/Bzg=; b=vGzxxiBlOVOF3NHI/eMgVCjsIuU3AadLFswtZT1iTSNaY/fl/l02Wyq3gTxbrat/m5 /krotvMEp/yl5+1nMbxtXZlfr5U9KhjXjxgTy6PvQUlLxvku307YovxGJBzJUbddbcOn u7DcIHItF8IQqG49sCeQquCp7p8I6ih7fdrJbioBYEeWV83ycEP/qLC6ENzTc0bCddyE PaW3I/fwzdYdXU3y5mZryJdl1WWIwdLKPQW2XJz8vWVQ3U0KxW8SwRdPSj1SBQvAAXx/ pc9xiHT1rlHm9xGTbj/m9JYRBsWIDxD4WrmAAt5mcVyBj+qfDph2c0xC9zpOQKB808YL M57A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+x0GRYuxDvnfEkeYpYvCTsDtGQEJLh4PF7p7x0+/Bzg=; b=n63KKfeESEShrM331QzCCDHKYpRxIK+0w5UZ8q115rNM6N7SvXwieFyq+Xak4cvQ4r D/sJxeVPDSRsXQLQJByLiV/G5msAGu+YF+bgR1+ht4b3alcDkntA3FONOC/B9l4suQyk 7P+Yx2emyxXN97R46Rj2BOc1dhxqYPqIM9ptF3jMxILqySxroJLRCPpH1qWZ5nt1FSiK tOWPsZSy+52bRYMDCexDUEfNkLcmqoVLhdMDEHJHnoVzrHpluqAXvbbC4OKTZSGDRa8G hmsVHb8M7SAcRRKwPVrmxGJOCs5RE034uVK9+oUghZob0PJG4iult57OKkR0N5q6dbVm QDOg== X-Gm-Message-State: AOAM530tpvYMf0kaE8BpYo7Dx+FC6TQX37KHwgJ5nNPDAOUmG0VRsdYh eIQgrxyaKQ0fGICk1PSCJqsPQOLb3pzFkg== X-Google-Smtp-Source: ABdhPJxgZ1U8gZXHg0bcX1t9QHIZLAGVQiGtRsUwqAjlwSItYzTyzx/X/1evI3hLsyYOm+jLhkONWQ== X-Received: by 2002:a1c:6506:: with SMTP id z6mr176455wmb.55.1610470682905; Tue, 12 Jan 2021 08:58:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/21] ui/cocoa: Update path to docs in build tree Date: Tue, 12 Jan 2021 16:57:38 +0000 Message-Id: <20210112165750.30475-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Roman Bolshakov QEMU documentation can't be opened if QEMU is run from build tree because executables are placed in the top of build tree after conversion to meson. Signed-off-by: Roman Bolshakov Reported-by: Peter Maydell Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- ui/cocoa.m | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index f32adc3074f..e913a514455 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -1176,7 +1176,7 @@ QemuCocoaView *cocoaView; - (void) openDocumentation: (NSString *) filename { /* Where to look for local files */ - NSString *path_array[] =3D {@"../share/doc/qemu/", @"../doc/qemu/", @"= ../docs/"}; + NSString *path_array[] =3D {@"../share/doc/qemu/", @"../doc/qemu/", @"= docs/"}; NSString *full_file_path; =20 /* iterate thru the possible paths until the file is found */ --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610471511; cv=none; d=zohomail.com; s=zohoarc; b=TvEjmQdfDLZw4dSZMOCK54kFxNQrEDeoqcSaqM1cdO5qdHT+0GNCavn8U7+R5YUOq+sdf8LVmO1IKcy9Ftmd2FhtUeNfuLvB53FawpiwB9o10Ix/ufwjLexLhda/XYJf4aRxB1RU4FDsTStP+3LN2/Z4M+PDu4mAxICEyEE43go= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610471511; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mw2ulj6dho7s6fL0XLnahWzsGLXVuZsAno6HF3dbcXM=; b=PXXKoWVLSjhWMqgDG7Oux9kgCkWwn81001sba14GTCKC/mAb33LbKa+KhFGkJ+qUuzbS6tn8eB0UnxJqfjVdEHE7pQ6mB1CVzhairHW57S8Q469G8xauyO1dNcJC9DDD3CYk2vgFVx5X8J0bWp/OgFTmJahA0qJiVhU0p0IDmqU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610471511915559.2604598285992; Tue, 12 Jan 2021 09:11:51 -0800 (PST) Received: from localhost ([::1]:60424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzNCw-0006mS-NJ for importer@patchew.org; Tue, 12 Jan 2021 12:11:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzh-0001cz-QR for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:09 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:52698) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzg-0006zd-3n for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:09 -0500 Received: by mail-wm1-x332.google.com with SMTP id a6so2528432wmc.2 for ; Tue, 12 Jan 2021 08:58:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mw2ulj6dho7s6fL0XLnahWzsGLXVuZsAno6HF3dbcXM=; b=CicBPbKwKM4mc2bEYt6vENr2xD2ApeRQ99K8a3hNe+gf68Xk4H21qnOHujVjv6v3zR afeepPnqSuRk0ENu0Yw/sx/bH7XJKOx/m69EcvhQ+AtgDlf1bkmnGz85Ow6Y6LQm9LK5 1VIJ0PkupWLdFAPHOi7zjmzYhmTZ7jdMMx3Z8RLNCNsHsFu6x0R68V+xnvTDj1whNqH9 rRzz/EykxtoalzAI8iqGozs0GkLPZVTnLtw1HF+AhGbkQsUlsEqNIjnJcFoneNThpfyQ iG16o8eQ/aHqt64TEhQWEBFc087n9S2qf9hPCH5l6PHoKS0spjLVLyyn40WDsA2brrpR 83EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mw2ulj6dho7s6fL0XLnahWzsGLXVuZsAno6HF3dbcXM=; b=fuKGr1QoeJqpbnKMr1zWmNLqQDJvcqktfhMFWixT7Zvb9CSorfxYDV8rY3xe+V/vpZ 9nCS3fEXCd2FKRcpK3P3E+elcLu/xRfNdjCn4qGXl0/Ci1NOSI4EXxfAVSNa10Z1+KUJ YWuFRvSyKMsmzcq79pFyiBLtkKtz94ZRdfnSVLhYPv46XOJk7L8YaHgVUopKb3/UDrfn Oj3bHJopQyv8MRSK3ybnehYnybpfyfEZLsRnnoS3sI6Es1C+p+h5fs/sNnXnnpX/IC/B yke+usueSwgwX/Ll0Gh+dWer6lTwaSDgqV9RrAyY0b3NkvYaj5slOCz8cUFDXST9HJzz AOhA== X-Gm-Message-State: AOAM533T64jcitoCCw2SQoMq3sDZMhMAVuiEVIRoNYXKyuWjw0HVFAkU q8ko3Qj+0Cg5xPej0p7QCxWEsYU8U+I/HQ== X-Google-Smtp-Source: ABdhPJw6zarHUF84S/bGcMiDuj/xpriK3Z/vrrMTpA5oUZo3phJjwvwfUa7qNybxLdv/Q3LT7Xm1gw== X-Received: by 2002:a1c:a145:: with SMTP id k66mr185005wme.11.1610470683967; Tue, 12 Jan 2021 08:58:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build Date: Tue, 12 Jan 2021 16:57:39 +0000 Message-Id: <20210112165750.30475-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage. At the moment new manpages have to be listed both in the conf.py for Sphinx and also in docs/meson.build for Meson. We forgot the second of those -- correct the omission. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-id: 20210108161416.21129-2-peter.maydell@linaro.org --- docs/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/meson.build b/docs/meson.build index 71641b4fe07..fae9849b79b 100644 --- a/docs/meson.build +++ b/docs/meson.build @@ -62,6 +62,7 @@ if build_docs 'qemu-img.1': (have_tools ? 'man1' : ''), 'qemu-nbd.8': (have_tools ? 'man8' : ''), 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), + 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''), 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP'= ) ? 'man1' : ''), 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), 'virtiofsd.1': (have_virtiofsd ? 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wPGXBSDCrBYajP3jT4AxQqAAQh1tAV7hwBx6HvckSBM=; b=DtBF6ZgGf7sp7+L7ZUl4f6fhQM6qzo0TBHVR0ui0Kv5m4X/oym1Trea+/FryUxL+uc TPPs0EOsT0aovPBLVDUSXGLB5nRUqJTGguuLY1Hq8so1PXTNngcofQhom4M0uD6KqcXh QI2tIze8crHFLHTkQvq1nU1wHaLej1A6uy+oAGGBlYOxG63LI1/64bPxmqf8GnU+9+Ce eDeYuMtk0SK9zoQaO59wKt9afFj2+dZ0vYnhX1bLaXou4YYAcVX9tI1mHYk1omrgqtGM 6xZihiyiOZ8BzhoQQDgKq7rRirED0ZIuBED89UPuCS7fn3PZEbgt9Gqo9N5lAbpxVXpT vMag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wPGXBSDCrBYajP3jT4AxQqAAQh1tAV7hwBx6HvckSBM=; b=tNGQhlP8B8W9ivMALGjkXX9aSoUqGiab1TP8PDobPNl2N9fWuJgQxi/+49ttu6uaqD KBKF1Hn65zffwHeQXotaE1BjVZJRTcL1kswHEXWbm6xg3ZvkhdVMNfzVMks5mFTlB9Fn Kc6s/yJZkKu1UQ0ObneVfDKYQKPvSFSGQZu2kTsfMeb6UYZEFmURZH76dOCNfdjFER/3 OydfvrLAGzyZ4v+hT3cjqYshID5I8WpPgDLFmyXRbV6dQTEZGwdcDevHYBUuQUQrC6sE 1JnmPdf8KzY10UjX8nSwb21LKzlhJjMfDoxLeCEfL6dPMJNwU37aeXUebpwnNrqnqTBU Fnwg== X-Gm-Message-State: AOAM530F3/aaf+UyCl948WmPAyPJqeY9CJyf8O1xHHMszhTX1g5Uc8FU VTPk8mePM6IDcmtehrX0k1oqxc15npq8Rg== X-Google-Smtp-Source: ABdhPJx7bRCicU4OOQ3z5+0rybDMEkgLDAXdYeK9yEcejZJuzVtiFSmWijmi44vh3x1GtZLIuV8KNg== X-Received: by 2002:a5d:5913:: with SMTP id v19mr5274163wrd.207.1610470685193; Tue, 12 Jan 2021 08:58:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/21] docs: Build and install all the docs in a single manual Date: Tue, 12 Jan 2021 16:57:40 +0000 Message-Id: <20210112165750.30475-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When we first converted our documentation to Sphinx, we split it into multiple manuals (system, interop, tools, etc), which are all built separately. The primary driver for this was wanting to be able to avoid shipping the 'devel' manual to end-users. However, this is working against the grain of the way Sphinx wants to be used and causes some annoyances: * Cross-references between documents become much harder or possibly impossible * There is no single index to the whole documentation * Within one manual there's no links or table-of-contents info that lets you easily navigate to the others * The devel manual doesn't get published on the QEMU website (it would be nice to able to refer to it there) Merely hiding our developer documentation from end users seems like it's not enough benefit for these costs. Combine all the documentation into a single manual (the same way that the readthedocs site builds it) and install the whole thing. The previous manual divisions remain as the new top level sections in the manual. * The per-manual conf.py files are no longer needed * The man_pages[] specifications previously in each per-manual conf.py move to the top level conf.py * docs/meson.build logic is simplified as we now only need to run Sphinx once for the HTML and then once for the manpages5B * The old index.html.in that produced the top-level page with links to each manual is no longer needed Unfortunately this means that we now have to build the HTML documentation into docs/manual in the build tree rather than directly into docs/; otherwise it is too awkward to ensure we install only the built manual and not also the dependency info, stamp file, etc. The manual still ends up in the same place in the final installed directory, but anybody who was consulting documentation from within the build tree will have to adjust where they're looking. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Message-id: 20210108161416.21129-3-peter.maydell@linaro.org --- docs/conf.py | 46 ++++++++++++++++++++++++++++++- docs/devel/conf.py | 15 ----------- docs/index.html.in | 17 ------------ docs/interop/conf.py | 28 ------------------- docs/meson.build | 64 +++++++++++++++++--------------------------- docs/specs/conf.py | 16 ----------- docs/system/conf.py | 28 ------------------- docs/tools/conf.py | 37 ------------------------- docs/user/conf.py | 15 ----------- 9 files changed, 70 insertions(+), 196 deletions(-) delete mode 100644 docs/devel/conf.py delete mode 100644 docs/index.html.in delete mode 100644 docs/interop/conf.py delete mode 100644 docs/specs/conf.py delete mode 100644 docs/system/conf.py delete mode 100644 docs/tools/conf.py delete mode 100644 docs/user/conf.py diff --git a/docs/conf.py b/docs/conf.py index d40d8ff37ba..2ee61118725 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -224,7 +224,51 @@ latex_documents =3D [ =20 # -- Options for manual page output --------------------------------------- # Individual manual/conf.py can override this to create man pages -man_pages =3D [] +man_pages =3D [ + ('interop/qemu-ga', 'qemu-ga', + 'QEMU Guest Agent', + ['Michael Roth '], 8), + ('interop/qemu-ga-ref', 'qemu-ga-ref', + 'QEMU Guest Agent Protocol Reference', + [], 7), + ('interop/qemu-qmp-ref', 'qemu-qmp-ref', + 'QEMU QMP Reference Manual', + [], 7), + ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', + 'QEMU Storage Daemon QMP Reference Manual', + [], 7), + ('system/qemu-manpage', 'qemu', + 'QEMU User Documentation', + ['Fabrice Bellard'], 1), + ('system/qemu-block-drivers', 'qemu-block-drivers', + 'QEMU block drivers reference', + ['Fabrice Bellard and the QEMU Project developers'], 7), + ('system/qemu-cpu-models', 'qemu-cpu-models', + 'QEMU CPU Models', + ['The QEMU Project developers'], 7), + ('tools/qemu-img', 'qemu-img', + 'QEMU disk image utility', + ['Fabrice Bellard'], 1), + ('tools/qemu-nbd', 'qemu-nbd', + 'QEMU Disk Network Block Device Server', + ['Anthony Liguori '], 8), + ('tools/qemu-pr-helper', 'qemu-pr-helper', + 'QEMU persistent reservation helper', + [], 8), + ('tools/qemu-storage-daemon', 'qemu-storage-daemon', + 'QEMU storage daemon', + [], 1), + ('tools/qemu-trace-stap', 'qemu-trace-stap', + 'QEMU SystemTap trace tool', + [], 1), + ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper', + 'QEMU 9p virtfs proxy filesystem helper', + ['M. Mohan Kumar'], 1), + ('tools/virtiofsd', 'virtiofsd', + 'QEMU virtio-fs shared file system daemon', + ['Stefan Hajnoczi ', + 'Masayoshi Mizuma '], 1), +] =20 # -- Options for Texinfo output ------------------------------------------- =20 diff --git a/docs/devel/conf.py b/docs/devel/conf.py deleted file mode 100644 index 7441f87e7f5..00000000000 --- a/docs/devel/conf.py +++ /dev/null @@ -1,15 +0,0 @@ -# -*- coding: utf-8 -*- -# -# QEMU documentation build configuration file for the 'devel' manual. -# -# This includes the top level conf file and then makes any necessary tweak= s. -import sys -import os - -qemu_docdir =3D os.path.abspath("..") -parent_config =3D os.path.join(qemu_docdir, "conf.py") -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) - -# This slightly misuses the 'description', but is the best way to get -# the manual title to appear in the sidebar. -html_theme_options['description'] =3D u'Developer''s Guide' diff --git a/docs/index.html.in b/docs/index.html.in deleted file mode 100644 index 33db4396ac8..00000000000 --- a/docs/index.html.in +++ /dev/null @@ -1,17 +0,0 @@ - - - - - QEMU @VERSION@ Documentation - - -

QEMU @VERSION@ Documentation

- - - diff --git a/docs/interop/conf.py b/docs/interop/conf.py deleted file mode 100644 index f4370aaa13f..00000000000 --- a/docs/interop/conf.py +++ /dev/null @@ -1,28 +0,0 @@ -# -*- coding: utf-8 -*- -# -# QEMU documentation build configuration file for the 'interop' manual. -# -# This includes the top level conf file and then makes any necessary tweak= s. -import sys -import os - -qemu_docdir =3D os.path.abspath("..") -parent_config =3D os.path.join(qemu_docdir, "conf.py") -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) - -# This slightly misuses the 'description', but is the best way to get -# the manual title to appear in the sidebar. -html_theme_options['description'] =3D u'System Emulation Management and In= teroperability Guide' - -# One entry per manual page. List of tuples -# (source start file, name, description, authors, manual section). -man_pages =3D [ - ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent', - ['Michael Roth '], 8), - ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference', - [], 7), - ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual', - [], 7), - ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', - 'QEMU Storage Daemon QMP Reference Manual', [], 7), -] diff --git a/docs/meson.build b/docs/meson.build index fae9849b79b..bb14eaebd3b 100644 --- a/docs/meson.build +++ b/docs/meson.build @@ -46,19 +46,11 @@ if build_docs meson.source_root() / 'docs/sphinx/qmp_lexer.py', qapi_gen_depends ] =20 - configure_file(output: 'index.html', - input: files('index.html.in'), - configuration: {'VERSION': meson.project_version()}, - install_dir: qemu_docdir) - manuals =3D [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ] man_pages =3D { - 'interop' : { 'qemu-ga.8': (have_tools ? 'man8' : ''), 'qemu-ga-ref.7': 'man7', 'qemu-qmp-ref.7': 'man7', 'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''), - }, - 'tools': { 'qemu-img.1': (have_tools ? 'man1' : ''), 'qemu-nbd.8': (have_tools ? 'man8' : ''), 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), @@ -66,53 +58,47 @@ if build_docs 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP'= ) ? 'man1' : ''), 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), - }, - 'system': { 'qemu.1': 'man1', 'qemu-block-drivers.7': 'man7', 'qemu-cpu-models.7': 'man7' - }, } =20 sphinxdocs =3D [] sphinxmans =3D [] - foreach manual : manuals - private_dir =3D meson.current_build_dir() / (manual + '.p') - output_dir =3D meson.current_build_dir() / manual - input_dir =3D meson.current_source_dir() / manual =20 - this_manual =3D custom_target(manual + ' manual', + private_dir =3D meson.current_build_dir() / 'manual.p' + output_dir =3D meson.current_build_dir() / 'manual' + input_dir =3D meson.current_source_dir() + + this_manual =3D custom_target('QEMU manual', build_by_default: build_docs, - output: [manual + '.stamp'], - input: [files('conf.py'), files(manual / 'conf.py')], - depfile: manual + '.d', + output: 'docs.stamp', + input: files('conf.py'), + depfile: 'docs.d', depend_files: sphinx_extn_depends, command: [SPHINX_ARGS, '-Ddepfile=3D@DEPFILE@', '-Ddepfile_stamp=3D@OUTPUT0@', '-b', 'html', '-d', private_dir, input_dir, output_dir]) - sphinxdocs +=3D this_manual - if build_docs and manual !=3D 'devel' - install_subdir(output_dir, install_dir: qemu_docdir) - endif + sphinxdocs +=3D this_manual + install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: tr= ue) =20 - these_man_pages =3D [] - install_dirs =3D [] - foreach page, section : man_pages.get(manual, {}) - these_man_pages +=3D page - install_dirs +=3D section =3D=3D '' ? false : get_option('mandir') /= section - endforeach - if these_man_pages.length() > 0 - sphinxmans +=3D custom_target(manual + ' man pages', - build_by_default: build_docs, - output: these_man_pages, - input: this_manual, - install: build_docs, - install_dir: install_dirs, - command: [SPHINX_ARGS, '-b', 'man', '-d', private= _dir, - input_dir, meson.current_build_dir()]) - endif + these_man_pages =3D [] + install_dirs =3D [] + foreach page, section : man_pages + these_man_pages +=3D page + install_dirs +=3D section =3D=3D '' ? false : get_option('mandir') / s= ection endforeach + + sphinxmans +=3D custom_target('QEMU man pages', + build_by_default: build_docs, + output: these_man_pages, + input: this_manual, + install: build_docs, + install_dir: install_dirs, + command: [SPHINX_ARGS, '-b', 'man', '-d', pr= ivate_dir, + input_dir, meson.current_build_dir= ()]) + alias_target('sphinxdocs', sphinxdocs) alias_target('html', sphinxdocs) alias_target('man', sphinxmans) diff --git a/docs/specs/conf.py b/docs/specs/conf.py deleted file mode 100644 index 4d56f3ae13c..00000000000 --- a/docs/specs/conf.py +++ /dev/null @@ -1,16 +0,0 @@ -# -*- coding: utf-8 -*- -# -# QEMU documentation build configuration file for the 'specs' manual. -# -# This includes the top level conf file and then makes any necessary tweak= s. -import sys -import os - -qemu_docdir =3D os.path.abspath("..") -parent_config =3D os.path.join(qemu_docdir, "conf.py") -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) - -# This slightly misuses the 'description', but is the best way to get -# the manual title to appear in the sidebar. -html_theme_options['description'] =3D \ - u'System Emulation Guest Hardware Specifications' diff --git a/docs/system/conf.py b/docs/system/conf.py deleted file mode 100644 index 6251849fefc..00000000000 --- a/docs/system/conf.py +++ /dev/null @@ -1,28 +0,0 @@ -# -*- coding: utf-8 -*- -# -# QEMU documentation build configuration file for the 'system' manual. -# -# This includes the top level conf file and then makes any necessary tweak= s. -import sys -import os - -qemu_docdir =3D os.path.abspath("..") -parent_config =3D os.path.join(qemu_docdir, "conf.py") -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) - -# This slightly misuses the 'description', but is the best way to get -# the manual title to appear in the sidebar. -html_theme_options['description'] =3D u'System Emulation User''s Guide' - -# One entry per manual page. List of tuples -# (source start file, name, description, authors, manual section). -man_pages =3D [ - ('qemu-manpage', 'qemu', u'QEMU User Documentation', - ['Fabrice Bellard'], 1), - ('qemu-block-drivers', 'qemu-block-drivers', - u'QEMU block drivers reference', - ['Fabrice Bellard and the QEMU Project developers'], 7), - ('qemu-cpu-models', 'qemu-cpu-models', - u'QEMU CPU Models', - ['The QEMU Project developers'], 7) -] diff --git a/docs/tools/conf.py b/docs/tools/conf.py deleted file mode 100644 index 7072d993246..00000000000 --- a/docs/tools/conf.py +++ /dev/null @@ -1,37 +0,0 @@ -# -*- coding: utf-8 -*- -# -# QEMU documentation build configuration file for the 'tools' manual. -# -# This includes the top level conf file and then makes any necessary tweak= s. -import sys -import os - -qemu_docdir =3D os.path.abspath("..") -parent_config =3D os.path.join(qemu_docdir, "conf.py") -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) - -# This slightly misuses the 'description', but is the best way to get -# the manual title to appear in the sidebar. -html_theme_options['description'] =3D \ - u'Tools Guide' - -# One entry per manual page. List of tuples -# (source start file, name, description, authors, manual section). -man_pages =3D [ - ('qemu-img', 'qemu-img', u'QEMU disk image utility', - ['Fabrice Bellard'], 1), - ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon', - [], 1), - ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server', - ['Anthony Liguori '], 8), - ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation help= er', - [], 8), - ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool', - [], 1), - ('virtfs-proxy-helper', 'virtfs-proxy-helper', - u'QEMU 9p virtfs proxy filesystem helper', - ['M. Mohan Kumar'], 1), - ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon', - ['Stefan Hajnoczi ', - 'Masayoshi Mizuma '], 1), -] diff --git a/docs/user/conf.py b/docs/user/conf.py deleted file mode 100644 index 4b09aedd454..00000000000 --- a/docs/user/conf.py +++ /dev/null @@ -1,15 +0,0 @@ -# -*- coding: utf-8 -*- -# -# QEMU documentation build configuration file for the 'user' manual. -# -# This includes the top level conf file and then makes any necessary tweak= s. -import sys -import os - -qemu_docdir =3D os.path.abspath("..") -parent_config =3D os.path.join(qemu_docdir, "conf.py") -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) - -# This slightly misuses the 'description', but is the best way to get -# the manual title to appear in the sidebar. -html_theme_options['description'] =3D u'User Mode Emulation User''s Guide' --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610471670; cv=none; d=zohomail.com; s=zohoarc; b=dE0qbtsOQLt4Ya1gFZXMAFK9TtnEge3I5D2Zs3q3xuew7o4QETFaGFBABJRPrctB15U9yiu8oOWxrb0rrhUcIJmYUUTHyhk5rBmmlB8bc34QMzB4ddsjUgwZbxpfXOhpRua101xegOtqy9qy6nHQXBALaboHY2cK1vmuLxlzZDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610471670; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IzBnQ5MyuscpiNLypCkOojFs/hlxwbq1JP9C+1j7a7s=; b=MWzWCx1d0BiCZWytX0F0zqmZp5eAsthexKOZNNFbiXnCC8UEo5hdm9QSTnYJT7Tfd/IeK0xG1YRuF1UvLnk1D7P2XiquLTmjbodmDLYYKgS8lmDWFWAIU5Izg1AfekBs3JbvQnrZl3/qm6gkAZf4CMozsybNgSIP1awdvaQgPTI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610471670108857.4378714091755; Tue, 12 Jan 2021 09:14:30 -0800 (PST) Received: from localhost ([::1]:40506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzNFU-0002HO-SP for importer@patchew.org; Tue, 12 Jan 2021 12:14:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzh-0001dK-Tb for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:09 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:55968) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzg-0006zq-50 for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:09 -0500 Received: by mail-wm1-x333.google.com with SMTP id c124so2505197wma.5 for ; Tue, 12 Jan 2021 08:58:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IzBnQ5MyuscpiNLypCkOojFs/hlxwbq1JP9C+1j7a7s=; b=MHGsccufrlBNi3k7ctS+fqmiVCwwqS0pqwbwzBB98G2ecF72kizgBnqCjExS9tBAwg 45n0T5qWRY1PgpQcw0dGcHKY4bC8ZyfWNZfioQaiAb57jvTlKpZfqOklthph0TQe7Tu1 QKg/Pmcywo0Fu8CegdeS5nT/yjkUcg/FKbu4uAMcGPq+10hxF7xCnXixbGB6Ay++2wDD ke0bBdcofgpjhlKegFg3sBMEx6AY013F08UQMbEE1Xkkd4Bamw8W0e4rLTMnQHIfxS8K x+8HTleV1+pPXFwmpWpTdpAAYvSqeWPpSaDjr39V33IxKof4KwNMBh6e/Z973D/bjDb8 1n0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IzBnQ5MyuscpiNLypCkOojFs/hlxwbq1JP9C+1j7a7s=; b=RMjOTNCkM4iT+64IBJMaR8rDrJenFw0RHhgHxAQnsZr/DmyK2uJROclRR9YbzGGyKV wbefNMQ0ADOetJ3bLrg9SDLJ0HMZhOuAawYaIcSwa/NMr/0Zt8b37hfiQ3OmqJfhtC8M VVJNYs94vWcZE0r+zExyFXchZxPyhSiGdnp80XY9E35kZdY1fu4f16paY8Za9fgtYQXB BEQEE5NenMRKjS2S1HmQlU0FbHnNKJpz4VaE1uQ/70ltRQevEA/zA+SaOusfzxq9/uh+ SiYQnFViLPEOlf0RDi35Bhf7xL16deOODcHE8qU2KVVPR7YlYzLWeyq9KtBkvTVyTdV+ wjXQ== X-Gm-Message-State: AOAM532UGdfSDomgrgLQqrsDA7BNZAv+WvCP0Ed1dkFEYRBoRSZH0JCN VTjVJWMBYhIfELylKTmUHCM31cA/rkEvgQ== X-Google-Smtp-Source: ABdhPJyC84AeTFrvcl8CZq1ClXdVdNppiX2QjakJM1EWMDnNSx6I5GBz9qtUzFF4ubHAM9V7VqfZ7w== X-Received: by 2002:a1c:2091:: with SMTP id g139mr160804wmg.133.1610470686001; Tue, 12 Jan 2021 08:58:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns Date: Tue, 12 Jan 2021 16:57:41 +0000 Message-Id: <20210112165750.30475-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In commit cd8be50e58f63413c0 we converted the A32 coprocessor insns to decodetree. This accidentally broke XScale/iWMMXt insns, because it moved the handling of "cp insns which are handled by looking up the cp register in the hashtable" from after the call to the legacy disas_xscale_insn() decode to before it, with the result that all XScale/iWMMXt insns now UNDEF. Update valid_cp() so that it knows that on XScale cp 0 and 1 are not standard coprocessor instructions; this will cause the decodetree trans_ functions to ignore them, so that execution will correctly get through to the legacy decode again. Cc: qemu-stable@nongnu.org Reported-by: Guenter Roeck Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Guenter Roeck Message-id: 20210108195157.32067-1-peter.maydell@linaro.org --- target/arm/translate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index f5acd32e76a..528b93dffa2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5282,7 +5282,14 @@ static bool valid_cp(DisasContext *s, int cp) * only cp14 and cp15 are valid, and other values aren't considered * to be in the coprocessor-instruction space at all. v8M still * permits coprocessors 0..7. + * For XScale, we must not decode the XScale cp0, cp1 space as + * a standard coprocessor insn, because we want to fall through to + * the legacy disas_xscale_insn() decoder after decodetree is done. */ + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp =3D=3D 0 || cp =3D=3D= 1)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_V8) && !arm_dc_feature(s, ARM_FEATURE_M)) { return cp >=3D 14; --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610471876; cv=none; d=zohomail.com; s=zohoarc; b=LvERZuEETLHADPviRMGQajmnOjlidXuhRN/0jMfiN62x4nn+W5G1RrrkE+PYhwYZNu0OGNUvRlAr1qvHMxl9OR2DTXqFHC8Xe3H0uH2JYLS1gg6DySHXQDVal4A/5ID6IWAzN7m3BhBh4Gq65pmkSaS+FO1/4unbj+fUrbYdva8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610471876; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L3GALm6LLUsg8yV05FVw9G4wDZ2dY+fohGIhr6EXc10=; b=UF+acBMuIeZ+51YZjmf+YH9vPZ20Yw0Wx+jwbL5DTHxt7dM/xYfO5CxglZL7w40dh4KyqAtYAVUJJbhxUX4nJC/4AgA/ieQzRUixFfmF+LfoigcPrK6mgRcv7Zt2eV4GgdA/fG5qrMjmwpxumyZa2h6GNuqvrk/ahLFEDxVMEgE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610471875996127.76466208626005; Tue, 12 Jan 2021 09:17:55 -0800 (PST) Received: from localhost ([::1]:48814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzNIo-0005xI-HE for importer@patchew.org; Tue, 12 Jan 2021 12:17:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzj-0001hR-Ac for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:11 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:55960) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzh-000708-AD for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:11 -0500 Received: by mail-wm1-x32a.google.com with SMTP id c124so2505314wma.5 for ; Tue, 12 Jan 2021 08:58:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=L3GALm6LLUsg8yV05FVw9G4wDZ2dY+fohGIhr6EXc10=; b=IIMbCDnNCjYXnPaxxV3eJdcHLm4Hcb5NgT0fPam9tsphULuxvo6dFalf39rwGNz8Zv ib44ohMa+K6uJsHBi+OnC5aHBHRzWonpvn/2SloOuoqRK2F0xWwAp54E5sxNT3OifosJ 2+uq+QDDudFG9AYx2EVeXq/K4EDDx+6VSfsx6Y4rE/ceoTBFtEHtQmoCVxnUAsZwWD5f X24mRZ8LaToYjxQitQ3vXtVOWWabHHw5MaQNCPWe/uYN83RVy0aU55NrLV/p10zgHoiC Sfil+s37x36L+SiZ+QcyL/iUHl+S7jux69f27MeZOqBOsUQ1s7S5EXAwdtl0WTQQKbwX 9LhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L3GALm6LLUsg8yV05FVw9G4wDZ2dY+fohGIhr6EXc10=; b=LnDwoaxTTjV1cvfu1jkEr9sOyI8UFAYedsA3E/QGY/hXRm8H63uibeMQGbr5AJLFkY aKDLv95CTeVtFXhh03KkUzmaMs64xTfQwQr9LpDYVYvc5QFjVooJ7OrvN0chByURRg+r CODTliwU4t6zwvNx2WV8mxZfgHhk6hdYjoeOXTwwJa5bW74s9NhnOe8hV+a8Fh3qJIhr DQtNrMV8Hs0yBDhLcUQ6MJk/ylRVacX4Di0bdqrAPYgnwDUK0hwtGTz5rKis6AvveQi7 C5uc5SfR7u0EDRkTQbOaoBpXIFzdyboo3VsswtBmbqH2gRYI/Kd6/K20Y0iJmYwRz3va 3VFA== X-Gm-Message-State: AOAM532Cqa/q+wiiT64wKzAfHU2bl+gbJPv//eHKF1pgp7GhC5Rk4V67 FkhFpci2ATUCmEZMsj+bCLBLy3ytAj2kzA== X-Google-Smtp-Source: ABdhPJzpijNpb9gjB+Xl19BGoMdAY57zBGBcLK/HhMr4jGJwguh8wq67ao8vpAJIeKrV7HUI3jvSwA== X-Received: by 2002:a05:600c:2303:: with SMTP id 3mr167563wmo.129.1610470687813; Tue, 12 Jan 2021 08:58:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value Date: Tue, 12 Jan 2021 16:57:42 +0000 Message-Id: <20210112165750.30475-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) A copy-and-paste error meant that the return value for register offset 0x44 (the RX Status FIFO PEEK register) returned a byte from a bogus offset in the rx status FIFO. Fix the typo. Cc: qemu-stable@nongnu.org Fixes: https://bugs.launchpad.net/qemu/+bug/1904954 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210108180401.2263-2-peter.maydell@linaro.org --- hw/net/lan9118.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index ab57c02c8e1..13d469fe24f 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -1206,7 +1206,7 @@ static uint64_t lan9118_readl(void *opaque, hwaddr of= fset, case 0x40: return rx_status_fifo_pop(s); case 0x44: - return s->rx_status_fifo[s->tx_status_fifo_head]; + return s->rx_status_fifo[s->rx_status_fifo_head]; case 0x48: return tx_status_fifo_pop(s); case 0x4c: --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610472059; cv=none; d=zohomail.com; s=zohoarc; b=mIeAYamldZRMJFcwxK+ed41wmvIkGKiGTK1rEHQhRTNZRI3ftWtaZI77RR4719sWRXokiHmPUbhy8fvLRbGBgJMYsB4aiId2IX079qBTlIKj39nn6IGhJTYmft+5XqotF/Wt+dYitn69QApKfy1X41s5OreNJ8lxzt56NAWwK30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610472059; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XIToQXuXYWfGEUbgT12NG+i3OudvqvCJSkXTNgJtBfE=; b=m7g1AJRrXURETpbIUtTtHt+X62CN5biihctvtwJzoxdH1bsTjCPnMHJ+RjOOzG2BvFe48t7QuHZwYIuvfH32euLAT65bHwsd83A43Zep61zV/KWxXx4yD7RsEr2fXzwSeEFfozElxpQLve30ET+Z4SA2v0w9JnyDIxBFSaGpk0Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161047205922364.95720183322021; Tue, 12 Jan 2021 09:20:59 -0800 (PST) Received: from localhost ([::1]:57204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzNLj-0001A1-UK for importer@patchew.org; Tue, 12 Jan 2021 12:20:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzm-0001pl-Iw for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:14 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:55963) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzi-00070G-Bx for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:14 -0500 Received: by mail-wm1-x32d.google.com with SMTP id c124so2505375wma.5 for ; Tue, 12 Jan 2021 08:58:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XIToQXuXYWfGEUbgT12NG+i3OudvqvCJSkXTNgJtBfE=; b=VJ7eift+frZtzE3Nvrb4hNe66udIxJtiSUodx3ClckCjQvSMEKForiBygauIcZRL6W 6+T1nF9VGDepYSy67/lsUNDAgb9/0SXaVCSlR2DCktvKUWQjgLwAZvIFGoz6qIkqlCJs gbEmdvfsftyo927WYSZpTqmqhazmsEEYCpiFG3/eMbjOkjs4Rj94eTW0W2PEkYSvCynM kZVHt9eVXAgx4jO4KgSj/zW5sfociuuaXMqo2amBw1mkzNidSezL50+u0R5yD2l/L//M k9SmclOMeBZJJxmCa+vscb81w3nvssbVSHWyYWIz2QWgZwzyiiL0o0vW2bBB+e8WrSx4 Z+uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XIToQXuXYWfGEUbgT12NG+i3OudvqvCJSkXTNgJtBfE=; b=SA9sCjmPl8e4B1fVt/St3jmoQiq5/CIfw9YfyHEjh+vtLdtAa/ZIahxHgifGxQRTfb N4FXqC/7DHsRBxdvy9iABZ0/qC6itsrLAl2Nbwup4rCI/nfrXLkntVuIUt46kRTuBDiy H5aaWr+dy3ckLik2y1y9CeXpMakrBBbwaC8ZoVlHXRk4x9wgTjdwq2EQsTkNFfGeiyWz +i76+nY4SD6elubWOESMyaJKNNhpSaSWem/0UBqMqFbStQt8ZsJ3Cu4+RZit3sX35gye iPKbvj8FCUucvslgG2QlZGt/EL2qXr2obEyrFWOmHwiWj8TDsdLI70LmM8D2Fv9u+ae0 Q0BQ== X-Gm-Message-State: AOAM530DBgYh5NUydWha/oQpAgORxtCCy+SZf6ZKS4Bd2hUbqJzoJLXz qBl4pSqqSBdbP/Ubusk9Mi83mhkt4WHV1g== X-Google-Smtp-Source: ABdhPJzr3h0UyahZ7lL/igsYrdJeSYB0/JjSHnawwVYKxaHnh0umlRSoObjMHCcBRHUz4D+sNFHFnw== X-Received: by 2002:a1c:4489:: with SMTP id r131mr240922wma.24.1610470688902; Tue, 12 Jan 2021 08:58:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets Date: Tue, 12 Jan 2021 16:57:43 +0000 Message-Id: <20210112165750.30475-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The lan9118 code mostly uses symbolic constants for register offsets; the exceptions are those which the datasheet doesn't give an official symbolic name to. Add some names for the registers which don't already have them, based on the longer names they are given in the memory map. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210108180401.2263-3-peter.maydell@linaro.org --- hw/net/lan9118.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index 13d469fe24f..abc796285ab 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -40,6 +40,17 @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);}= while (0) do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) #endif =20 +/* The tx and rx fifo ports are a range of aliased 32-bit registers */ +#define RX_DATA_FIFO_PORT_FIRST 0x00 +#define RX_DATA_FIFO_PORT_LAST 0x1f +#define TX_DATA_FIFO_PORT_FIRST 0x20 +#define TX_DATA_FIFO_PORT_LAST 0x3f + +#define RX_STATUS_FIFO_PORT 0x40 +#define RX_STATUS_FIFO_PEEK 0x44 +#define TX_STATUS_FIFO_PORT 0x48 +#define TX_STATUS_FIFO_PEEK 0x4c + #define CSR_ID_REV 0x50 #define CSR_IRQ_CFG 0x54 #define CSR_INT_STS 0x58 @@ -1020,7 +1031,8 @@ static void lan9118_writel(void *opaque, hwaddr offse= t, offset &=3D 0xff; =20 //DPRINTF("Write reg 0x%02x =3D 0x%08x\n", (int)offset, val); - if (offset >=3D 0x20 && offset < 0x40) { + if (offset >=3D TX_DATA_FIFO_PORT_FIRST && + offset <=3D TX_DATA_FIFO_PORT_LAST) { /* TX FIFO */ tx_fifo_push(s, val); return; @@ -1198,18 +1210,18 @@ static uint64_t lan9118_readl(void *opaque, hwaddr = offset, lan9118_state *s =3D (lan9118_state *)opaque; =20 //DPRINTF("Read reg 0x%02x\n", (int)offset); - if (offset < 0x20) { + if (offset <=3D RX_DATA_FIFO_PORT_LAST) { /* RX FIFO */ return rx_fifo_pop(s); } switch (offset) { - case 0x40: + case RX_STATUS_FIFO_PORT: return rx_status_fifo_pop(s); - case 0x44: + case RX_STATUS_FIFO_PEEK: return s->rx_status_fifo[s->rx_status_fifo_head]; - case 0x48: + case TX_STATUS_FIFO_PORT: return tx_status_fifo_pop(s); - case 0x4c: + case TX_STATUS_FIFO_PEEK: return s->tx_status_fifo[s->tx_status_fifo_head]; case CSR_ID_REV: return 0x01180001; --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610472270; cv=none; d=zohomail.com; s=zohoarc; b=B/6ZsRZr3Egz6kixQD0PdqMQUszwL2PEjF7MJa8MHty/BkdZLqMGtqJYwcMQ4rcsS9OYR+VqVTn9keWoZd8HoNMfA2C4FuteZM1K2tPKV7ZBlipISo5nXTTRk55ihDK5Fl1ISMnbtfB+BygQEJPThnulx7b/UDrFSZaVsMR8m18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610472270; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6nWn4AHavEYK2e+JK6ye9vjc5+qhENfILsI/oABYtSU=; b=BN9woSoGqg+F9gjsdaQDrKMSU9VgWXr+WqX2/JlNngMHJeVER9m9uJzL9R4cJ6/MCA9GmWUyAwBDMxSY0kfBB10cMpDlF8upJ6bpSdqOxwmt1YHULC1dpG8j9YWzYAjDQk/RXdlG/eynAkCOVw+lDJAMMojlMt23M215FGd9U3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610472270799938.8281979939026; Tue, 12 Jan 2021 09:24:30 -0800 (PST) Received: from localhost ([::1]:38296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzNPB-0005J7-F2 for importer@patchew.org; Tue, 12 Jan 2021 12:24:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzo-0001u5-4m for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:16 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:38430) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzk-00071V-HV for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:15 -0500 Received: by mail-wr1-x430.google.com with SMTP id r7so3246250wrc.5 for ; Tue, 12 Jan 2021 08:58:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6nWn4AHavEYK2e+JK6ye9vjc5+qhENfILsI/oABYtSU=; b=vVzhBW9DYPJgQXVmS4i5rY289yRlPFhQsjKV24s/kERxXgzceDMA7KQZkoKMA7NbmL 2YZGkb+UpZvxKTlkTffiqTOYEA51tmvvAVVvMIzOG9/gGTvnl9vfzucvndFGBUL/gFMm QTN9sWK3ePMkT1PAIFYAcN4LkH2FDawzEFYJ62YBNQ65EHHWSNL0Zf0dzm0e+c9mUihq LrT5QgsH6Leg1E0va2z6y14G+NVWOMN+S+Ry9TPdgy5dAqm//ke7kzEK/bblG1JA3MI0 2CKGrQWavxKbxMwAdnm2EOcqN+fIw4M1ptlWcG8NgZtvoYAl73jsaocuozGNJBheN7y8 jVhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6nWn4AHavEYK2e+JK6ye9vjc5+qhENfILsI/oABYtSU=; b=EiGURXsfhlhnQ017tNAXs8gwRgT3QCpKt/7/8BL8XKsoi+JGjrQ7GaamM6jrmeQHrn x8iZdpjgmOPJc8LmyIlxsqdSbD6svcGCMlIygtw0tOAxyJIyv5xJl3AKZsouYvr9dCA5 jQGIUwVQKkI1eQru+KY5E1IS+wxfJlH7eBg/v/c2XCFmKTeSq05Mr8111rOX4YLNvncV 3BdejtSbaWTxDO5/xTHxSfbhiNF/m53CY8VsOaLnTiLvqcsQkwktd/VOuP6Xuy+Woydc Xw3OMWr6c0PpMD2sVMIOnBf0PpbSOCDfUnCs6gtryE3ihoAYuDXpGwElTPnSTJAnj1Ul 0afw== X-Gm-Message-State: AOAM533CsxUlkpHFChAvWiOs2VJWJETMyoKCHX+IUEmXVbOJwjqNFIin Y30Whky0S7Lw8o/k+EV4e5ggU7JOl0f79Q== X-Google-Smtp-Source: ABdhPJw1ENRws/tugAyGnUqnWNk/CQO8+Izkj1DkjbRJ3zMNj5wc0N2x0qc/kEL1e7AvkIenyR9Nwg== X-Received: by 2002:a05:6000:1884:: with SMTP id a4mr5133619wri.42.1610470690558; Tue, 12 Jan 2021 08:58:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module Date: Tue, 12 Jan 2021 16:57:44 +0000 Message-Id: <20210112165750.30475-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu This patch allows NPCM7XX CLK module to compute clocks that are used by other NPCM7XX modules. Add a new struct NPCM7xxClockConverterState which represents a single converter. Each clock converter in CLK module represents one converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter takes one or more input clocks and converts them into one output clock. They form a clock hierarchy in the CLK module and are responsible for outputing clocks for various other modules in an NPCM7XX SoC. Each converter has a function pointer called "convert" which represents the unique logic for that converter. The clock contains two initialization information: ConverterInitInfo and ConverterConnectionInfo. They represent the vertices and edges in the clock diagram respectively. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Reviewed-by: Peter Maydell Message-id: 20210108190945.949196-2-wuhaotsh@google.com Signed-off-by: Peter Maydell --- include/hw/misc/npcm7xx_clk.h | 140 +++++- hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++- 2 files changed, 932 insertions(+), 13 deletions(-) diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h index 2338fbbdb5d..f641f95f3e6 100644 --- a/include/hw/misc/npcm7xx_clk.h +++ b/include/hw/misc/npcm7xx_clk.h @@ -17,6 +17,7 @@ #define NPCM7XX_CLK_H =20 #include "exec/memory.h" +#include "hw/clock.h" #include "hw/sysbus.h" =20 /* @@ -33,16 +34,151 @@ =20 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" =20 -typedef struct NPCM7xxCLKState { +/* Maximum amount of clock inputs in a SEL module. */ +#define NPCM7XX_CLK_SEL_MAX_INPUT 5 + +/* PLLs in CLK module. */ +typedef enum NPCM7xxClockPLL { + NPCM7XX_CLOCK_PLL0, + NPCM7XX_CLOCK_PLL1, + NPCM7XX_CLOCK_PLL2, + NPCM7XX_CLOCK_PLLG, + NPCM7XX_CLOCK_NR_PLLS, +} NPCM7xxClockPLL; + +/* SEL/MUX in CLK module. */ +typedef enum NPCM7xxClockSEL { + NPCM7XX_CLOCK_PIXCKSEL, + NPCM7XX_CLOCK_MCCKSEL, + NPCM7XX_CLOCK_CPUCKSEL, + NPCM7XX_CLOCK_CLKOUTSEL, + NPCM7XX_CLOCK_UARTCKSEL, + NPCM7XX_CLOCK_TIMCKSEL, + NPCM7XX_CLOCK_SDCKSEL, + NPCM7XX_CLOCK_GFXMSEL, + NPCM7XX_CLOCK_SUCKSEL, + NPCM7XX_CLOCK_NR_SELS, +} NPCM7xxClockSEL; + +/* Dividers in CLK module. */ +typedef enum NPCM7xxClockDivider { + NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */ + NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */ + NPCM7XX_CLOCK_MC_DIVIDER, + NPCM7XX_CLOCK_AXI_DIVIDER, + NPCM7XX_CLOCK_AHB_DIVIDER, + NPCM7XX_CLOCK_AHB3_DIVIDER, + NPCM7XX_CLOCK_SPI0_DIVIDER, + NPCM7XX_CLOCK_SPIX_DIVIDER, + NPCM7XX_CLOCK_APB1_DIVIDER, + NPCM7XX_CLOCK_APB2_DIVIDER, + NPCM7XX_CLOCK_APB3_DIVIDER, + NPCM7XX_CLOCK_APB4_DIVIDER, + NPCM7XX_CLOCK_APB5_DIVIDER, + NPCM7XX_CLOCK_CLKOUT_DIVIDER, + NPCM7XX_CLOCK_UART_DIVIDER, + NPCM7XX_CLOCK_TIMER_DIVIDER, + NPCM7XX_CLOCK_ADC_DIVIDER, + NPCM7XX_CLOCK_MMC_DIVIDER, + NPCM7XX_CLOCK_SDHC_DIVIDER, + NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */ + NPCM7XX_CLOCK_UTMI_DIVIDER, + NPCM7XX_CLOCK_NR_DIVIDERS, +} NPCM7xxClockConverter; + +typedef struct NPCM7xxCLKState NPCM7xxCLKState; + +/** + * struct NPCM7xxClockPLLState - A PLL module in CLK module. + * @name: The name of the module. + * @clk: The CLK module that owns this module. + * @clock_in: The input clock of this module. + * @clock_out: The output clock of this module. + * @reg: The control registers for this PLL module. + */ +typedef struct NPCM7xxClockPLLState { + DeviceState parent; + + const char *name; + NPCM7xxCLKState *clk; + Clock *clock_in; + Clock *clock_out; + + int reg; +} NPCM7xxClockPLLState; + +/** + * struct NPCM7xxClockSELState - A SEL module in CLK module. + * @name: The name of the module. + * @clk: The CLK module that owns this module. + * @input_size: The size of inputs of this module. + * @clock_in: The input clocks of this module. + * @clock_out: The output clocks of this module. + * @offset: The offset of this module in the control register. + * @len: The length of this module in the control register. + */ +typedef struct NPCM7xxClockSELState { + DeviceState parent; + + const char *name; + NPCM7xxCLKState *clk; + uint8_t input_size; + Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT]; + Clock *clock_out; + + int offset; + int len; +} NPCM7xxClockSELState; + +/** + * struct NPCM7xxClockDividerState - A Divider module in CLK module. + * @name: The name of the module. + * @clk: The CLK module that owns this module. + * @clock_in: The input clock of this module. + * @clock_out: The output clock of this module. + * @divide: The function the divider uses to divide the input. + * @reg: The index of the control register that contains the divisor. + * @offset: The offset of the divisor in the control register. + * @len: The length of the divisor in the control register. + * @divisor: The divisor for a constant divisor + */ +typedef struct NPCM7xxClockDividerState { + DeviceState parent; + + const char *name; + NPCM7xxCLKState *clk; + Clock *clock_in; + Clock *clock_out; + + uint32_t (*divide)(struct NPCM7xxClockDividerState *s); + union { + struct { + int reg; + int offset; + int len; + }; + int divisor; + }; +} NPCM7xxClockDividerState; + +struct NPCM7xxCLKState { SysBusDevice parent; =20 MemoryRegion iomem; =20 + /* Clock converters */ + NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; + NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; + NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; + uint32_t regs[NPCM7XX_CLK_NR_REGS]; =20 /* Time reference for SECCNT and CNTR25M, initialized by power on rese= t */ int64_t ref_ns; -} NPCM7xxCLKState; + + /* The incoming reference clock. */ + Clock *clkref; +}; =20 #define TYPE_NPCM7XX_CLK "npcm7xx-clk" #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX= _CLK) diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index 6732437fe22..48bc9bdda55 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -18,6 +18,7 @@ =20 #include "hw/misc/npcm7xx_clk.h" #include "hw/timer/npcm7xx_timer.h" +#include "hw/qdev-clock.h" #include "migration/vmstate.h" #include "qemu/error-report.h" #include "qemu/log.h" @@ -27,9 +28,22 @@ #include "trace.h" #include "sysemu/watchdog.h" =20 +/* + * The reference clock hz, and the SECCNT and CNTR25M registers in this mo= dule, + * is always 25 MHz. + */ +#define NPCM7XX_CLOCK_REF_HZ (25000000) + +/* Register Field Definitions */ +#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ + #define PLLCON_LOKI BIT(31) #define PLLCON_LOKS BIT(30) #define PLLCON_PWDEN BIT(12) +#define PLLCON_FBDV(con) extract32((con), 16, 12) +#define PLLCON_OTDV2(con) extract32((con), 13, 3) +#define PLLCON_OTDV1(con) extract32((con), 8, 3) +#define PLLCON_INDV(con) extract32((con), 0, 6) =20 enum NPCM7xxCLKRegisters { NPCM7XX_CLK_CLKEN1, @@ -89,12 +103,609 @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_N= R_REGS] =3D { [NPCM7XX_CLK_AHBCKFI] =3D 0x000000c8, }; =20 -/* Register Field Definitions */ -#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ - /* The number of watchdogs that can trigger a reset. */ #define NPCM7XX_NR_WATCHDOGS (3) =20 +/* Clock converter functions */ + +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll" +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \ + (obj), TYPE_NPCM7XX_CLOCK_PLL) +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel" +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \ + (obj), TYPE_NPCM7XX_CLOCK_SEL) +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider" +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \ + (obj), TYPE_NPCM7XX_CLOCK_DIVIDER) + +static void npcm7xx_clk_update_pll(void *opaque) +{ + NPCM7xxClockPLLState *s =3D opaque; + uint32_t con =3D s->clk->regs[s->reg]; + uint64_t freq; + + /* The PLL is grounded if it is not locked yet. */ + if (con & PLLCON_LOKI) { + freq =3D clock_get_hz(s->clock_in); + freq *=3D PLLCON_FBDV(con); + freq /=3D PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); + } else { + freq =3D 0; + } + + clock_update_hz(s->clock_out, freq); +} + +static void npcm7xx_clk_update_sel(void *opaque) +{ + NPCM7xxClockSELState *s =3D opaque; + uint32_t index =3D extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offs= et, + s->len); + + if (index >=3D s->input_size) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SEL index: %u out of range\n", + __func__, index); + index =3D 0; + } + clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index])); +} + +static void npcm7xx_clk_update_divider(void *opaque) +{ + NPCM7xxClockDividerState *s =3D opaque; + uint32_t freq; + + freq =3D s->divide(s); + clock_update_hz(s->clock_out, freq); +} + +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s) +{ + return clock_get_hz(s->clock_in) / s->divisor; +} + +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s) +{ + return clock_get_hz(s->clock_in) / + (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); +} + +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s) +{ + return divide_by_reg_divisor(s) / 2; +} + +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s) +{ + return clock_get_hz(s->clock_in) >> + extract32(s->clk->regs[s->reg], s->offset, s->len); +} + +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg) +{ + switch (reg) { + case NPCM7XX_CLK_PLLCON0: + return NPCM7XX_CLOCK_PLL0; + case NPCM7XX_CLK_PLLCON1: + return NPCM7XX_CLOCK_PLL1; + case NPCM7XX_CLK_PLLCON2: + return NPCM7XX_CLOCK_PLL2; + case NPCM7XX_CLK_PLLCONG: + return NPCM7XX_CLOCK_PLLG; + default: + g_assert_not_reached(); + } +} + +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) +{ + int i; + + for (i =3D 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + npcm7xx_clk_update_pll(&clk->plls[i]); + } +} + +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) +{ + int i; + + for (i =3D 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + npcm7xx_clk_update_sel(&clk->sels[i]); + } +} + +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) +{ + int i; + + for (i =3D 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + npcm7xx_clk_update_divider(&clk->dividers[i]); + } +} + +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) +{ + clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); + npcm7xx_clk_update_all_plls(clk); + npcm7xx_clk_update_all_sels(clk); + npcm7xx_clk_update_all_dividers(clk); +} + +/* Types of clock sources. */ +typedef enum ClockSrcType { + CLKSRC_REF, + CLKSRC_PLL, + CLKSRC_SEL, + CLKSRC_DIV, +} ClockSrcType; + +typedef struct PLLInitInfo { + const char *name; + ClockSrcType src_type; + int src_index; + int reg; + const char *public_name; +} PLLInitInfo; + +typedef struct SELInitInfo { + const char *name; + uint8_t input_size; + ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT]; + int src_index[NPCM7XX_CLK_SEL_MAX_INPUT]; + int offset; + int len; + const char *public_name; +} SELInitInfo; + +typedef struct DividerInitInfo { + const char *name; + ClockSrcType src_type; + int src_index; + uint32_t (*divide)(NPCM7xxClockDividerState *s); + int reg; /* not used when type =3D=3D CONSTANT */ + int offset; /* not used when type =3D=3D CONSTANT */ + int len; /* not used when type =3D=3D CONSTANT */ + int divisor; /* used only when type =3D=3D CONSTANT */ + const char *public_name; +} DividerInitInfo; + +static const PLLInitInfo pll_init_info_list[] =3D { + [NPCM7XX_CLOCK_PLL0] =3D { + .name =3D "pll0", + .src_type =3D CLKSRC_REF, + .reg =3D NPCM7XX_CLK_PLLCON0, + }, + [NPCM7XX_CLOCK_PLL1] =3D { + .name =3D "pll1", + .src_type =3D CLKSRC_REF, + .reg =3D NPCM7XX_CLK_PLLCON1, + }, + [NPCM7XX_CLOCK_PLL2] =3D { + .name =3D "pll2", + .src_type =3D CLKSRC_REF, + .reg =3D NPCM7XX_CLK_PLLCON2, + }, + [NPCM7XX_CLOCK_PLLG] =3D { + .name =3D "pllg", + .src_type =3D CLKSRC_REF, + .reg =3D NPCM7XX_CLK_PLLCONG, + }, +}; + +static const SELInitInfo sel_init_info_list[] =3D { + [NPCM7XX_CLOCK_PIXCKSEL] =3D { + .name =3D "pixcksel", + .input_size =3D 2, + .src_type =3D {CLKSRC_PLL, CLKSRC_REF}, + .src_index =3D {NPCM7XX_CLOCK_PLLG, 0}, + .offset =3D 5, + .len =3D 1, + .public_name =3D "pixel-clock", + }, + [NPCM7XX_CLOCK_MCCKSEL] =3D { + .name =3D "mccksel", + .input_size =3D 4, + .src_type =3D {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF, + /*MCBPCK, shouldn't be used in normal operation*/ + CLKSRC_REF}, + .src_index =3D {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0}, + .offset =3D 12, + .len =3D 2, + .public_name =3D "mc-phy-clock", + }, + [NPCM7XX_CLOCK_CPUCKSEL] =3D { + .name =3D "cpucksel", + .input_size =3D 4, + .src_type =3D {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, + /*SYSBPCK, shouldn't be used in normal operation*/ + CLKSRC_REF}, + .src_index =3D {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0}, + .offset =3D 0, + .len =3D 2, + .public_name =3D "system-clock", + }, + [NPCM7XX_CLOCK_CLKOUTSEL] =3D { + .name =3D "clkoutsel", + .input_size =3D 5, + .src_type =3D {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, + CLKSRC_PLL, CLKSRC_DIV}, + .src_index =3D {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2}, + .offset =3D 18, + .len =3D 3, + .public_name =3D "tock", + }, + [NPCM7XX_CLOCK_UARTCKSEL] =3D { + .name =3D "uartcksel", + .input_size =3D 4, + .src_type =3D {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index =3D {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset =3D 8, + .len =3D 2, + }, + [NPCM7XX_CLOCK_TIMCKSEL] =3D { + .name =3D "timcksel", + .input_size =3D 4, + .src_type =3D {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index =3D {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset =3D 14, + .len =3D 2, + }, + [NPCM7XX_CLOCK_SDCKSEL] =3D { + .name =3D "sdcksel", + .input_size =3D 4, + .src_type =3D {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index =3D {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset =3D 6, + .len =3D 2, + }, + [NPCM7XX_CLOCK_GFXMSEL] =3D { + .name =3D "gfxmksel", + .input_size =3D 2, + .src_type =3D {CLKSRC_REF, CLKSRC_PLL}, + .src_index =3D {0, NPCM7XX_CLOCK_PLL2}, + .offset =3D 21, + .len =3D 1, + }, + [NPCM7XX_CLOCK_SUCKSEL] =3D { + .name =3D "sucksel", + .input_size =3D 4, + .src_type =3D {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index =3D {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset =3D 10, + .len =3D 2, + }, +}; + +static const DividerInitInfo divider_init_info_list[] =3D { + [NPCM7XX_CLOCK_PLL1D2] =3D { + .name =3D "pll1d2", + .src_type =3D CLKSRC_PLL, + .src_index =3D NPCM7XX_CLOCK_PLL1, + .divide =3D divide_by_constant, + .divisor =3D 2, + }, + [NPCM7XX_CLOCK_PLL2D2] =3D { + .name =3D "pll2d2", + .src_type =3D CLKSRC_PLL, + .src_index =3D NPCM7XX_CLOCK_PLL2, + .divide =3D divide_by_constant, + .divisor =3D 2, + }, + [NPCM7XX_CLOCK_MC_DIVIDER] =3D { + .name =3D "mc-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_MCCKSEL, + .divide =3D divide_by_constant, + .divisor =3D 2, + .public_name =3D "mc-clock" + }, + [NPCM7XX_CLOCK_AXI_DIVIDER] =3D { + .name =3D "axi-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_CPUCKSEL, + .divide =3D shift_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV1, + .offset =3D 0, + .len =3D 1, + .public_name =3D "clk2" + }, + [NPCM7XX_CLOCK_AHB_DIVIDER] =3D { + .name =3D "ahb-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AXI_DIVIDER, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV1, + .offset =3D 26, + .len =3D 2, + .public_name =3D "clk4" + }, + [NPCM7XX_CLOCK_AHB3_DIVIDER] =3D { + .name =3D "ahb3-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV1, + .offset =3D 6, + .len =3D 5, + .public_name =3D "ahb3-spi3-clock" + }, + [NPCM7XX_CLOCK_SPI0_DIVIDER] =3D { + .name =3D "spi0-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV3, + .offset =3D 6, + .len =3D 5, + .public_name =3D "spi0-clock", + }, + [NPCM7XX_CLOCK_SPIX_DIVIDER] =3D { + .name =3D "spix-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV3, + .offset =3D 1, + .len =3D 5, + .public_name =3D "spix-clock", + }, + [NPCM7XX_CLOCK_APB1_DIVIDER] =3D { + .name =3D "apb1-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D shift_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 24, + .len =3D 2, + .public_name =3D "apb1-clock", + }, + [NPCM7XX_CLOCK_APB2_DIVIDER] =3D { + .name =3D "apb2-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D shift_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 26, + .len =3D 2, + .public_name =3D "apb2-clock", + }, + [NPCM7XX_CLOCK_APB3_DIVIDER] =3D { + .name =3D "apb3-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D shift_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 28, + .len =3D 2, + .public_name =3D "apb3-clock", + }, + [NPCM7XX_CLOCK_APB4_DIVIDER] =3D { + .name =3D "apb4-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D shift_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 30, + .len =3D 2, + .public_name =3D "apb4-clock", + }, + [NPCM7XX_CLOCK_APB5_DIVIDER] =3D { + .name =3D "apb5-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_AHB_DIVIDER, + .divide =3D shift_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 22, + .len =3D 2, + .public_name =3D "apb5-clock", + }, + [NPCM7XX_CLOCK_CLKOUT_DIVIDER] =3D { + .name =3D "clkout-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_CLKOUTSEL, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 16, + .len =3D 5, + .public_name =3D "clkout", + }, + [NPCM7XX_CLOCK_UART_DIVIDER] =3D { + .name =3D "uart-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_UARTCKSEL, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV1, + .offset =3D 16, + .len =3D 5, + .public_name =3D "uart-clock", + }, + [NPCM7XX_CLOCK_TIMER_DIVIDER] =3D { + .name =3D "timer-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_TIMCKSEL, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV1, + .offset =3D 21, + .len =3D 5, + .public_name =3D "timer-clock", + }, + [NPCM7XX_CLOCK_ADC_DIVIDER] =3D { + .name =3D "adc-divider", + .src_type =3D CLKSRC_DIV, + .src_index =3D NPCM7XX_CLOCK_TIMER_DIVIDER, + .divide =3D shift_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV1, + .offset =3D 28, + .len =3D 3, + .public_name =3D "adc-clock", + }, + [NPCM7XX_CLOCK_MMC_DIVIDER] =3D { + .name =3D "mmc-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_SDCKSEL, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV1, + .offset =3D 11, + .len =3D 5, + .public_name =3D "mmc-clock", + }, + [NPCM7XX_CLOCK_SDHC_DIVIDER] =3D { + .name =3D "sdhc-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_SDCKSEL, + .divide =3D divide_by_reg_divisor_times_2, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 0, + .len =3D 4, + .public_name =3D "sdhc-clock", + }, + [NPCM7XX_CLOCK_GFXM_DIVIDER] =3D { + .name =3D "gfxm-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_GFXMSEL, + .divide =3D divide_by_constant, + .divisor =3D 3, + .public_name =3D "gfxm-clock", + }, + [NPCM7XX_CLOCK_UTMI_DIVIDER] =3D { + .name =3D "utmi-divider", + .src_type =3D CLKSRC_SEL, + .src_index =3D NPCM7XX_CLOCK_SUCKSEL, + .divide =3D divide_by_reg_divisor, + .reg =3D NPCM7XX_CLK_CLKDIV2, + .offset =3D 8, + .len =3D 5, + .public_name =3D "utmi-clock", + }, +}; + +static void npcm7xx_clk_pll_init(Object *obj) +{ + NPCM7xxClockPLLState *pll =3D NPCM7XX_CLOCK_PLL(obj); + + pll->clock_in =3D qdev_init_clock_in(DEVICE(pll), "clock-in", + npcm7xx_clk_update_pll, pll); + pll->clock_out =3D qdev_init_clock_out(DEVICE(pll), "clock-out"); +} + +static void npcm7xx_clk_sel_init(Object *obj) +{ + int i; + NPCM7xxClockSELState *sel =3D NPCM7XX_CLOCK_SEL(obj); + + for (i =3D 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { + sel->clock_in[i] =3D qdev_init_clock_in(DEVICE(sel), + g_strdup_printf("clock-in[%d]", i), + npcm7xx_clk_update_sel, sel); + } + sel->clock_out =3D qdev_init_clock_out(DEVICE(sel), "clock-out"); +} +static void npcm7xx_clk_divider_init(Object *obj) +{ + NPCM7xxClockDividerState *div =3D NPCM7XX_CLOCK_DIVIDER(obj); + + div->clock_in =3D qdev_init_clock_in(DEVICE(div), "clock-in", + npcm7xx_clk_update_divider, div); + div->clock_out =3D qdev_init_clock_out(DEVICE(div), "clock-out"); +} + +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, + NPCM7xxCLKState *clk, const PLLInitInfo *init_info) +{ + pll->name =3D init_info->name; + pll->clk =3D clk; + pll->reg =3D init_info->reg; + if (init_info->public_name !=3D NULL) { + qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), + init_info->public_name); + } +} + +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, + NPCM7xxCLKState *clk, const SELInitInfo *init_info) +{ + int input_size =3D init_info->input_size; + + sel->name =3D init_info->name; + sel->clk =3D clk; + sel->input_size =3D init_info->input_size; + g_assert(input_size <=3D NPCM7XX_CLK_SEL_MAX_INPUT); + sel->offset =3D init_info->offset; + sel->len =3D init_info->len; + if (init_info->public_name !=3D NULL) { + qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk), + init_info->public_name); + } +} + +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div, + NPCM7xxCLKState *clk, const DividerInitInfo *init_info) +{ + div->name =3D init_info->name; + div->clk =3D clk; + + div->divide =3D init_info->divide; + if (div->divide =3D=3D divide_by_constant) { + div->divisor =3D init_info->divisor; + } else { + div->reg =3D init_info->reg; + div->offset =3D init_info->offset; + div->len =3D init_info->len; + } + if (init_info->public_name !=3D NULL) { + qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk), + init_info->public_name); + } +} + +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, + int index) +{ + switch (type) { + case CLKSRC_REF: + return clk->clkref; + case CLKSRC_PLL: + return clk->plls[index].clock_out; + case CLKSRC_SEL: + return clk->sels[index].clock_out; + case CLKSRC_DIV: + return clk->dividers[index].clock_out; + default: + g_assert_not_reached(); + } +} + +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) +{ + int i, j; + Clock *src; + + for (i =3D 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + src =3D npcm7xx_get_clock(clk, pll_init_info_list[i].src_type, + pll_init_info_list[i].src_index); + clock_set_source(clk->plls[i].clock_in, src); + } + for (i =3D 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + for (j =3D 0; j < sel_init_info_list[i].input_size; ++j) { + src =3D npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[= j], + sel_init_info_list[i].src_index[j]); + clock_set_source(clk->sels[i].clock_in[j], src); + } + } + for (i =3D 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + src =3D npcm7xx_get_clock(clk, divider_init_info_list[i].src_type, + divider_init_info_list[i].src_index); + clock_set_source(clk->dividers[i].clock_in, src); + } +} + static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned siz= e) { uint32_t reg =3D offset / sizeof(uint32_t); @@ -129,7 +740,7 @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr o= ffset, unsigned size) * * The 4 LSBs are always zero: (1e9 / 640) << 4 =3D 25000000. */ - value =3D (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_= HZ; + value =3D (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_= HZ; break; =20 default: @@ -183,6 +794,20 @@ static void npcm7xx_clk_write(void *opaque, hwaddr off= set, value |=3D (value & PLLCON_LOKS); } } + /* Only update PLL when it is locked. */ + if (value & PLLCON_LOKI) { + npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); + } + break; + + case NPCM7XX_CLK_CLKSEL: + npcm7xx_clk_update_all_sels(s); + break; + + case NPCM7XX_CLK_CLKDIV1: + case NPCM7XX_CLK_CLKDIV2: + case NPCM7XX_CLK_CLKDIV3: + npcm7xx_clk_update_all_dividers(s); break; =20 case NPCM7XX_CLK_CNTR25M: @@ -234,6 +859,7 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetT= ype type) case RESET_TYPE_COLD: memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); s->ref_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + npcm7xx_clk_update_all_clocks(s); return; } =20 @@ -245,6 +871,42 @@ static void npcm7xx_clk_enter_reset(Object *obj, Reset= Type type) __func__, type); } =20 +static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) +{ + int i; + + s->clkref =3D qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL); + + /* First pass: init all converter modules */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) !=3D NPCM7XX_CLOCK_NR= _PLLS); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) !=3D NPCM7XX_CLOCK_NR= _SELS); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list) + !=3D NPCM7XX_CLOCK_NR_DIVIDERS); + for (i =3D 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + object_initialize_child(OBJECT(s), pll_init_info_list[i].name, + &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); + npcm7xx_init_clock_pll(&s->plls[i], s, + &pll_init_info_list[i]); + } + for (i =3D 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + object_initialize_child(OBJECT(s), sel_init_info_list[i].name, + &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL); + npcm7xx_init_clock_sel(&s->sels[i], s, + &sel_init_info_list[i]); + } + for (i =3D 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + object_initialize_child(OBJECT(s), divider_init_info_list[i].name, + &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER); + npcm7xx_init_clock_divider(&s->dividers[i], s, + ÷r_init_info_list[i]); + } + + /* Second pass: connect converter modules */ + npcm7xx_connect_clocks(s); + + clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); +} + static void npcm7xx_clk_init(Object *obj) { NPCM7xxCLKState *s =3D NPCM7XX_CLK(obj); @@ -252,21 +914,114 @@ static void npcm7xx_clk_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, TYPE_NPCM7XX_CLK, 4 * KiB); sysbus_init_mmio(&s->parent, &s->iomem); - qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, - NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); } =20 -static const VMStateDescription vmstate_npcm7xx_clk =3D { - .name =3D "npcm7xx-clk", +static int npcm7xx_clk_post_load(void *opaque, int version_id) +{ + if (version_id >=3D 1) { + NPCM7xxCLKState *clk =3D opaque; + + npcm7xx_clk_update_all_clocks(clk); + } + + return 0; +} + +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp) +{ + int i; + NPCM7xxCLKState *s =3D NPCM7XX_CLK(dev); + + qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, + NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); + npcm7xx_clk_init_clock_hierarchy(s); + + /* Realize child devices */ + for (i =3D 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { + return; + } + } + for (i =3D 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) { + return; + } + } + for (i =3D 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) { + return; + } + } +} + +static const VMStateDescription vmstate_npcm7xx_clk_pll =3D { + .name =3D "npcm7xx-clock-pll", .version_id =3D 0, .minimum_version_id =3D 0, - .fields =3D (VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), - VMSTATE_INT64(ref_ns, NPCM7xxCLKState), + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState), VMSTATE_END_OF_LIST(), }, }; =20 +static const VMStateDescription vmstate_npcm7xx_clk_sel =3D { + .name =3D "npcm7xx-clock-sel", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState, + NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_npcm7xx_clk_divider =3D { + .name =3D "npcm7xx-clock-divider", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_npcm7xx_clk =3D { + .name =3D "npcm7xx-clk", + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D npcm7xx_clk_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), + VMSTATE_INT64(ref_ns, NPCM7xxCLKState), + VMSTATE_CLOCK(clkref, NPCM7xxCLKState), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM7xx Clock PLL Module"; + dc->vmsd =3D &vmstate_npcm7xx_clk_pll; +} + +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM7xx Clock SEL Module"; + dc->vmsd =3D &vmstate_npcm7xx_clk_sel; +} + +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM7xx Clock Divider Module"; + dc->vmsd =3D &vmstate_npcm7xx_clk_divider; +} + static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) { ResettableClass *rc =3D RESETTABLE_CLASS(klass); @@ -276,9 +1031,34 @@ static void npcm7xx_clk_class_init(ObjectClass *klass= , void *data) =20 dc->desc =3D "NPCM7xx Clock Control Registers"; dc->vmsd =3D &vmstate_npcm7xx_clk; + dc->realize =3D npcm7xx_clk_realize; rc->phases.enter =3D npcm7xx_clk_enter_reset; } =20 +static const TypeInfo npcm7xx_clk_pll_info =3D { + .name =3D TYPE_NPCM7XX_CLOCK_PLL, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(NPCM7xxClockPLLState), + .instance_init =3D npcm7xx_clk_pll_init, + .class_init =3D npcm7xx_clk_pll_class_init, +}; + +static const TypeInfo npcm7xx_clk_sel_info =3D { + .name =3D TYPE_NPCM7XX_CLOCK_SEL, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(NPCM7xxClockSELState), + .instance_init =3D npcm7xx_clk_sel_init, + .class_init =3D npcm7xx_clk_sel_class_init, +}; + +static const TypeInfo npcm7xx_clk_divider_info =3D { + .name =3D TYPE_NPCM7XX_CLOCK_DIVIDER, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(NPCM7xxClockDividerState), + .instance_init =3D npcm7xx_clk_divider_init, + .class_init =3D npcm7xx_clk_divider_class_init, +}; + static const TypeInfo npcm7xx_clk_info =3D { .name =3D TYPE_NPCM7XX_CLK, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -289,6 +1069,9 @@ static const TypeInfo npcm7xx_clk_info =3D { =20 static void npcm7xx_clk_register_type(void) { + type_register_static(&npcm7xx_clk_pll_info); + type_register_static(&npcm7xx_clk_sel_info); + type_register_static(&npcm7xx_clk_divider_info); type_register_static(&npcm7xx_clk_info); } type_init(npcm7xx_clk_register_type); --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610472065; cv=none; d=zohomail.com; s=zohoarc; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xPY8nyqplCCAoQ3I/U15xp4D5EkhgfGsX5UQScmFzGo=; b=EI/NM5hvz5HanCOJBBp4lj4UFf7E2g1ICmDPUIZ6iTDmpMaOatZQ4QKquh/bGljoIQ wLZWTOFqk241G1JvHmys9fewaTlRSaEBiosPGx35PCldIKxzdk+8Z+SY2ysDFS3F7Sla W0xBi9zOKOoSBMbo4UsNSrDI7nlhMjUX0cWoOeYugHKSZHBxqetOtSL0KftF7n0NVThw Mfg+0ncXNj0qm8iZZydIgTcTjG9jer2juylrdD/hqoOk6n+mCQjCT2atx0G/lBxw5bud HYv3yC85g6xCEhZQCU6QbFLGHRGgNJKnoqJVDR3bfg0aGhIKnwx5zEnX4+oI4XUBJUSK D1kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xPY8nyqplCCAoQ3I/U15xp4D5EkhgfGsX5UQScmFzGo=; b=PpcAqof0aRO2pM+uvFJPt2y4PuLTcrD3iAr0y7DCdgp19h4952DN9n5hwsqnCptI5X CNb+4l/ULMlS3CXHrwlqzE8UGNfz2oEwpOW7Bo+yZtbky2UiuTDaQ+sXppgpG4dAXy5R k1G9bvh3+1qXHdwtrJbFvdm1USgpKwlBIXc6GKtJvZUsmdzSyprbvqSOhKOC6ZQNFvku cTIrdHXja6BgbNGpg7xHl65ViONdsF/6D3Qhbum6Uce7T9wsssnuG0OCusfFXpsolghy F2AghpAyTyYFDnYrlllbXjKn3jgYXkHsumaj8WP3Vv4TXZLv2idDqo1lzJ1Co3SXFigM 1r7w== X-Gm-Message-State: AOAM533OWBXz2fSxOLkGd3r3H2DsF3z2WEMQG1bD0dhSfVuwwTMHQcgL qzG7z51B+L4X578O2cDlSxX4siMasaqSPQ== X-Google-Smtp-Source: ABdhPJxy64wh6atzG3fGNoIxoaMyE/HoWrhYeuxx64qzKRuCFo4Fm3ZRR6rxymA2YtHVuumPvD/XJg== X-Received: by 2002:a05:600c:3549:: with SMTP id i9mr165297wmq.89.1610470692038; Tue, 12 Jan 2021 08:58:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock Date: Tue, 12 Jan 2021 16:57:45 +0000 Message-Id: <20210112165750.30475-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu This patch makes NPCM7XX Timer to use a the timer clock generated by the CLK module instead of the magic number TIMER_REF_HZ. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Message-id: 20210108190945.949196-3-wuhaotsh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/misc/npcm7xx_clk.h | 6 ----- include/hw/timer/npcm7xx_timer.h | 1 + hw/arm/npcm7xx.c | 5 ++++ hw/timer/npcm7xx_timer.c | 39 +++++++++++++++----------------- 4 files changed, 24 insertions(+), 27 deletions(-) diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h index f641f95f3e6..d5c8d16ca42 100644 --- a/include/hw/misc/npcm7xx_clk.h +++ b/include/hw/misc/npcm7xx_clk.h @@ -20,12 +20,6 @@ #include "hw/clock.h" #include "hw/sysbus.h" =20 -/* - * The reference clock frequency for the timer modules, and the SECCNT and - * CNTR25M registers in this module, is always 25 MHz. - */ -#define NPCM7XX_TIMER_REF_HZ (25000000) - /* * Number of registers in our device state structure. Don't change this wi= thout * incrementing the version_id in the vmstate. diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_ti= mer.h index 6993fd723a1..d45c051b56a 100644 --- a/include/hw/timer/npcm7xx_timer.h +++ b/include/hw/timer/npcm7xx_timer.h @@ -101,6 +101,7 @@ struct NPCM7xxTimerCtrlState { =20 uint32_t tisr; =20 + Clock *clock; NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL]; NPCM7xxWatchdogTimer watchdog_timer; }; diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 47e2b6fc400..fabfb1697ba 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -22,6 +22,7 @@ #include "hw/char/serial.h" #include "hw/loader.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/units.h" @@ -420,6 +421,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) int first_irq; int j; =20 + /* Connect the timer clock. */ + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_= out( + DEVICE(&s->clk), "timer-clock")); + sysbus_realize(sbd, &error_abort); sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); =20 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index d24445bd6e4..36e2c07db26 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -17,8 +17,8 @@ #include "qemu/osdep.h" =20 #include "hw/irq.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" -#include "hw/misc/npcm7xx_clk.h" #include "hw/timer/npcm7xx_timer.h" #include "migration/vmstate.h" #include "qemu/bitops.h" @@ -128,23 +128,18 @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) /* Convert a timer cycle count to a time interval in nanoseconds. */ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) { - int64_t ns =3D count; + int64_t ticks =3D count; =20 - ns *=3D NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; - ns *=3D npcm7xx_tcsr_prescaler(t->tcsr); + ticks *=3D npcm7xx_tcsr_prescaler(t->tcsr); =20 - return ns; + return clock_ticks_to_ns(t->ctrl->clock, ticks); } =20 /* Convert a time interval in nanoseconds to a timer cycle count. */ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) { - int64_t count; - - count =3D ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ); - count /=3D npcm7xx_tcsr_prescaler(t->tcsr); - - return count; + return ns / clock_ticks_to_ns(t->ctrl->clock, + npcm7xx_tcsr_prescaler(t->tcsr)); } =20 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTime= r *t) @@ -166,8 +161,8 @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const = NPCM7xxWatchdogTimer *t) static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, int64_t cycles) { - uint32_t prescaler =3D npcm7xx_watchdog_timer_prescaler(t); - int64_t ns =3D (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycle= s; + int64_t ticks =3D cycles * npcm7xx_watchdog_timer_prescaler(t); + int64_t ns =3D clock_ticks_to_ns(t->ctrl->clock, ticks); =20 /* * The reset function always clears the current timer. The caller of t= he @@ -176,7 +171,6 @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xx= WatchdogTimer *t, */ npcm7xx_timer_clear(&t->base_timer); =20 - ns *=3D prescaler; t->base_timer.remaining_ns =3D ns; } =20 @@ -606,10 +600,11 @@ static void npcm7xx_timer_hold_reset(Object *obj) qemu_irq_lower(s->watchdog_timer.irq); } =20 -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) +static void npcm7xx_timer_init(Object *obj) { - NPCM7xxTimerCtrlState *s =3D NPCM7XX_TIMER(dev); - SysBusDevice *sbd =3D &s->parent; + NPCM7xxTimerCtrlState *s =3D NPCM7XX_TIMER(obj); + DeviceState *dev =3D DEVICE(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); int i; NPCM7xxWatchdogTimer *w; =20 @@ -627,11 +622,12 @@ static void npcm7xx_timer_realize(DeviceState *dev, E= rror **errp) npcm7xx_watchdog_timer_expired, w); sysbus_init_irq(sbd, &w->irq); =20 - memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s, + memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, TYPE_NPCM7XX_TIMER, 4 * KiB); sysbus_init_mmio(sbd, &s->iomem); qdev_init_gpio_out_named(dev, &w->reset_signal, NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); + s->clock =3D qdev_init_clock_in(dev, "clock", NULL, NULL); } =20 static const VMStateDescription vmstate_npcm7xx_base_timer =3D { @@ -675,10 +671,11 @@ static const VMStateDescription vmstate_npcm7xx_watch= dog_timer =3D { =20 static const VMStateDescription vmstate_npcm7xx_timer_ctrl =3D { .name =3D "npcm7xx-timer-ctrl", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), + VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_t= imer, NPCM7xxTimer), @@ -697,7 +694,6 @@ static void npcm7xx_timer_class_init(ObjectClass *klass= , void *data) QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); =20 dc->desc =3D "NPCM7xx Timer Controller"; - dc->realize =3D npcm7xx_timer_realize; dc->vmsd =3D &vmstate_npcm7xx_timer_ctrl; rc->phases.enter =3D npcm7xx_timer_enter_reset; rc->phases.hold =3D npcm7xx_timer_hold_reset; @@ -708,6 +704,7 @@ static const TypeInfo npcm7xx_timer_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(NPCM7xxTimerCtrlState), .class_init =3D npcm7xx_timer_class_init, + .instance_init =3D npcm7xx_timer_init, }; =20 static void npcm7xx_timer_register_type(void) --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610471100; cv=none; d=zohomail.com; s=zohoarc; b=PJhydUNBCDxdo19j1DHu1iuXu92eroQST+NkcmWJF638qyQVhJQXnv3UUWCgmCRutfBRb9T9hDPx5/nT0R97oQWVWUWClsVpg+47h+VaFW7l86DclrKnUEcxknIQoXDFi2SYIWCI0EBbKC2FVboW2qjMdowQ1uhaJegH+32B//s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610471100; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4FlNkzNZlb3zZ7vcEpXyK6XdcSGmtuLMsQxAIwbf1ds=; b=nZL6T++6fOQVCW1djGS5F/FTBg+AMr7QulAYJxzFOFUCPDv7PsBbkPIQuFFK7DBOZJHFH+RzN32sUqj9WOrcuLk8njLC72qU4YKypTzR4TC9MSxeEgJE0MPWbz9riPH+waEoLWDgk3/2jOEwzSIZVwujOCaGI86D6SFbNx+AXaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610471100542983.6437425138417; Tue, 12 Jan 2021 09:05:00 -0800 (PST) Received: from localhost ([::1]:43804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzN6J-0007XI-0b for importer@patchew.org; Tue, 12 Jan 2021 12:04:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMzq-0001y7-WD for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:19 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43535) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzMzn-00072q-Dg for qemu-devel@nongnu.org; Tue, 12 Jan 2021 11:58:18 -0500 Received: by mail-wr1-x42e.google.com with SMTP id y17so3217763wrr.10 for ; Tue, 12 Jan 2021 08:58:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4FlNkzNZlb3zZ7vcEpXyK6XdcSGmtuLMsQxAIwbf1ds=; b=XR3Ma+/RLS5mPZSmsO2lJB4I1DtZmAJ54Z2jbr/CUEi5MC09WL/+lv5npqSX/Qo5Rc DLp8fDrDPxQvg1vQ8QQ5IYpOTL0rjak8a6BY820srWwR9DNTYCsbrHVk380qbwxshD7H 7ldEBgU+5kfMHdfIQT81RTsbLSV+3JI2uuAWkyXCefM1KTRrCXB4xLpLEw8Pnga/87YX qvU47owgPQzDtnaUWMv0YHTE92an06IvcVLMQUoZfTa04miaaRfSvPHjW9ZkAxF8v3OV E6sBsyx7hecKl1AoLKFJsWc1K44Vf8R1aTTmMKZfSpETMujY04RekY6/FybQsMz5slv6 hzYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4FlNkzNZlb3zZ7vcEpXyK6XdcSGmtuLMsQxAIwbf1ds=; b=jJN0RVuQDvH6ugbEXS56BuZ44TrDdUSLV5Fk//HPEHlslDT8cCbAwJqHMbD4f4yK7E dPyRemR4xf4x+TnfCsCoe+0DNcmCfo9orw0cfSws6WiWlyTUJpspiz4aghoh78GvjDxU IftKpcpf7jAFZiBcmVgz6x7xWtLWKsIUe/leiLEpFC59qhvugVdVRCULX7OWLBDuJd5k 5Hsfs5613fPNjGgzf547fYgCQHwigXZSwSyuGAZTOCVhNCfeoVs64/9xu9eJSgH1Upzi djUAWIeyg1LMHPAowH44z3Ce3X0oTP26IdTRDB8NgHkZJvoV0oXAnT5S9vLCpUM0T5yp PPnA== X-Gm-Message-State: AOAM532RjeQKHvgyQZeo+Bc08O/87wYQpoz3agQ/HHi9gCCoFuq6QkSW bkulFcQMiARcYerTczx3vpQp8XfTZ19l4g== X-Google-Smtp-Source: ABdhPJyuhf6RPZyvtFvkgjOexTVG946N7AGA2QhOg7+y0WZYczCaPBMHUqB3LiTibPPza0Hhy5q/7A== X-Received: by 2002:a5d:457a:: with SMTP id a26mr2733639wrc.53.1610470693466; Tue, 12 Jan 2021 08:58:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/21] hw/adc: Add an ADC module for NPCM7XX Date: Tue, 12 Jan 2021 16:57:46 +0000 Message-Id: <20210112165750.30475-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu The ADC is part of NPCM7XX Module. Its behavior is controled by the ADC_CON register. It converts one of the eight analog inputs into a digital input and stores it in the ADC_DATA register when enabled. Users can alter input value by using qom-set QMP command. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Message-id: 20210108190945.949196-4-wuhaotsh@google.com [PMM: Added missing hw/adc/trace.h file] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 2 +- meson.build | 1 + hw/adc/trace.h | 1 + include/hw/adc/npcm7xx_adc.h | 69 ++++++ include/hw/arm/npcm7xx.h | 2 + hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++ hw/arm/npcm7xx.c | 24 ++- tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++ hw/adc/meson.build | 1 + hw/adc/trace-events | 5 + tests/qtest/meson.build | 3 +- 11 files changed, 783 insertions(+), 3 deletions(-) create mode 100644 hw/adc/trace.h create mode 100644 include/hw/adc/npcm7xx_adc.h create mode 100644 hw/adc/npcm7xx_adc.c create mode 100644 tests/qtest/npcm7xx_adc-test.c create mode 100644 hw/adc/trace-events diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index b00d405d52e..35829f8d0b6 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -41,6 +41,7 @@ Supported devices * Random Number Generator (RNG) * USB host (USBH) * GPIO controller + * Analog to Digital Converter (ADC) =20 Missing devices --------------- @@ -58,7 +59,6 @@ Missing devices * USB device (USBD) * SMBus controller (SMBF) * Peripheral SPI controller (PSPI) - * Analog to Digital Converter (ADC) * SD/MMC host * PECI interface * Pulse Width Modulation (PWM) diff --git a/meson.build b/meson.build index e4db67ccf2e..0ce993a404b 100644 --- a/meson.build +++ b/meson.build @@ -1687,6 +1687,7 @@ if have_system 'chardev', 'hw/9pfs', 'hw/acpi', + 'hw/adc', 'hw/alpha', 'hw/arm', 'hw/audio', diff --git a/hw/adc/trace.h b/hw/adc/trace.h new file mode 100644 index 00000000000..b71d5b5b4ee --- /dev/null +++ b/hw/adc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_adc.h" diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h new file mode 100644 index 00000000000..7d8442107ae --- /dev/null +++ b/include/hw/adc/npcm7xx_adc.h @@ -0,0 +1,69 @@ +/* + * Nuvoton NPCM7xx ADC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_ADC_H +#define NPCM7XX_ADC_H + +#include "hw/clock.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" + +#define NPCM7XX_ADC_NUM_INPUTS 8 +/** + * This value should not be changed unless write_adc_calibration function = in + * hw/arm/npcm7xx.c is also changed. + */ +#define NPCM7XX_ADC_NUM_CALIB 2 + +/** + * struct NPCM7xxADCState - Analog to Digital Converter Module device stat= e. + * @parent: System bus device. + * @iomem: Memory region through which registers are accessed. + * @conv_timer: The timer counts down remaining cycles for the conversion. + * @irq: GIC interrupt line to fire on expiration (if enabled). + * @con: The Control Register. + * @data: The Data Buffer. + * @clock: The ADC Clock. + * @adci: The input voltage in units of uV. 1uv =3D 1e-6V. + * @vref: The external reference voltage. + * @iref: The internal reference voltage, initialized at launch time. + * @rv: The calibrated output values of 0.5V and 1.5V for the ADC. + */ +typedef struct { + SysBusDevice parent; + + MemoryRegion iomem; + + QEMUTimer conv_timer; + + qemu_irq irq; + uint32_t con; + uint32_t data; + Clock *clock; + + /* Voltages are in unit of uV. 1V =3D 1000000uV. */ + uint32_t adci[NPCM7XX_ADC_NUM_INPUTS]; + uint32_t vref; + uint32_t iref; + + uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB]; +} NPCM7xxADCState; + +#define TYPE_NPCM7XX_ADC "npcm7xx-adc" +#define NPCM7XX_ADC(obj) \ + OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC) + +#endif /* NPCM7XX_ADC_H */ diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 5469247e389..51e1c7620db 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -17,6 +17,7 @@ #define NPCM7XX_H =20 #include "hw/boards.h" +#include "hw/adc/npcm7xx_adc.h" #include "hw/cpu/a9mpcore.h" #include "hw/gpio/npcm7xx_gpio.h" #include "hw/mem/npcm7xx_mc.h" @@ -76,6 +77,7 @@ typedef struct NPCM7xxState { NPCM7xxGCRState gcr; NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; + NPCM7xxADCState adc; NPCM7xxOTPState key_storage; NPCM7xxOTPState fuse_array; NPCM7xxMCState mc; diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c new file mode 100644 index 00000000000..870a6d50c27 --- /dev/null +++ b/hw/adc/npcm7xx_adc.c @@ -0,0 +1,301 @@ +/* + * Nuvoton NPCM7xx ADC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "hw/adc/npcm7xx_adc.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/timer.h" +#include "qemu/units.h" +#include "trace.h" + +REG32(NPCM7XX_ADC_CON, 0x0) +REG32(NPCM7XX_ADC_DATA, 0x4) + +/* Register field definitions. */ +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4) +#define NPCM7XX_ADC_CON_INT_EN BIT(21) +#define NPCM7XX_ADC_CON_REFSEL BIT(19) +#define NPCM7XX_ADC_CON_INT BIT(18) +#define NPCM7XX_ADC_CON_EN BIT(17) +#define NPCM7XX_ADC_CON_RST BIT(16) +#define NPCM7XX_ADC_CON_CONV BIT(14) +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) + +#define NPCM7XX_ADC_MAX_RESULT 1023 +#define NPCM7XX_ADC_DEFAULT_IREF 2000000 +#define NPCM7XX_ADC_CONV_CYCLES 20 +#define NPCM7XX_ADC_RESET_CYCLES 10 +#define NPCM7XX_ADC_R0_INPUT 500000 +#define NPCM7XX_ADC_R1_INPUT 1500000 + +static void npcm7xx_adc_reset(NPCM7xxADCState *s) +{ + timer_del(&s->conv_timer); + s->con =3D 0x000c0001; + s->data =3D 0x00000000; +} + +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref) +{ + uint32_t result; + + result =3D input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref; + if (result > NPCM7XX_ADC_MAX_RESULT) { + result =3D NPCM7XX_ADC_MAX_RESULT; + } + + return result; +} + +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s) +{ + return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1); +} + +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer, + uint32_t cycles, uint32_t prescaler) +{ + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int64_t ticks =3D cycles; + int64_t ns; + + ticks *=3D prescaler; + ns =3D clock_ticks_to_ns(clk, ticks); + ns +=3D now; + timer_mod(timer, ns); +} + +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s) +{ + uint32_t prescaler =3D npcm7xx_adc_prescaler(s); + + npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYC= LES, + prescaler); +} + +static void npcm7xx_adc_convert_done(void *opaque) +{ + NPCM7xxADCState *s =3D opaque; + uint32_t input =3D NPCM7XX_ADC_CON_MUX(s->con); + uint32_t ref =3D (s->con & NPCM7XX_ADC_CON_REFSEL) + ? s->iref : s->vref; + + if (input >=3D NPCM7XX_ADC_NUM_INPUTS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n", + __func__, input); + return; + } + s->data =3D npcm7xx_adc_convert(s->adci[input], ref); + if (s->con & NPCM7XX_ADC_CON_INT_EN) { + s->con |=3D NPCM7XX_ADC_CON_INT; + qemu_irq_raise(s->irq); + } + s->con &=3D ~NPCM7XX_ADC_CON_CONV; +} + +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc) +{ + adc->calibration_r_values[0] =3D npcm7xx_adc_convert(NPCM7XX_ADC_R0_IN= PUT, + adc->iref); + adc->calibration_r_values[1] =3D npcm7xx_adc_convert(NPCM7XX_ADC_R1_IN= PUT, + adc->iref); +} + +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con) +{ + uint32_t old_con =3D s->con; + + /* Write ADC_INT to 1 to clear it */ + if (new_con & NPCM7XX_ADC_CON_INT) { + new_con &=3D ~NPCM7XX_ADC_CON_INT; + qemu_irq_lower(s->irq); + } else if (old_con & NPCM7XX_ADC_CON_INT) { + new_con |=3D NPCM7XX_ADC_CON_INT; + } + + s->con =3D new_con; + + if (s->con & NPCM7XX_ADC_CON_RST) { + npcm7xx_adc_reset(s); + return; + } + + if ((s->con & NPCM7XX_ADC_CON_EN)) { + if (s->con & NPCM7XX_ADC_CON_CONV) { + if (!(old_con & NPCM7XX_ADC_CON_CONV)) { + npcm7xx_adc_start_convert(s); + } + } else { + timer_del(&s->conv_timer); + } + } +} + +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + uint64_t value =3D 0; + NPCM7xxADCState *s =3D opaque; + + switch (offset) { + case A_NPCM7XX_ADC_CON: + value =3D s->con; + break; + + case A_NPCM7XX_ADC_DATA: + value =3D s->data; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } + + trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value); + return value; +} + +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v, + unsigned size) +{ + NPCM7xxADCState *s =3D opaque; + + trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v); + switch (offset) { + case A_NPCM7XX_ADC_CON: + npcm7xx_adc_write_con(s, v); + break; + + case A_NPCM7XX_ADC_DATA: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", + __func__, offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } + +} + +static const struct MemoryRegionOps npcm7xx_adc_ops =3D { + .read =3D npcm7xx_adc_read, + .write =3D npcm7xx_adc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxADCState *s =3D NPCM7XX_ADC(obj); + + npcm7xx_adc_reset(s); +} + +static void npcm7xx_adc_hold_reset(Object *obj) +{ + NPCM7xxADCState *s =3D NPCM7XX_ADC(obj); + + qemu_irq_lower(s->irq); +} + +static void npcm7xx_adc_init(Object *obj) +{ + NPCM7xxADCState *s =3D NPCM7XX_ADC(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int i; + + sysbus_init_irq(sbd, &s->irq); + + timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL, + npcm7xx_adc_convert_done, s); + memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s, + TYPE_NPCM7XX_ADC, 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + + for (i =3D 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { + object_property_add_uint32_ptr(obj, "adci[*]", + &s->adci[i], OBJ_PROP_FLAG_WRITE); + } + object_property_add_uint32_ptr(obj, "vref", + &s->vref, OBJ_PROP_FLAG_WRITE); + npcm7xx_adc_calibrate(s); +} + +static const VMStateDescription vmstate_npcm7xx_adc =3D { + .name =3D "npcm7xx-adc", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_TIMER(conv_timer, NPCM7xxADCState), + VMSTATE_UINT32(con, NPCM7xxADCState), + VMSTATE_UINT32(data, NPCM7xxADCState), + VMSTATE_CLOCK(clock, NPCM7xxADCState), + VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS= ), + VMSTATE_UINT32(vref, NPCM7xxADCState), + VMSTATE_UINT32(iref, NPCM7xxADCState), + VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState, + NPCM7XX_ADC_NUM_CALIB), + VMSTATE_END_OF_LIST(), + }, +}; + +static Property npcm7xx_timer_properties[] =3D { + DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_= IREF), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM7xx ADC Module"; + dc->vmsd =3D &vmstate_npcm7xx_adc; + rc->phases.enter =3D npcm7xx_adc_enter_reset; + rc->phases.hold =3D npcm7xx_adc_hold_reset; + + device_class_set_props(dc, npcm7xx_timer_properties); +} + +static const TypeInfo npcm7xx_adc_info =3D { + .name =3D TYPE_NPCM7XX_ADC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCM7xxADCState), + .class_init =3D npcm7xx_adc_class_init, + .instance_init =3D npcm7xx_adc_init, +}; + +static void npcm7xx_adc_register_types(void) +{ + type_register_static(&npcm7xx_adc_info); +} + +type_init(npcm7xx_adc_register_types); diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index fabfb1697ba..b22a8c966d3 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -51,6 +51,9 @@ #define NPCM7XX_EHCI_BA (0xf0806000) #define NPCM7XX_OHCI_BA (0xf0807000) =20 +/* ADC Module */ +#define NPCM7XX_ADC_BA (0xf000c000) + /* Internal AHB SRAM */ #define NPCM7XX_RAM3_BA (0xc0008000) #define NPCM7XX_RAM3_SZ (4 * KiB) @@ -61,6 +64,7 @@ #define NPCM7XX_ROM_BA (0xffff0000) #define NPCM7XX_ROM_SZ (64 * KiB) =20 + /* Clock configuration values to be fixed up when bypassing bootloader */ =20 /* Run PLL1 at 1600 MHz */ @@ -73,6 +77,7 @@ * interrupts. */ enum NPCM7xxInterrupt { + NPCM7XX_ADC_IRQ =3D 0, NPCM7XX_UART0_IRQ =3D 2, NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, @@ -296,6 +301,14 @@ static void npcm7xx_init_fuses(NPCM7xxState *s) sizeof(value)); } =20 +static void npcm7xx_write_adc_calibration(NPCM7xxState *s) +{ + /* Both ADC and the fuse array must have realized. */ + QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) !=3D 4); + npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, + NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); +} + static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) { return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); @@ -322,6 +335,7 @@ static void npcm7xx_init(Object *obj) TYPE_NPCM7XX_FUSE_ARRAY); object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); + object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); =20 for (i =3D 0; i < ARRAY_SIZE(s->tim); i++) { object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TI= MER); @@ -414,6 +428,15 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); =20 + /* ADC Modules. Cannot fail. */ + qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( + DEVICE(&s->clk), "adc-clock")); + sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, + npcm7xx_irq(s, NPCM7XX_ADC_IRQ)); + npcm7xx_write_adc_calibration(s); + /* Timer Modules (TIM). Cannot fail. */ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) !=3D ARRAY_SIZE(s->tim)= ); for (i =3D 0; i < ARRAY_SIZE(s->tim); i++) { @@ -528,7 +551,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * = KiB); create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * = KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * = KiB); - create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * = KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * = KiB); create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * = KiB); create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * = KiB); diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c new file mode 100644 index 00000000000..f0297069459 --- /dev/null +++ b/tests/qtest/npcm7xx_adc-test.c @@ -0,0 +1,377 @@ +/* + * QTests for Nuvoton NPCM7xx ADCModules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/timer.h" +#include "libqos/libqtest.h" +#include "qapi/qmp/qdict.h" + +#define REF_HZ (25000000) + +#define CON_OFFSET 0x0 +#define DATA_OFFSET 0x4 + +#define NUM_INPUTS 8 +#define DEFAULT_IREF 2000000 +#define CONV_CYCLES 20 +#define RESET_CYCLES 10 +#define R0_INPUT 500000 +#define R1_INPUT 1500000 +#define MAX_RESULT 1023 + +#define DEFAULT_CLKDIV 5 + +#define FUSE_ARRAY_BA 0xf018a000 +#define FCTL_OFFSET 0x14 +#define FST_OFFSET 0x0 +#define FADDR_OFFSET 0x4 +#define FDATA_OFFSET 0x8 +#define ADC_CALIB_ADDR 24 +#define FUSE_READ 0x2 + +/* Register field definitions. */ +#define CON_MUX(rv) ((rv) << 24) +#define CON_INT_EN BIT(21) +#define CON_REFSEL BIT(19) +#define CON_INT BIT(18) +#define CON_EN BIT(17) +#define CON_RST BIT(16) +#define CON_CONV BIT(14) +#define CON_DIV(rv) extract32(rv, 1, 8) + +#define FST_RDST BIT(1) +#define FDATA_MASK 0xff + +#define MAX_ERROR 10000 +#define MIN_CALIB_INPUT 100000 +#define MAX_CALIB_INPUT 1800000 + +static const uint32_t input_list[] =3D { + 100000, + 500000, + 1000000, + 1500000, + 1800000, + 2000000, +}; + +static const uint32_t vref_list[] =3D { + 2000000, + 2200000, + 2500000, +}; + +static const uint32_t iref_list[] =3D { + 1800000, + 1900000, + 2000000, + 2100000, + 2200000, +}; + +static const uint32_t div_list[] =3D {0, 1, 3, 7, 15}; + +typedef struct ADC { + int irq; + uint64_t base_addr; +} ADC; + +ADC adc =3D { + .irq =3D 0, + .base_addr =3D 0xf000c000 +}; + +static uint32_t adc_read_con(QTestState *qts, const ADC *adc) +{ + return qtest_readl(qts, adc->base_addr + CON_OFFSET); +} + +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) +{ + qtest_writel(qts, adc->base_addr + CON_OFFSET, value); +} + +static uint32_t adc_read_data(QTestState *qts, const ADC *adc) +{ + return qtest_readl(qts, adc->base_addr + DATA_OFFSET); +} + +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv) +{ + return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0]) + / (int32_t)(rv[1] - rv[0]); +} + +static void adc_qom_set(QTestState *qts, const ADC *adc, + const char *name, uint32_t value) +{ + QDict *response; + const char *path =3D "/machine/soc/adc"; + + g_test_message("Setting properties %s of %s with value %u", + name, path, value); + response =3D qtest_qmp(qts, "{ 'execute': 'qom-set'," + " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}", + path, name, value); + /* The qom set message returns successfully. */ + g_assert_true(qdict_haskey(response, "return")); +} + +static void adc_write_input(QTestState *qts, const ADC *adc, + uint32_t index, uint32_t value) +{ + char name[100]; + + sprintf(name, "adci[%u]", index); + adc_qom_set(qts, adc, name, value); +} + +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value) +{ + adc_qom_set(qts, adc, "vref", value); +} + +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref) +{ + uint32_t output; + + g_assert_cmpuint(input, <=3D, ref); + output =3D (input * (MAX_RESULT + 1)) / ref; + if (output > MAX_RESULT) { + output =3D MAX_RESULT; + } + + return output; +} + +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc) +{ + uint32_t div =3D extract32(adc_read_con(qts, adc), 1, 8); + + return 2 * (div + 1); +} + +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale, + uint32_t clkdiv) +{ + return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * presca= le; +} + +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc, + uint32_t clkdiv) +{ + uint32_t prescaler =3D adc_prescaler(qts, adc); + + /* + * ADC should takes roughly 20 cycles to convert one sample. So we ass= ert it + * should take 10~30 cycles here. + */ + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler, + clkdiv)); + /* ADC is still converting. */ + g_assert_true(adc_read_con(qts, adc) & CON_CONV); + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkd= iv)); + /* ADC has finished conversion. */ + g_assert_false(adc_read_con(qts, adc) & CON_CONV); +} + +/* Check ADC can be reset to default value. */ +static void test_init(gconstpointer adc_p) +{ + const ADC *adc =3D adc_p; + + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + adc_write_con(qts, adc, CON_REFSEL | CON_INT); + g_assert_cmphex(adc_read_con(qts, adc), =3D=3D, CON_REFSEL); + qtest_quit(qts); +} + +/* Check ADC can convert from an internal reference. */ +static void test_convert_internal(gconstpointer adc_p) +{ + const ADC *adc =3D adc_p; + uint32_t index, input, output, expected_output; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + for (index =3D 0; index < NUM_INPUTS; ++index) { + for (size_t i =3D 0; i < ARRAY_SIZE(input_list); ++i) { + input =3D input_list[i]; + expected_output =3D adc_calculate_output(input, DEFAULT_IREF); + + adc_write_input(qts, adc, index, input); + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | + CON_EN | CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), =3D=3D, CON_MUX(index)= | + CON_REFSEL | CON_EN); + g_assert_false(qtest_get_irq(qts, adc->irq)); + output =3D adc_read_data(qts, adc); + g_assert_cmpuint(output, =3D=3D, expected_output); + } + } + + qtest_quit(qts); +} + +/* Check ADC can convert from an external reference. */ +static void test_convert_external(gconstpointer adc_p) +{ + const ADC *adc =3D adc_p; + uint32_t index, input, vref, output, expected_output; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + for (index =3D 0; index < NUM_INPUTS; ++index) { + for (size_t i =3D 0; i < ARRAY_SIZE(input_list); ++i) { + for (size_t j =3D 0; j < ARRAY_SIZE(vref_list); ++j) { + input =3D input_list[i]; + vref =3D vref_list[j]; + expected_output =3D adc_calculate_output(input, vref); + + adc_write_input(qts, adc, index, input); + adc_write_vref(qts, adc, vref); + adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN | + CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), =3D=3D, + CON_MUX(index) | CON_EN); + g_assert_false(qtest_get_irq(qts, adc->irq)); + output =3D adc_read_data(qts, adc); + g_assert_cmpuint(output, =3D=3D, expected_output); + } + } + } + + qtest_quit(qts); +} + +/* Check ADC interrupt files if and only if CON_INT_EN is set. */ +static void test_interrupt(gconstpointer adc_p) +{ + const ADC *adc =3D adc_p; + uint32_t index, input, output, expected_output; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + + index =3D 1; + input =3D input_list[1]; + expected_output =3D adc_calculate_output(input, DEFAULT_IREF); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + adc_write_input(qts, adc, index, input); + g_assert_false(qtest_get_irq(qts, adc->irq)); + adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON= _INT + | CON_EN | CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), =3D=3D, CON_MUX(index) | CON_I= NT_EN + | CON_REFSEL | CON_INT | CON_EN); + g_assert_true(qtest_get_irq(qts, adc->irq)); + output =3D adc_read_data(qts, adc); + g_assert_cmpuint(output, =3D=3D, expected_output); + + qtest_quit(qts); +} + +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */ +static void test_reset(gconstpointer adc_p) +{ + const ADC *adc =3D adc_p; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + + for (size_t i =3D 0; i < ARRAY_SIZE(div_list); ++i) { + uint32_t div =3D div_list[i]; + + adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div)); + qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES, + adc_prescaler(qts, adc), DEFAULT_CLKDIV)); + g_assert_false(adc_read_con(qts, adc) & CON_EN); + } + qtest_quit(qts); +} + +/* Check ADC Calibration works as desired. */ +static void test_calibrate(gconstpointer adc_p) +{ + int i, j; + const ADC *adc =3D adc_p; + + for (j =3D 0; j < ARRAY_SIZE(iref_list); ++j) { + uint32_t iref =3D iref_list[j]; + uint32_t expected_rv[] =3D { + adc_calculate_output(R0_INPUT, iref), + adc_calculate_output(R1_INPUT, iref), + }; + char buf[100]; + QTestState *qts; + + sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=3D%u", = iref); + qts =3D qtest_init(buf); + + /* Check the converted value is correct using the calibration valu= e. */ + for (i =3D 0; i < ARRAY_SIZE(input_list); ++i) { + uint32_t input; + uint32_t output; + uint32_t expected_output; + uint32_t calibrated_voltage; + uint32_t index =3D 0; + + input =3D input_list[i]; + /* Calibration only works for input range 0.1V ~ 1.8V. */ + if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) { + continue; + } + expected_output =3D adc_calculate_output(input, iref); + + adc_write_input(qts, adc, index, input); + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | + CON_EN | CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), =3D=3D, + CON_REFSEL | CON_MUX(index) | CON_EN); + output =3D adc_read_data(qts, adc); + g_assert_cmpuint(output, =3D=3D, expected_output); + + calibrated_voltage =3D adc_calibrate(output, expected_rv); + g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR); + g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR); + } + + qtest_quit(qts); + } +} + +static void adc_add_test(const char *name, const ADC* wd, + GTestDataFunc fn) +{ + g_autofree char *full_name =3D g_strdup_printf("npcm7xx_adc/%s", name= ); + qtest_add_data_func(full_name, wd, fn); +} +#define add_test(name, td) adc_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + add_test(init, &adc); + add_test(convert_internal, &adc); + add_test(convert_external, &adc); + add_test(interrupt, &adc); + add_test(reset, &adc); + add_test(calibrate, &adc); + + return g_test_run(); +} diff --git a/hw/adc/meson.build b/hw/adc/meson.build index 0d62ae96ae9..6ddee238139 100644 --- a/hw/adc/meson.build +++ b/hw/adc/meson.build @@ -1 +1,2 @@ softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc= .c')) +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) diff --git a/hw/adc/trace-events b/hw/adc/trace-events new file mode 100644 index 00000000000..4c3279ece2c --- /dev/null +++ b/hw/adc/trace-events @@ -0,0 +1,5 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# npcm7xx_adc.c +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s off= set: 0x%04" PRIx64 " value 0x%04" PRIx32 +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s off= set: 0x%04" PRIx64 " value 0x%04" PRIx32 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 6a67c538be1..955710d1c5d 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -134,7 +134,8 @@ qtests_sparc64 =3D \ ['prom-env-test', 'boot-serial-test'] =20 qtests_npcm7xx =3D \ - ['npcm7xx_gpio-test', + ['npcm7xx_adc-test', + 'npcm7xx_gpio-test', 'npcm7xx_rng-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wR5z/kJnao51NPzZP9QnfcBQ068D1JOXzILEW7CUv2o=; b=Z4zEEUeuRP1pPm58x9HFpsiE5iObmu/So5qqo5TG0imwxim/7LgiP7zGPhAlq18f2K ywnMKE1ndjHeJgYZlWm/XaB5wi9o5wMplI7rN3Bd7syYqi7kwjF1gH434nf0uD0ewh7K f/Qyd/H0XIK60tARbma2KiGUY+Azir2t7RN94Uw3XEs6CBxzdA4c6xupHoop9Hl6j97e 9U9af8c0bRoUW4V83M8u+fbMtGV5agRwQBY5//ziBPVtiSrOI5Kb82njcgEFA0gsiyYh BCJdODfjb0xYfP+d69ppF0zObJI4mn6YoX6QIqEQgZoeZ0w7eFBhJ4Um6i0/sJUFL+fs jtRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wR5z/kJnao51NPzZP9QnfcBQ068D1JOXzILEW7CUv2o=; b=Or+GT/luMlNFuTMCbbvezZo2jqe7P47qnoaJifXY1o/nzcewKpLe4aG7jo0dLJrw8J 1R3YJcX8cXC0/8SZx1L35lD5suhEQExnYSYDFyNx4U6obRfb4gfy0ckXg3756ocexee3 BV2C0/wePWqr1Frr29Inf1U6z19FPjHyXqK7JQEGyO/YIQqv0M76ZIQGXPb5ejGUyV6V fkbbXaXtn0q4TkKrKLx4FJ6RrPUSKosfooQbBZS+qr+ffIHZf9xwcZMLg1IogcGsXBGa pL1mjK7ZZzCEFFimFYv2No98T+igDqHvLqSYgUBaNli/vkTaH4WhUafOnvb1Cu/TH8nz C2sw== X-Gm-Message-State: AOAM5324rQSW1FGCnVpQPrS+/PAQNK3I5FygQd0roIqleb71UYSr7HyO eilNTFxRMPKK4LH6eVFtLG3fE0f1+G4EXQ== X-Google-Smtp-Source: ABdhPJzU6PkxbE2J4dSZ1ollSTCCkepnbh96HPXt4pPI4Jc32TRlwdmtgqx4m8gInud3E+vFp8o5Tw== X-Received: by 2002:adf:ec92:: with SMTP id z18mr5396008wrn.166.1610470694907; Tue, 12 Jan 2021 08:58:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/21] hw/misc: Add a PWM module for NPCM7XX Date: Tue, 12 Jan 2021 16:57:47 +0000 Message-Id: <20210112165750.30475-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu The PWM module is part of NPCM7XX module. Each NPCM7XX module has two identical PWM modules. Each module contains 4 PWM entries. Each PWM has two outputs: frequency and duty_cycle. Both are computed using inputs from software side. This module does not model detail pulse signals since it is expensive. It also does not model interrupts and watchdogs that are dependant on the detail models. The interfaces for these are left in the module so that anyone in need for these functionalities can implement on their own. The user can read the duty cycle and frequency using qom-get command. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Message-id: 20210108190945.949196-5-wuhaotsh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 2 +- include/hw/arm/npcm7xx.h | 2 + include/hw/misc/npcm7xx_pwm.h | 105 +++++++ hw/arm/npcm7xx.c | 26 +- hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 6 + 7 files changed, 689 insertions(+), 3 deletions(-) create mode 100644 include/hw/misc/npcm7xx_pwm.h create mode 100644 hw/misc/npcm7xx_pwm.c diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 35829f8d0b6..a1786342e21 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -42,6 +42,7 @@ Supported devices * USB host (USBH) * GPIO controller * Analog to Digital Converter (ADC) + * Pulse Width Modulation (PWM) =20 Missing devices --------------- @@ -61,7 +62,6 @@ Missing devices * Peripheral SPI controller (PSPI) * SD/MMC host * PECI interface - * Pulse Width Modulation (PWM) * Tachometer * PCI and PCIe root complex and bridges * VDM and MCTP support diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 51e1c7620db..f6227aa8aa8 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -23,6 +23,7 @@ #include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" +#include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" @@ -78,6 +79,7 @@ typedef struct NPCM7xxState { NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; NPCM7xxADCState adc; + NPCM7xxPWMState pwm[2]; NPCM7xxOTPState key_storage; NPCM7xxOTPState fuse_array; NPCM7xxMCState mc; diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h new file mode 100644 index 00000000000..5a689d3f669 --- /dev/null +++ b/include/hw/misc/npcm7xx_pwm.h @@ -0,0 +1,105 @@ +/* + * Nuvoton NPCM7xx PWM Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_PWM_H +#define NPCM7XX_PWM_H + +#include "hw/clock.h" +#include "hw/sysbus.h" +#include "hw/irq.h" + +/* Each PWM module holds 4 PWM channels. */ +#define NPCM7XX_PWM_PER_MODULE 4 + +/* + * Number of registers in one pwm module. Don't change this without increa= sing + * the version_id in vmstate. + */ +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t)) + +/* + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DU= TY + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=3D1,000,000 and a PWM has = a duty + * value of 100,000 the duty cycle for that PWM is 10%. + */ +#define NPCM7XX_PWM_MAX_DUTY 1000000 + +typedef struct NPCM7xxPWMState NPCM7xxPWMState; + +/** + * struct NPCM7xxPWM - The state of a single PWM channel. + * @module: The PWM module that contains this channel. + * @irq: GIC interrupt line to fire on expiration if enabled. + * @running: Whether this PWM channel is generating output. + * @inverted: Whether this PWM channel is inverted. + * @index: The index of this PWM channel. + * @cnr: The counter register. + * @cmr: The comparator register. + * @pdr: The data register. + * @pwdr: The watchdog register. + * @freq: The frequency of this PWM channel. + * @duty: The duty cycle of this PWM channel. One unit represents + * 1/NPCM7XX_MAX_DUTY cycles. + */ +typedef struct NPCM7xxPWM { + NPCM7xxPWMState *module; + + qemu_irq irq; + + bool running; + bool inverted; + + uint8_t index; + uint32_t cnr; + uint32_t cmr; + uint32_t pdr; + uint32_t pwdr; + + uint32_t freq; + uint32_t duty; +} NPCM7xxPWM; + +/** + * struct NPCM7xxPWMState - Pulse Width Modulation device state. + * @parent: System bus device. + * @iomem: Memory region through which registers are accessed. + * @clock: The PWM clock. + * @pwm: The PWM channels owned by this module. + * @ppr: The prescaler register. + * @csr: The clock selector register. + * @pcr: The control register. + * @pier: The interrupt enable register. + * @piir: The interrupt indication register. + */ +struct NPCM7xxPWMState { + SysBusDevice parent; + + MemoryRegion iomem; + + Clock *clock; + NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE]; + + uint32_t ppr; + uint32_t csr; + uint32_t pcr; + uint32_t pier; + uint32_t piir; +}; + +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm" +#define NPCM7XX_PWM(obj) \ + OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM) + +#endif /* NPCM7XX_PWM_H */ diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index b22a8c966d3..72040d40799 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -102,6 +102,8 @@ enum NPCM7xxInterrupt { NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ NPCM7XX_EHCI_IRQ =3D 61, NPCM7XX_OHCI_IRQ =3D 62, + NPCM7XX_PWM0_IRQ =3D 93, /* PWM module 0 */ + NPCM7XX_PWM1_IRQ, /* PWM module 1 */ NPCM7XX_GPIO0_IRQ =3D 116, NPCM7XX_GPIO1_IRQ, NPCM7XX_GPIO2_IRQ, @@ -144,6 +146,12 @@ static const hwaddr npcm7xx_fiu3_flash_addr[] =3D { 0xb8000000, /* CS3 */ }; =20 +/* Register base address for each PWM Module */ +static const hwaddr npcm7xx_pwm_addr[] =3D { + 0xf0103000, + 0xf0104000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -353,6 +361,10 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], TYPE_NPCM7XX_FIU); } + + for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { + object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PW= M); + } } =20 static void npcm7xx_realize(DeviceState *dev, Error **errp) @@ -513,6 +525,18 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); =20 + /* PWM Modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) !=3D ARRAY_SIZE(s->pwm)= ); + for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->pwm[i]); + + qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_= out( + DEVICE(&s->clk), "apb3-clock")); + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); + sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip se= lects * specified, but this is a programming error. @@ -580,8 +604,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * = KiB); create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * = KiB); create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * = KiB); - create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * = KiB); - create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * = KiB); create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * = KiB); create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * = KiB); create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * = KiB); diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c new file mode 100644 index 00000000000..e99e3cc7ef3 --- /dev/null +++ b/hw/misc/npcm7xx_pwm.c @@ -0,0 +1,550 @@ +/* + * Nuvoton NPCM7xx PWM Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/misc/npcm7xx_pwm.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "trace.h" + +REG32(NPCM7XX_PWM_PPR, 0x00); +REG32(NPCM7XX_PWM_CSR, 0x04); +REG32(NPCM7XX_PWM_PCR, 0x08); +REG32(NPCM7XX_PWM_CNR0, 0x0c); +REG32(NPCM7XX_PWM_CMR0, 0x10); +REG32(NPCM7XX_PWM_PDR0, 0x14); +REG32(NPCM7XX_PWM_CNR1, 0x18); +REG32(NPCM7XX_PWM_CMR1, 0x1c); +REG32(NPCM7XX_PWM_PDR1, 0x20); +REG32(NPCM7XX_PWM_CNR2, 0x24); +REG32(NPCM7XX_PWM_CMR2, 0x28); +REG32(NPCM7XX_PWM_PDR2, 0x2c); +REG32(NPCM7XX_PWM_CNR3, 0x30); +REG32(NPCM7XX_PWM_CMR3, 0x34); +REG32(NPCM7XX_PWM_PDR3, 0x38); +REG32(NPCM7XX_PWM_PIER, 0x3c); +REG32(NPCM7XX_PWM_PIIR, 0x40); +REG32(NPCM7XX_PWM_PWDR0, 0x44); +REG32(NPCM7XX_PWM_PWDR1, 0x48); +REG32(NPCM7XX_PWM_PWDR2, 0x4c); +REG32(NPCM7XX_PWM_PWDR3, 0x50); + +/* Register field definitions. */ +#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index= ], 8) +#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index= ], 3) +#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index]= , 4) +#define NPCM7XX_CH_EN BIT(0) +#define NPCM7XX_CH_INV BIT(2) +#define NPCM7XX_CH_MOD BIT(3) + +/* Offset of each PWM channel's prescaler in the PPR register. */ +static const int npcm7xx_ppr_base[] =3D { 0, 0, 8, 8 }; +/* Offset of each PWM channel's clock selector in the CSR register. */ +static const int npcm7xx_csr_base[] =3D { 0, 4, 8, 12 }; +/* Offset of each PWM channel's control variable in the PCR register. */ +static const int npcm7xx_ch_base[] =3D { 0, 8, 12, 16 }; + +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p) +{ + uint32_t ppr; + uint32_t csr; + uint32_t freq; + + if (!p->running) { + return 0; + } + + csr =3D NPCM7XX_CSR(p->module->csr, p->index); + ppr =3D NPCM7XX_PPR(p->module->ppr, p->index); + freq =3D clock_get_hz(p->module->clock); + freq /=3D ppr + 1; + /* csr can only be 0~4 */ + if (csr > 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid csr value %u\n", + __func__, csr); + csr =3D 4; + } + /* freq won't be changed if csr =3D=3D 4. */ + if (csr < 4) { + freq >>=3D csr + 1; + } + + return freq / (p->cnr + 1); +} + +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) +{ + uint64_t duty; + + if (p->running) { + if (p->cnr =3D=3D 0) { + duty =3D 0; + } else if (p->cmr >=3D p->cnr) { + duty =3D NPCM7XX_PWM_MAX_DUTY; + } else { + duty =3D NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); + } + } else { + duty =3D 0; + } + + if (p->inverted) { + duty =3D NPCM7XX_PWM_MAX_DUTY - duty; + } + + return duty; +} + +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p) +{ + uint32_t freq =3D npcm7xx_pwm_calculate_freq(p); + + if (freq !=3D p->freq) { + trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path, + p->index, p->freq, freq); + p->freq =3D freq; + } +} + +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p) +{ + uint32_t duty =3D npcm7xx_pwm_calculate_duty(p); + + if (duty !=3D p->duty) { + trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path, + p->index, p->duty, duty); + p->duty =3D duty; + } +} + +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p) +{ + npcm7xx_pwm_update_freq(p); + npcm7xx_pwm_update_duty(p); +} + +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr) +{ + int i; + uint32_t old_ppr =3D s->ppr; + + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) !=3D NPCM7XX_PWM_PER_MO= DULE); + s->ppr =3D new_ppr; + for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + if (NPCM7XX_PPR(old_ppr, i) !=3D NPCM7XX_PPR(new_ppr, i)) { + npcm7xx_pwm_update_freq(&s->pwm[i]); + } + } +} + +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr) +{ + int i; + uint32_t old_csr =3D s->csr; + + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) !=3D NPCM7XX_PWM_PER_MO= DULE); + s->csr =3D new_csr; + for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + if (NPCM7XX_CSR(old_csr, i) !=3D NPCM7XX_CSR(new_csr, i)) { + npcm7xx_pwm_update_freq(&s->pwm[i]); + } + } +} + +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr) +{ + int i; + bool inverted; + uint32_t pcr; + NPCM7xxPWM *p; + + s->pcr =3D new_pcr; + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) !=3D NPCM7XX_PWM_PER_MOD= ULE); + for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + p =3D &s->pwm[i]; + pcr =3D NPCM7XX_CH(new_pcr, i); + inverted =3D pcr & NPCM7XX_CH_INV; + + /* + * We only run a PWM channel with toggle mode. Single-shot mode do= es not + * generate frequency and duty-cycle values. + */ + if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) { + if (p->running) { + /* Re-run this PWM channel if inverted changed. */ + if (p->inverted ^ inverted) { + p->inverted =3D inverted; + npcm7xx_pwm_update_duty(p); + } + } else { + /* Run this PWM channel. */ + p->running =3D true; + p->inverted =3D inverted; + npcm7xx_pwm_update_output(p); + } + } else { + /* Clear this PWM channel. */ + p->running =3D false; + p->inverted =3D inverted; + npcm7xx_pwm_update_output(p); + } + } + +} + +static hwaddr npcm7xx_cnr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_CNR0: + return 0; + case A_NPCM7XX_PWM_CNR1: + return 1; + case A_NPCM7XX_PWM_CNR2: + return 2; + case A_NPCM7XX_PWM_CNR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static hwaddr npcm7xx_cmr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_CMR0: + return 0; + case A_NPCM7XX_PWM_CMR1: + return 1; + case A_NPCM7XX_PWM_CMR2: + return 2; + case A_NPCM7XX_PWM_CMR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static hwaddr npcm7xx_pdr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_PDR0: + return 0; + case A_NPCM7XX_PWM_PDR1: + return 1; + case A_NPCM7XX_PWM_PDR2: + return 2; + case A_NPCM7XX_PWM_PDR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static hwaddr npcm7xx_pwdr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_PWDR0: + return 0; + case A_NPCM7XX_PWM_PWDR1: + return 1; + case A_NPCM7XX_PWM_PWDR2: + return 2; + case A_NPCM7XX_PWM_PWDR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + NPCM7xxPWMState *s =3D opaque; + uint64_t value =3D 0; + + switch (offset) { + case A_NPCM7XX_PWM_CNR0: + case A_NPCM7XX_PWM_CNR1: + case A_NPCM7XX_PWM_CNR2: + case A_NPCM7XX_PWM_CNR3: + value =3D s->pwm[npcm7xx_cnr_index(offset)].cnr; + break; + + case A_NPCM7XX_PWM_CMR0: + case A_NPCM7XX_PWM_CMR1: + case A_NPCM7XX_PWM_CMR2: + case A_NPCM7XX_PWM_CMR3: + value =3D s->pwm[npcm7xx_cmr_index(offset)].cmr; + break; + + case A_NPCM7XX_PWM_PDR0: + case A_NPCM7XX_PWM_PDR1: + case A_NPCM7XX_PWM_PDR2: + case A_NPCM7XX_PWM_PDR3: + value =3D s->pwm[npcm7xx_pdr_index(offset)].pdr; + break; + + case A_NPCM7XX_PWM_PWDR0: + case A_NPCM7XX_PWM_PWDR1: + case A_NPCM7XX_PWM_PWDR2: + case A_NPCM7XX_PWM_PWDR3: + value =3D s->pwm[npcm7xx_pwdr_index(offset)].pwdr; + break; + + case A_NPCM7XX_PWM_PPR: + value =3D s->ppr; + break; + + case A_NPCM7XX_PWM_CSR: + value =3D s->csr; + break; + + case A_NPCM7XX_PWM_PCR: + value =3D s->pcr; + break; + + case A_NPCM7XX_PWM_PIER: + value =3D s->pier; + break; + + case A_NPCM7XX_PWM_PIIR: + value =3D s->piir; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } + + trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value); + return value; +} + +static void npcm7xx_pwm_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCM7xxPWMState *s =3D opaque; + NPCM7xxPWM *p; + uint32_t value =3D v; + + trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value); + switch (offset) { + case A_NPCM7XX_PWM_CNR0: + case A_NPCM7XX_PWM_CNR1: + case A_NPCM7XX_PWM_CNR2: + case A_NPCM7XX_PWM_CNR3: + p =3D &s->pwm[npcm7xx_cnr_index(offset)]; + p->cnr =3D value; + npcm7xx_pwm_update_output(p); + break; + + case A_NPCM7XX_PWM_CMR0: + case A_NPCM7XX_PWM_CMR1: + case A_NPCM7XX_PWM_CMR2: + case A_NPCM7XX_PWM_CMR3: + p =3D &s->pwm[npcm7xx_cmr_index(offset)]; + p->cmr =3D value; + npcm7xx_pwm_update_output(p); + break; + + case A_NPCM7XX_PWM_PDR0: + case A_NPCM7XX_PWM_PDR1: + case A_NPCM7XX_PWM_PDR2: + case A_NPCM7XX_PWM_PDR3: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", + __func__, offset); + break; + + case A_NPCM7XX_PWM_PWDR0: + case A_NPCM7XX_PWM_PWDR1: + case A_NPCM7XX_PWM_PWDR2: + case A_NPCM7XX_PWM_PWDR3: + qemu_log_mask(LOG_UNIMP, + "%s: register @ 0x%04" HWADDR_PRIx " is not implement= ed\n", + __func__, offset); + break; + + case A_NPCM7XX_PWM_PPR: + npcm7xx_pwm_write_ppr(s, value); + break; + + case A_NPCM7XX_PWM_CSR: + npcm7xx_pwm_write_csr(s, value); + break; + + case A_NPCM7XX_PWM_PCR: + npcm7xx_pwm_write_pcr(s, value); + break; + + case A_NPCM7XX_PWM_PIER: + qemu_log_mask(LOG_UNIMP, + "%s: register @ 0x%04" HWADDR_PRIx " is not implement= ed\n", + __func__, offset); + break; + + case A_NPCM7XX_PWM_PIIR: + qemu_log_mask(LOG_UNIMP, + "%s: register @ 0x%04" HWADDR_PRIx " is not implement= ed\n", + __func__, offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } +} + +static const struct MemoryRegionOps npcm7xx_pwm_ops =3D { + .read =3D npcm7xx_pwm_read, + .write =3D npcm7xx_pwm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxPWMState *s =3D NPCM7XX_PWM(obj); + int i; + + for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; i++) { + NPCM7xxPWM *p =3D &s->pwm[i]; + + p->cnr =3D 0x00000000; + p->cmr =3D 0x00000000; + p->pdr =3D 0x00000000; + p->pwdr =3D 0x00000000; + } + + s->ppr =3D 0x00000000; + s->csr =3D 0x00000000; + s->pcr =3D 0x00000000; + s->pier =3D 0x00000000; + s->piir =3D 0x00000000; +} + +static void npcm7xx_pwm_hold_reset(Object *obj) +{ + NPCM7xxPWMState *s =3D NPCM7XX_PWM(obj); + int i; + + for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; i++) { + qemu_irq_lower(s->pwm[i].irq); + } +} + +static void npcm7xx_pwm_init(Object *obj) +{ + NPCM7xxPWMState *s =3D NPCM7XX_PWM(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int i; + + for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; i++) { + NPCM7xxPWM *p =3D &s->pwm[i]; + p->module =3D s; + p->index =3D i; + sysbus_init_irq(sbd, &p->irq); + } + + memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s, + TYPE_NPCM7XX_PWM, 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + + for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + object_property_add_uint32_ptr(obj, "freq[*]", + &s->pwm[i].freq, OBJ_PROP_FLAG_READ); + object_property_add_uint32_ptr(obj, "duty[*]", + &s->pwm[i].duty, OBJ_PROP_FLAG_READ); + } +} + +static const VMStateDescription vmstate_npcm7xx_pwm =3D { + .name =3D "npcm7xx-pwm", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_BOOL(running, NPCM7xxPWM), + VMSTATE_BOOL(inverted, NPCM7xxPWM), + VMSTATE_UINT8(index, NPCM7xxPWM), + VMSTATE_UINT32(cnr, NPCM7xxPWM), + VMSTATE_UINT32(cmr, NPCM7xxPWM), + VMSTATE_UINT32(pdr, NPCM7xxPWM), + VMSTATE_UINT32(pwdr, NPCM7xxPWM), + VMSTATE_UINT32(freq, NPCM7xxPWM), + VMSTATE_UINT32(duty, NPCM7xxPWM), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_npcm7xx_pwm_module =3D { + .name =3D "npcm7xx-pwm-module", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(clock, NPCM7xxPWMState), + VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState, + NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pw= m, + NPCM7xxPWM), + VMSTATE_UINT32(ppr, NPCM7xxPWMState), + VMSTATE_UINT32(csr, NPCM7xxPWMState), + VMSTATE_UINT32(pcr, NPCM7xxPWMState), + VMSTATE_UINT32(pier, NPCM7xxPWMState), + VMSTATE_UINT32(piir, NPCM7xxPWMState), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM7xx PWM Controller"; + dc->vmsd =3D &vmstate_npcm7xx_pwm_module; + rc->phases.enter =3D npcm7xx_pwm_enter_reset; + rc->phases.hold =3D npcm7xx_pwm_hold_reset; +} + +static const TypeInfo npcm7xx_pwm_info =3D { + .name =3D TYPE_NPCM7XX_PWM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCM7xxPWMState), + .class_init =3D npcm7xx_pwm_class_init, + .instance_init =3D npcm7xx_pwm_init, +}; + +static void npcm7xx_pwm_register_type(void) +{ + type_register_static(&npcm7xx_pwm_info); +} +type_init(npcm7xx_pwm_register_type); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index ce15ffceb95..607cd38a210 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -64,6 +64,7 @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('= mst_fpga.c')) softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm7xx_clk.c', 'npcm7xx_gcr.c', + 'npcm7xx_pwm.c', 'npcm7xx_rng.c', )) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files( diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b5118acd3fd..d626b9d7a7c 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -120,6 +120,12 @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "of= fset: 0x%04" PRIx64 " valu npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: = 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset:= 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" =20 +# npcm7xx_pwm.c +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offs= et: 0x%04" PRIx64 " value: 0x%08" PRIx32 +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s off= set: 0x%04" PRIx64 " value: 0x%08" PRIx32 +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value,= uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value,= uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" + # stm32f4xx_syscfg.c stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %= d, Line: %d; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FYSx5C1RllXjCPZSgL2+iGMXVBbHtGDyiRvXwgE4uRQ=; b=H1UW5eSXP5XjfS/5haE8pHMUur5ng/zP0zyeVknn0JodmmngLpFbjfdU8SbAvdl4D9 x1UI8ksEDmeZ6DL14+NvLYJ9uEy9cZhg6xmFPkY8+sZgPAFPDcnTPOQ24/q7hnyCGDn0 VX1bWNBDvpA9MVxWscii1g4mKGU9DhMBh7vLFtmFst3dOk0nlddMvcn/mUouw+LVtFvQ 9qlGffrF8GgrJqlKxs19U+43Y1qi/9Dj1ZF9O4coPqg+24G/4eBUK2CWUymMqm0IbLcN ReBnIfL7UgFRsDt9vJ57AW/ARujMnkz/gwEAtynd2j1VToJEKgSSuKReFy+Q+Y5Zx/gL KWLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FYSx5C1RllXjCPZSgL2+iGMXVBbHtGDyiRvXwgE4uRQ=; b=Sf8yN8bwhd06Zkr9kQbhjRvtM0V5cxapOuCyGN6qg3Xh1YngJAs8U0WrchI8/RkF9N nhdLMEdWpXb+PONFxHqH0P7tAB2ufFR/zRUn2zkDWLD7r5AKnOpjHAFdhnmRdaYVa4Hu OHyWVLWhmQ8s94k5iHAEIxxDPienNpBq99FV/q6BMNhzu1m6LcFD1C7vr96X9qDJEtjc Ct7FmrZl2UronWz/kMXID6SdcErX9tooeZznZLI2Ec3Pu8tnBNBojuXgWbSBWJIxEkpD XlupZs5NFZIPMa41OHcJuvJFsKlDWLANZ/qzYHYJa1QMJROLWFSVVD/iHfTkOTEc+sc7 3ZCg== X-Gm-Message-State: AOAM533SwrlgkkC6L3B6mG+u6BlJr7V4kEO9Jeja1OdaukjMtnZTpQOx bQonkA9PoXNZqUqIVHL08MdLia3Rq16UWA== X-Google-Smtp-Source: ABdhPJy4Fk22iD5mpDcxaqPIHxodA93XssUbyYsWKEHliS+i7c1CthvEXKAMwAoVAkpvsaQQTkbWIw== X-Received: by 2002:a7b:c182:: with SMTP id y2mr173741wmi.57.1610470696946; Tue, 12 Jan 2021 08:58:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/21] hw/misc: Add QTest for NPCM7XX PWM Module Date: Tue, 12 Jan 2021 16:57:48 +0000 Message-Id: <20210112165750.30475-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu We add a qtest for the PWM in the previous patch. It proves it works as expected. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Reviewed-by: Peter Maydell Message-id: 20210108190945.949196-6-wuhaotsh@google.com Signed-off-by: Peter Maydell --- tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 491 insertions(+) create mode 100644 tests/qtest/npcm7xx_pwm-test.c diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c new file mode 100644 index 00000000000..33fbdf5f545 --- /dev/null +++ b/tests/qtest/npcm7xx_pwm-test.c @@ -0,0 +1,490 @@ +/* + * QTests for Nuvoton NPCM7xx PWM Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "libqos/libqtest.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" + +#define REF_HZ 25000000 + +/* Register field definitions. */ +#define CH_EN BIT(0) +#define CH_INV BIT(2) +#define CH_MOD BIT(3) + +/* Registers shared between all PWMs in a module */ +#define PPR 0x00 +#define CSR 0x04 +#define PCR 0x08 +#define PIER 0x3c +#define PIIR 0x40 + +/* CLK module related */ +#define CLK_BA 0xf0801000 +#define CLKSEL 0x04 +#define CLKDIV1 0x08 +#define CLKDIV2 0x2c +#define PLLCON0 0x0c +#define PLLCON1 0x10 +#define PLL_INDV(rv) extract32((rv), 0, 6) +#define PLL_FBDV(rv) extract32((rv), 16, 12) +#define PLL_OTDV1(rv) extract32((rv), 8, 3) +#define PLL_OTDV2(rv) extract32((rv), 13, 3) +#define APB3CKDIV(rv) extract32((rv), 28, 2) +#define CLK2CKDIV(rv) extract32((rv), 0, 1) +#define CLK4CKDIV(rv) extract32((rv), 26, 2) +#define CPUCKSEL(rv) extract32((rv), 0, 2) + +#define MAX_DUTY 1000000 + +typedef struct PWMModule { + int irq; + uint64_t base_addr; +} PWMModule; + +typedef struct PWM { + uint32_t cnr_offset; + uint32_t cmr_offset; + uint32_t pdr_offset; + uint32_t pwdr_offset; +} PWM; + +typedef struct TestData { + const PWMModule *module; + const PWM *pwm; +} TestData; + +static const PWMModule pwm_module_list[] =3D { + { + .irq =3D 93, + .base_addr =3D 0xf0103000 + }, + { + .irq =3D 94, + .base_addr =3D 0xf0104000 + } +}; + +static const PWM pwm_list[] =3D { + { + .cnr_offset =3D 0x0c, + .cmr_offset =3D 0x10, + .pdr_offset =3D 0x14, + .pwdr_offset =3D 0x44, + }, + { + .cnr_offset =3D 0x18, + .cmr_offset =3D 0x1c, + .pdr_offset =3D 0x20, + .pwdr_offset =3D 0x48, + }, + { + .cnr_offset =3D 0x24, + .cmr_offset =3D 0x28, + .pdr_offset =3D 0x2c, + .pwdr_offset =3D 0x4c, + }, + { + .cnr_offset =3D 0x30, + .cmr_offset =3D 0x34, + .pdr_offset =3D 0x38, + .pwdr_offset =3D 0x50, + }, +}; + +static const int ppr_base[] =3D { 0, 0, 8, 8 }; +static const int csr_base[] =3D { 0, 4, 8, 12 }; +static const int pcr_base[] =3D { 0, 8, 12, 16 }; + +static const uint32_t ppr_list[] =3D { + 0, + 1, + 10, + 100, + 255, /* Max possible value. */ +}; + +static const uint32_t csr_list[] =3D { + 0, + 1, + 2, + 3, + 4, /* Max possible value. */ +}; + +static const uint32_t cnr_list[] =3D { + 0, + 1, + 50, + 100, + 150, + 200, + 1000, + 10000, + 65535, /* Max possible value. */ +}; + +static const uint32_t cmr_list[] =3D { + 0, + 1, + 10, + 50, + 100, + 150, + 200, + 1000, + 10000, + 65535, /* Max possible value. */ +}; + +/* Returns the index of the PWM module. */ +static int pwm_module_index(const PWMModule *module) +{ + ptrdiff_t diff =3D module - pwm_module_list; + + g_assert_true(diff >=3D 0 && diff < ARRAY_SIZE(pwm_module_list)); + + return diff; +} + +/* Returns the index of the PWM entry. */ +static int pwm_index(const PWM *pwm) +{ + ptrdiff_t diff =3D pwm - pwm_list; + + g_assert_true(diff >=3D 0 && diff < ARRAY_SIZE(pwm_list)); + + return diff; +} + +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char = *name) +{ + QDict *response; + + g_test_message("Getting properties %s from %s", name, path); + response =3D qtest_qmp(qts, "{ 'execute': 'qom-get'," + " 'arguments': { 'path': %s, 'property': %s}}", + path, name); + /* The qom set message returns successfully. */ + g_assert_true(qdict_haskey(response, "return")); + return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return"))); +} + +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_in= dex) +{ + char path[100]; + char name[100]; + + sprintf(path, "/machine/soc/pwm[%d]", module_index); + sprintf(name, "freq[%d]", pwm_index); + + return pwm_qom_get(qts, path, name); +} + +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_in= dex) +{ + char path[100]; + char name[100]; + + sprintf(path, "/machine/soc/pwm[%d]", module_index); + sprintf(name, "duty[%d]", pwm_index); + + return pwm_qom_get(qts, path, name); +} + +static uint32_t get_pll(uint32_t con) +{ + return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con) + * PLL_OTDV2(con)); +} + +static uint64_t read_pclk(QTestState *qts) +{ + uint64_t freq =3D REF_HZ; + uint32_t clksel =3D qtest_readl(qts, CLK_BA + CLKSEL); + uint32_t pllcon; + uint32_t clkdiv1 =3D qtest_readl(qts, CLK_BA + CLKDIV1); + uint32_t clkdiv2 =3D qtest_readl(qts, CLK_BA + CLKDIV2); + + switch (CPUCKSEL(clksel)) { + case 0: + pllcon =3D qtest_readl(qts, CLK_BA + PLLCON0); + freq =3D get_pll(pllcon); + break; + case 1: + pllcon =3D qtest_readl(qts, CLK_BA + PLLCON1); + freq =3D get_pll(pllcon); + break; + case 2: + break; + case 3: + break; + default: + g_assert_not_reached(); + } + + freq >>=3D (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv= 2)); + + return freq; +} + +static uint32_t pwm_selector(uint32_t csr) +{ + switch (csr) { + case 0: + return 2; + case 1: + return 4; + case 2: + return 8; + case 3: + return 16; + case 4: + return 1; + default: + g_assert_not_reached(); + } +} + +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t c= sr, + uint32_t cnr) +{ + return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1)); +} + +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) +{ + uint64_t duty; + + if (cnr =3D=3D 0) { + /* PWM is stopped. */ + duty =3D 0; + } else if (cmr >=3D cnr) { + duty =3D MAX_DUTY; + } else { + duty =3D MAX_DUTY * (cmr + 1) / (cnr + 1); + } + + if (inverted) { + duty =3D MAX_DUTY - duty; + } + + return duty; +} + +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned off= set) +{ + return qtest_readl(qts, td->module->base_addr + offset); +} + +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset, + uint32_t value) +{ + qtest_writel(qts, td->module->base_addr + offset, value); +} + +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td) +{ + return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)],= 8); +} + +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t va= lue) +{ + pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]); +} + +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td) +{ + return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)],= 3); +} + +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t va= lue) +{ + pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]); +} + +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td) +{ + return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)],= 4); +} + +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t va= lue) +{ + pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]); +} + +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td) +{ + return pwm_read(qts, td, td->pwm->cnr_offset); +} + +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t va= lue) +{ + pwm_write(qts, td, td->pwm->cnr_offset, value); +} + +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td) +{ + return pwm_read(qts, td, td->pwm->cmr_offset); +} + +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t va= lue) +{ + pwm_write(qts, td, td->pwm->cmr_offset, value); +} + +/* Check pwm registers can be reset to default value */ +static void test_init(gconstpointer test_data) +{ + const TestData *td =3D test_data; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + int module =3D pwm_module_index(td->module); + int pwm =3D pwm_index(td->pwm); + + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), =3D=3D, 0); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), =3D=3D, 0); + + qtest_quit(qts); +} + +/* One-shot mode should not change frequency and duty cycle. */ +static void test_oneshot(gconstpointer test_data) +{ + const TestData *td =3D test_data; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + int module =3D pwm_module_index(td->module); + int pwm =3D pwm_index(td->pwm); + uint32_t ppr, csr, pcr; + int i, j; + + pcr =3D CH_EN; + for (i =3D 0; i < ARRAY_SIZE(ppr_list); ++i) { + ppr =3D ppr_list[i]; + pwm_write_ppr(qts, td, ppr); + + for (j =3D 0; j < ARRAY_SIZE(csr_list); ++j) { + csr =3D csr_list[j]; + pwm_write_csr(qts, td, csr); + pwm_write_pcr(qts, td, pcr); + + g_assert_cmpuint(pwm_read_ppr(qts, td), =3D=3D, ppr); + g_assert_cmpuint(pwm_read_csr(qts, td), =3D=3D, csr); + g_assert_cmpuint(pwm_read_pcr(qts, td), =3D=3D, pcr); + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), =3D=3D, 0); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), =3D=3D, 0); + } + } + + qtest_quit(qts); +} + +/* In toggle mode, the PWM generates correct outputs. */ +static void test_toggle(gconstpointer test_data) +{ + const TestData *td =3D test_data; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + int module =3D pwm_module_index(td->module); + int pwm =3D pwm_index(td->pwm); + uint32_t ppr, csr, pcr, cnr, cmr; + int i, j, k, l; + uint64_t expected_freq, expected_duty; + + pcr =3D CH_EN | CH_MOD; + for (i =3D 0; i < ARRAY_SIZE(ppr_list); ++i) { + ppr =3D ppr_list[i]; + pwm_write_ppr(qts, td, ppr); + + for (j =3D 0; j < ARRAY_SIZE(csr_list); ++j) { + csr =3D csr_list[j]; + pwm_write_csr(qts, td, csr); + + for (k =3D 0; k < ARRAY_SIZE(cnr_list); ++k) { + cnr =3D cnr_list[k]; + pwm_write_cnr(qts, td, cnr); + + for (l =3D 0; l < ARRAY_SIZE(cmr_list); ++l) { + cmr =3D cmr_list[l]; + pwm_write_cmr(qts, td, cmr); + expected_freq =3D pwm_compute_freq(qts, ppr, csr, cnr); + expected_duty =3D pwm_compute_duty(cnr, cmr, false); + + pwm_write_pcr(qts, td, pcr); + g_assert_cmpuint(pwm_read_ppr(qts, td), =3D=3D, ppr); + g_assert_cmpuint(pwm_read_csr(qts, td), =3D=3D, csr); + g_assert_cmpuint(pwm_read_pcr(qts, td), =3D=3D, pcr); + g_assert_cmpuint(pwm_read_cnr(qts, td), =3D=3D, cnr); + g_assert_cmpuint(pwm_read_cmr(qts, td), =3D=3D, cmr); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), + =3D=3D, expected_duty); + if (expected_duty !=3D 0 && expected_duty !=3D 100) { + /* Duty cycle with 0 or 100 doesn't need frequency= . */ + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), + =3D=3D, expected_freq); + } + + /* Test inverted mode */ + expected_duty =3D pwm_compute_duty(cnr, cmr, true); + pwm_write_pcr(qts, td, pcr | CH_INV); + g_assert_cmpuint(pwm_read_pcr(qts, td), =3D=3D, pcr | = CH_INV); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), + =3D=3D, expected_duty); + if (expected_duty !=3D 0 && expected_duty !=3D 100) { + /* Duty cycle with 0 or 100 doesn't need frequency= . */ + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), + =3D=3D, expected_freq); + } + + } + } + } + } + + qtest_quit(qts); +} + +static void pwm_add_test(const char *name, const TestData* td, + GTestDataFunc fn) +{ + g_autofree char *full_name =3D g_strdup_printf( + "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->modu= le), + pwm_index(td->pwm), name); + qtest_add_data_func(full_name, td, fn); +} +#define add_test(name, td) pwm_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_l= ist)]; + + g_test_init(&argc, &argv, NULL); + + for (int i =3D 0; i < ARRAY_SIZE(pwm_module_list); ++i) { + for (int j =3D 0; j < ARRAY_SIZE(pwm_list); ++j) { + TestData *td =3D &test_data_list[i * ARRAY_SIZE(pwm_list) + j]; + + td->module =3D &pwm_module_list[i]; + td->pwm =3D &pwm_list[j]; + + add_test(init, td); + add_test(oneshot, td); + add_test(toggle, td); + } + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 955710d1c5d..0b5467f0844 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -136,6 +136,7 @@ qtests_sparc64 =3D \ qtests_npcm7xx =3D \ ['npcm7xx_adc-test', 'npcm7xx_gpio-test', + 'npcm7xx_pwm-test', 'npcm7xx_rng-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hljzW3VNw842X9fmZ052IHs9PJeCgTdh0vSWqneEEFc=; b=FgRfPcKuCzcBpnS91Uualu9dSOtdUfbIGp16FO//xXJ46iEAkZQsKwYWa/QeKWXmm2 PFtUVQB9sqonqu58fgdHvuq0EORthSLzDH4xsYVzuDlJ/xDMISS7XEyKQEF1czI45TKs O/IdK+5O/RijVEIMSeSl8/uJFofOctFbzWtKjXCpFX6vv/ZTTf4Oui/Iflt+XoDHVlcL xDcJl2fQhIw/1oaPOAmOjnty4OpGBQ1xUR/lJGFiTui3Hx+gjbZaTfOVeKWxf629iY+a uB5fmCii2ZIslwvCaVLTDQn8drTa1uh773u4d3/xWrMMW3vBYAus9EkKuAnZXK3ZI2in oQtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hljzW3VNw842X9fmZ052IHs9PJeCgTdh0vSWqneEEFc=; b=OSuxYcBuSXaMP3i3c3Afgs/NtEUsrljREx9W1Tk7v/Bjo0yYvFiNzKp+Zfib/VhbME 7GQPAUrVZ7L/oSxlnROCyHDqgoIMYi+HSCsFSdljnibhSm5SZpAv1bv3zgHKR5pT0kyI ZYyGLaR6fOvRmOmcZx31VBcePKkogBLTPJ3fi0T8AaJNx4OEP1d+AVOujo+gyb57sH8H xDFIcVch/tYF4zfxw+X9bytloQ2/bPL+jj1m2vkF0UJuQUsCQyeE4zQZGetP7QGB0TBk 1j1y3maufDB6+YcxXeHZwEUstF7HnzZlPe/WhqBv6OGdqQyMPjhlkKG9YE51mS9rjfnI UiGg== X-Gm-Message-State: AOAM533PkCLezJPySZw+kD7TnCMNt8o1iw1OBZmdQCXoHuncZG5TYOgm vXrmXXCllbJLH4w3AqWSJpgOUSsGaCMXMw== X-Google-Smtp-Source: ABdhPJy1h47HfhSswhDi++i1iwxyWYAHTI/wgFFvloXIJGHenZBseCgYdbeKWgf8am++2viSKEwIIQ== X-Received: by 2002:a1c:9a4d:: with SMTP id c74mr193831wme.5.1610470698304; Tue, 12 Jan 2021 08:58:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/21] hw/*: Use type casting for SysBusDevice in NPCM7XX Date: Tue, 12 Jan 2021 16:57:49 +0000 Message-Id: <20210112165750.30475-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu A device shouldn't access its parent object which is QOM internal. Instead it should use type cast for this purporse. This patch fixes this issue for all NPCM7XX Devices. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell Message-id: 20210108190945.949196-7-wuhaotsh@google.com Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 2 +- hw/mem/npcm7xx_mc.c | 2 +- hw/misc/npcm7xx_clk.c | 2 +- hw/misc/npcm7xx_gcr.c | 2 +- hw/misc/npcm7xx_rng.c | 2 +- hw/nvram/npcm7xx_otp.c | 2 +- hw/ssi/npcm7xx_fiu.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 306260fa671..3fdd5cab01d 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -82,7 +82,7 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *mac= hine, uint32_t hw_straps) { NPCM7xxMachineClass *nmc =3D NPCM7XX_MACHINE_GET_CLASS(machine); - MachineClass *mc =3D &nmc->parent; + MachineClass *mc =3D MACHINE_CLASS(nmc); Object *obj; =20 if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c index 0435d06ab44..abc5af56208 100644 --- a/hw/mem/npcm7xx_mc.c +++ b/hw/mem/npcm7xx_mc.c @@ -62,7 +62,7 @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **= errp) =20 memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs", NPCM7XX_MC_REGS_SIZE); - sysbus_init_mmio(&s->parent, &s->mmio); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); } =20 static void npcm7xx_mc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index 48bc9bdda55..0bcae9ce957 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -913,7 +913,7 @@ static void npcm7xx_clk_init(Object *obj) =20 memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, TYPE_NPCM7XX_CLK, 4 * KiB); - sysbus_init_mmio(&s->parent, &s->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } =20 static int npcm7xx_clk_post_load(void *opaque, int version_id) diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c index 745f6908097..eace9e1967a 100644 --- a/hw/misc/npcm7xx_gcr.c +++ b/hw/misc/npcm7xx_gcr.c @@ -220,7 +220,7 @@ static void npcm7xx_gcr_init(Object *obj) =20 memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s, TYPE_NPCM7XX_GCR, 4 * KiB); - sysbus_init_mmio(&s->parent, &s->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } =20 static const VMStateDescription vmstate_npcm7xx_gcr =3D { diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c index f650f3401f8..b01df7cdb25 100644 --- a/hw/misc/npcm7xx_rng.c +++ b/hw/misc/npcm7xx_rng.c @@ -143,7 +143,7 @@ static void npcm7xx_rng_init(Object *obj) =20 memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs", NPCM7XX_RNG_REGS_SIZE); - sysbus_init_mmio(&s->parent, &s->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } =20 static const VMStateDescription vmstate_npcm7xx_rng =3D { diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c index b16ca530baa..c61f2fc1aa2 100644 --- a/hw/nvram/npcm7xx_otp.c +++ b/hw/nvram/npcm7xx_otp.c @@ -371,7 +371,7 @@ static void npcm7xx_otp_realize(DeviceState *dev, Error= **errp) { NPCM7xxOTPClass *oc =3D NPCM7XX_OTP_GET_CLASS(dev); NPCM7xxOTPState *s =3D NPCM7XX_OTP(dev); - SysBusDevice *sbd =3D &s->parent; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 memset(s->array, 0, sizeof(s->array)); =20 diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 5040132b074..4eedb2927e7 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -498,7 +498,7 @@ static void npcm7xx_fiu_hold_reset(Object *obj) static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp) { NPCM7xxFIUState *s =3D NPCM7XX_FIU(dev); - SysBusDevice *sbd =3D &s->parent; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); int i; =20 if (s->cs_count <=3D 0) { --=20 2.20.1 From nobody Wed May 1 22:10:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610472426; cv=none; d=zohomail.com; s=zohoarc; b=HnDE7kh2RiYAoQpbw7LohJKgcj15npCq2M8LvVIIIqMB/f/s8wFZ4ODjFmDzsTlph9mTiEY7qH+dLQ+asfx7WUrbx63Rl/hrk7RU6TSxi4CrLczY3xlOUfCWXYesL2Mi1yxBHvdh01JMMm4HQAdhTk6c/nM7Z2HTqiGIt6P2vYI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610472426; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4AiUv8vR/uQVbGFxL8A/0x9RYxkd9rCpT0os8VNsY9I=; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i18sm6210083wrp.74.2021.01.12.08.58.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 08:58:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4AiUv8vR/uQVbGFxL8A/0x9RYxkd9rCpT0os8VNsY9I=; b=vhad0Sw6NPGqfoGQFMUlYNYERWtuGbtxw6ZuvE9oOh6IAN3x/zbhnJuDQtsm3dwU0L g+HldsgJ8GKSOGnX3SP8eQ60fHQruRbCELC/ZEHqcKhfb/uvtzasG+izr3x5/K3Uv68/ n0APx5ZL2boiKO9MBR0ZOApDcX6d8Tnqm4uXVS00koIALVgQQhfhSNnJau5hUfOKlT// 7zlQJKLzV9VLWd4OLWxqb4jwelLW/tAzA+HdGeb7zSvcEKWlNlt7kvNWo+2fVsyDpDDh TkS1JhO+PhOOtiVZMhTAPNZx8K1EoDYpmqVMIgm9pe+05X4UA1wli6qgwSII+brDX01P yaCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4AiUv8vR/uQVbGFxL8A/0x9RYxkd9rCpT0os8VNsY9I=; b=jdjFQqInGuxmz9k7Uj1Vrlbsx43VrqQ6c6C3bwrKusUL0W3SbZhSdudmgxcIIGjQIB vXkuIrGcnyV3XeXyZdOTdopNEIRFGxH7qQI/FzgDWJ7YoKs/ZDmIzFyh2WT2+rYyDoGF mNSNaNvsd20GaQrJOlAo+I9PJoKmWUj6FPt0saTvrqzmYgK29yK224ytT+PEwntcKNGV vsL33/ZHFz89x9gwH+J2gAPD/5uADI2/ak0Gid3FIqx/PRrNR34LIkqsfm2MGI77NePu vnFZG9f1UDi9YlXCzbF3OxzFJ1BbPV0IOZaSBYtavSERlR9rsYt/F+aRJp+xunkBhywU feIQ== X-Gm-Message-State: AOAM533LDpjF1H+h67z++8L6FbSpQsL9JrlWZDjT/osqqtiKvOwGtyGA of6Q0hehHI2/OJU+9SU3A+PcIs2LP1zhYw== X-Google-Smtp-Source: ABdhPJy4WJaf8sYfECrV+zkTrzGIrpuENRcktaJDPI5tcMrSNDy2sRw9DmLXEw88oBVUza9+gX11ag== X-Received: by 2002:a05:600c:22d7:: with SMTP id 23mr193774wmg.7.1610470699409; Tue, 12 Jan 2021 08:58:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/21] ui/cocoa: Fix openFile: deprecation on Big Sur Date: Tue, 12 Jan 2021 16:57:50 +0000 Message-Id: <20210112165750.30475-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210112165750.30475-1-peter.maydell@linaro.org> References: <20210112165750.30475-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Roman Bolshakov ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in= macOS 11.0 - Use -[NSWorkspace openURL:] instead. [-Wdeprecated-declarations] if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] =3D=3D= YES) { ^ /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Framewor= ks/AppKit.framework/Headers/NSWorkspace.h:350:1: note: 'openFile:' has been explicitly marked deprecated here - (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace ope= nURL:] instead.", macos(10.0, 11.0)); ^ Signed-off-by: Roman Bolshakov Reviewed-by: Peter Maydell Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com Signed-off-by: Peter Maydell --- ui/cocoa.m | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index e913a514455..13fba8103e1 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -1178,6 +1178,7 @@ QemuCocoaView *cocoaView; /* Where to look for local files */ NSString *path_array[] =3D {@"../share/doc/qemu/", @"../doc/qemu/", @"= docs/"}; NSString *full_file_path; + NSURL *full_file_url; =20 /* iterate thru the possible paths until the file is found */ int index; @@ -1186,7 +1187,9 @@ QemuCocoaView *cocoaView; full_file_path =3D [full_file_path stringByDeletingLastPathCompone= nt]; full_file_path =3D [NSString stringWithFormat: @"%@/%@%@", full_fi= le_path, path_array[index], filename]; - if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] =3D= =3D YES) { + full_file_url =3D [NSURL fileURLWithPath: full_file_path + isDirectory: false]; + if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] =3D=3D = YES) { return; } } --=20 2.20.1