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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+Mb3Gb3M8mku4NpiAEdzwbwGDJi9TG7kc1WGZbG7wr8=; b=AiA0hsFItQRCKYjjo3cYdF38rHmLaN9uBdkzN37njizg3WBWHJe11s5AgXum8IQkow GpQHNNpRuWXc3j8Wim0/7nEFNSAbkJl93AM4qWHk5wpLCjBmvPeI9wMcAfzkwSaE/4a0 IxiY2+pbIDqMPSHYmP4nsJ63jFz//E7Ewrq+q1WxCeh9OuvULevQRXc2KGmShvUObR33 22sOq8C61RKunQwdr7kmyEcWplqqXxwVJK83H1yGdZiUwk3i7Tez9aTgPRsNmXRfcKvk R4GVJffOcd65GlYGz6Kzuz5pr1V5jTEp/CF0P8pdu65kzexoe2GLY33DTBwMmrRxCgjj JVCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+Mb3Gb3M8mku4NpiAEdzwbwGDJi9TG7kc1WGZbG7wr8=; b=KU6AGGNzJ1ZEz0T82+iLclAMhVnFEuOfuqKpkNmqkvJf+zWUn9PTe9ONiLRrWIMkjt l+ZRRUV5GDwNpjwmL6tLpfl2mMg6iX9wCEgB4UUyFQlH04Jq5uXRZ8xKqD5FIFCBMfBk h7ldclEqaFAn5MDuGJdMh+E10USacsaRDC4ks90xb4s15N0GIvgIaPIiprQYv0AmxGIY or7ahmB/z0KNPgCTtLX7BSjufXn9F7606rb0awB2LXCkw6awWr3BKB24EsWNopGQ8cOR /uZ63/+q05yruDn0D/2QMNzC/VeOru2dG0c3Z3zbYB1U6+IsUgGwMUr6HKfPkYpJmDfN mCGw== X-Gm-Message-State: AOAM532g+dQOAoWIzuJawRVNKKypksE35iT1np4L3p6gJ1Gm1cuB5NWI Jom0PXojgOtIQ+/OpmZ0rsA= X-Google-Smtp-Source: ABdhPJxGw0hbeByYHLOMKZSRiBsuEz7yg10pbML/YRrDZbi5c0WJys+c4Oo0mP2pb0vT8BP73JAwZA== X-Received: by 2002:a17:902:a711:b029:da:f065:1315 with SMTP id w17-20020a170902a711b02900daf0651315mr5552623plq.36.1610463349100; Tue, 12 Jan 2021 06:55:49 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 3/6] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 12 Jan 2021 22:55:23 +0800 Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112145526.31095-1-bmeng.cn@gmail.com> References: <20210112145526.31095-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xuzhou Cheng , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- (no changes since v3) Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4d488b159a..880939f595 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -246,9 +246,15 @@ static void imx_spi_reset(DeviceState *dev) =20 static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_reset(DEVICE(s)); =20 imx_spi_update_irq(s); + + for (i =3D 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } =20 static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) --=20 2.25.1