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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id h16sm2865664pgd.62.2021.01.12.01.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 01:40:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AImtaI1XpU/izzOLPjkNcy0w+CEH9VQf4je2sAF5hjc=; b=cYBMynh6Btr7DczCZmA+XG+cwuYwjJ8OzN5PQu34WdfEl9R6s7SJuHFO9JAcTP/AHy VFn8gz0VKz7KqYCi2TH+kcgIstYS5KHsSkxdKSbkgSMyzQ1yqer4hW8hNsEVpy9tofr/ MU78EbzATMtvqU1gKhqb2ZR7Q5GaHbxmxiV+DfU1KJGqonL0nesMXlScKr5GG8+E5TFq gKsZPCGnSu0KnB3PcHJkQc8saMuyosxtkNvjjyVspWPxF/RlEXXwOn0qRXObXWBsbaG+ 8jmD/76laSbsPFITmd40FMWgVFGg8emElrL98qZXew/7yiyJxjhpd2e0vG495vO8RIan MfEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AImtaI1XpU/izzOLPjkNcy0w+CEH9VQf4je2sAF5hjc=; b=QkigMFKQ/9U0wxihRYcJRngXeMnlPe0h7LuL49mQJCyXvmB6De8+5+sc6MK/GuXJX2 UBczUkMrLAY2/Ox+KgsnZ+eD/Hi1JkKW4cnKdyqegQURbgYNAsoekbgpgt+yoA5D5cBx XR9l9DIy4Ijqo73xGVrWPMgUtmlZFHzWJ/7OJHJYUDJd2Ih6l93Z1iya67WjtBwdf2SO fna59smWUewo3Fe4PJsLPVtBNlT2pob7gG/BekB9yexsTLPkxFZ72J1J1FrsdpeqNIj+ qOxbyrPzXGxS0VjmahAjoFh1UCHJK5IlPRkZZgMP7c3KYOUJpKEELBvehKJKgfYIb3zo bgcg== X-Gm-Message-State: AOAM530KkUALMkYqLPyrtM9mjyckon/5plQeA0/w9nFjz4A7w9aYSwgT faHen3mVBnQCGw7kSZmJU9k2pDgIxne/mpGT X-Google-Smtp-Source: ABdhPJw+JEHs9lwoEdvsDSIN5gA8o3HdkL5AgDQhf/K4gZBxyAs7weSIvUMqrCRsxzcKisWCZh74cA== X-Received: by 2002:a63:4f04:: with SMTP id d4mr3920355pgb.225.1610444445096; Tue, 12 Jan 2021 01:40:45 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL Date: Tue, 12 Jan 2021 17:38:46 +0800 Message-Id: <20210112093950.17530-13-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210112093950.17530-1-frank.chang@sifive.com> References: <20210112093950.17530-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 17 +++++++++-------- target/riscv/translate.c | 16 ++++++++++++++-- target/riscv/vector_helper.c | 16 ++++++++++++++-- 3 files changed, 37 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cd5c77114a4..3b985f6218d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,10 +105,10 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 256 =20 -FIELD(VTYPE, VLMUL, 0, 2) -FIELD(VTYPE, VSEW, 2, 3) -FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, VLMUL, 0, 3) +FIELD(VTYPE, VSEW, 3, 3) +FIELD(VTYPE, VEDIV, 8, 2) +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { @@ -380,11 +380,12 @@ typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) -FIELD(TB_FLAGS, LMUL, 3, 2) -FIELD(TB_FLAGS, SEW, 5, 3) -FIELD(TB_FLAGS, VILL, 8, 1) +FIELD(TB_FLAGS, LMUL, 3, 3) +FIELD(TB_FLAGS, SEW, 6, 3) +/* Skip MSTATUS_VS (0x600) fields */ +FIELD(TB_FLAGS, VILL, 11, 1) /* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, HLSX, 12, 1) =20 bool riscv_cpu_is_32bit(CPURISCVState *env); =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18e198bf8a6..d9b3b37f698 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -60,7 +60,19 @@ typedef struct DisasContext { bool hlsx; /* vector extension */ bool vill; - uint8_t lmul; + /* + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ + int8_t lmul; uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; @@ -843,7 +855,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); - ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); + ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); } =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12301e943e6..aa8348ea25a 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VM); } =20 -static inline uint32_t vext_lmul(uint32_t desc) +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) { - return FIELD_EX32(simd_data(desc), VDATA, LMUL); + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); } =20 static uint32_t vext_wd(uint32_t desc) --=20 2.17.1