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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=66.111.4.224; envelope-from=jiaxun.yang@flygoat.com; helo=new2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Loongson IPI controller is a MMIO based simple level triggered interrupt controller. It will trigger IRQ to it's upstream processor when set register is written. It also has 8 32bit mailboxes to pass boot information to secondary processor. Signed-off-by: Jiaxun Yang --- hw/intc/Kconfig | 3 + hw/intc/loongson_ipi.c | 146 +++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + include/hw/intc/loongson_ipi.h | 20 +++++ 4 files changed, 170 insertions(+) create mode 100644 hw/intc/loongson_ipi.c create mode 100644 include/hw/intc/loongson_ipi.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index c18d11142a..0e15102662 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -59,6 +59,9 @@ config RX_ICU config LOONGSON_LIOINTC bool =20 +config LOONGSON_IPI + bool + config SIFIVE_CLINT bool =20 diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c new file mode 100644 index 0000000000..7246f05f9e --- /dev/null +++ b/hw/intc/loongson_ipi.c @@ -0,0 +1,146 @@ +/* + * QEMU Loongson Inter Processor Interrupt Controller + * + * Copyright (c) 2020-2021 Jiaxun Yang + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/module.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/intc/loongson_ipi.h" + +#define R_ISR 0 +#define R_IEN 1 +#define R_SET 2 +#define R_CLR 3 +/* No register between 0x10~0x20 */ +#define R_MBOX0 8 +#define NUM_MBOX 8 +#define R_END 16 + +struct loongson_ipi { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq parent_irq; + + uint32_t isr; + uint32_t ien; + uint32_t mbox[NUM_MBOX]; +}; + +static uint64_t +ipi_read(void *opaque, hwaddr addr, unsigned int size) +{ + struct loongson_ipi *p =3D opaque; + uint64_t r =3D 0; + + addr >>=3D 2; + switch (addr) { + case R_ISR: + r =3D p->isr; + break; + case R_IEN: + r =3D p->ien; + break; + case R_MBOX0 ... (R_END - 1): + r =3D p->mbox[addr - R_MBOX0]; + break; + default: + break; + } + + qemu_log_mask(CPU_LOG_INT, + "%s: size=3D%d, addr=3D%"HWADDR_PRIx", val=3D%"PRIx64"\n= ", + __func__, size, addr, r); + + return r; +} + +static void +ipi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + struct loongson_ipi *p =3D opaque; + uint32_t value =3D val64; + + addr >>=3D 2; + switch (addr) { + case R_ISR: + /* Do nothing */ + break; + case R_IEN: + p->ien =3D value; + break; + case R_SET: + p->isr |=3D value; + break; + case R_CLR: + p->isr &=3D ~value; + break; + case R_MBOX0 ... (R_END - 1): + p->mbox[addr - R_MBOX0] =3D value; + break; + default: + break; + } + p->isr &=3D p->ien; + + qemu_log_mask(CPU_LOG_INT, + "%s: size=3D%d, addr=3D%"HWADDR_PRIx", val=3D%"PRIx32"\n= ", + __func__, size, addr, value); + + qemu_set_irq(p->parent_irq, !!p->isr); +} + +static const MemoryRegionOps pic_ops =3D { + .read =3D ipi_read, + .write =3D ipi_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void loongson_ipi_init(Object *obj) +{ + struct loongson_ipi *p =3D LOONGSON_IPI(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); + + memory_region_init_io(&p->mmio, obj, &pic_ops, p, "loongson.ipi", + R_END * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); +} + +static const TypeInfo loongson_ipi_info =3D { + .name =3D TYPE_LOONGSON_IPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(struct loongson_ipi), + .instance_init =3D loongson_ipi_init, +}; + +static void loongson_ipi_register_types(void) +{ + type_register_static(&loongson_ipi_info); +} + +type_init(loongson_ipi_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 53cba11569..5257c5fb94 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -36,6 +36,7 @@ specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grl= ib_irqmp.c')) specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_= liointc.c')) +specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c')) specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c')) specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h new file mode 100644 index 0000000000..a535c467bf --- /dev/null +++ b/include/hw/intc/loongson_ipi.h @@ -0,0 +1,20 @@ +/* + * This file is subject to the terms and conditions of the GNU General Pub= lic + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2020-2021 Jiaxun Yang + * + */ + +#ifndef LOONGSON_IPI_H +#define LOONGSON_IPI_H + +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_LOONGSON_IPI "loongson.ipi" +#define LOONGSON_IPI(obj) OBJECT_CHECK(struct loongson_ipi, (obj), TYPE_LO= ONGSON_IPI) + +#endif /* LOONGSON_IPI_H */ --=20 2.30.0