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Mon, 11 Jan 2021 18:20:36 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v3 05/16] target/riscv: rvb: pack two words into one register Date: Tue, 12 Jan 2021 10:19:46 +0800 Message-Id: <20210112022001.20521-6-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210112022001.20521-1-frank.chang@sifive.com> References: <20210112022001.20521-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvb.c.inc | 30 +++++++++++++++++++ target/riscv/translate.c | 40 +++++++++++++++++++++++++ 4 files changed, 76 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 89498a9a28a..d28c0bcf2c1 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -91,3 +91,6 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s clzw 0110000 00000 ..... 001 ..... 0011011 @r2 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 + +packw 0000100 .......... 100 ..... 0111011 @r +packuw 0100100 .......... 100 ..... 0111011 @r diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d0b3f109b4e..7f32b8c6d15 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -602,3 +602,6 @@ cpop 011000 000010 ..... 001 ..... 0010011 @r2 andn 0100000 .......... 111 ..... 0110011 @r orn 0100000 .......... 110 ..... 0110011 @r xnor 0100000 .......... 100 ..... 0110011 @r +pack 0000100 .......... 100 ..... 0110011 @r +packu 0100100 .......... 100 ..... 0110011 @r +packh 0000100 .......... 111 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 73c4693a263..2d24dafac09 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) return gen_arith(ctx, a, tcg_gen_eqv_tl); } =20 +static bool trans_pack(DisasContext *ctx, arg_pack *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, gen_pack); +} + +static bool trans_packu(DisasContext *ctx, arg_packu *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, gen_packu); +} + +static bool trans_packh(DisasContext *ctx, arg_packh *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, gen_packh); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 =20 @@ -74,4 +92,16 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) return gen_unary(ctx, a, gen_cpopw); } =20 +static bool trans_packw(DisasContext *ctx, arg_packw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, gen_packw); +} + +static bool trans_packuw(DisasContext *ctx, arg_packuw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, gen_packuw); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3a14bdba194..53c0c34ce16 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -711,6 +711,29 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r = *a, =20 #endif =20 +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_deposit_tl(ret, arg1, arg2, + TARGET_LONG_BITS / 2, + TARGET_LONG_BITS / 2); +} + +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); + tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); + tcg_temp_free(t); +} + +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_ext8u_tl(t, arg2); + tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); + tcg_temp_free(t); +} + #ifdef TARGET_RISCV64 =20 static void gen_ctzw(TCGv ret, TCGv arg1) @@ -732,6 +755,23 @@ static void gen_cpopw(TCGv ret, TCGv arg1) tcg_gen_ctpop_tl(ret, arg1); } =20 +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_ext16s_i64(t, arg2); + tcg_gen_deposit_i64(ret, arg1, t, 16, 48); + tcg_temp_free(t); +} + +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_shri_i64(t, arg1, 16); + tcg_gen_deposit_i64(ret, arg2, t, 0, 16); + tcg_gen_ext32s_i64(ret, ret); + tcg_temp_free(t); +} + #endif =20 static bool gen_arith(DisasContext *ctx, arg_r *a, --=20 2.17.1