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Mon, 11 Jan 2021 18:20:27 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v3 03/16] target/riscv: rvb: count bits set Date: Tue, 12 Jan 2021 10:19:44 +0800 Message-Id: <20210112022001.20521-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210112022001.20521-1-frank.chang@sifive.com> References: <20210112022001.20521-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Signed-off-by: Frank Chang --- target/riscv/insn32-64.decode | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++ target/riscv/translate.c | 6 ++++++ 4 files changed, 20 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index f4c42720fc7..89498a9a28a 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s # *** RV64B Standard Extension (in addition to RV32B) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8fe838cf0d0..0e321da37f4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 = @r # *** RV32B Standard Extension *** clz 011000 000000 ..... 001 ..... 0010011 @r2 ctz 011000 000001 ..... 001 ..... 0010011 @r2 +cpop 011000 000010 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 76788c2f353..dbbd94e1015 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a) return gen_unary(ctx, a, gen_ctz); } =20 +static bool trans_cpop(DisasContext *ctx, arg_cpop *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, tcg_gen_ctpop_tl); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 =20 @@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) return gen_unary(ctx, a, gen_ctzw); } =20 +static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, gen_cpopw); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fac111d465c..3a14bdba194 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -726,6 +726,12 @@ static void gen_clzw(TCGv ret, TCGv arg1) tcg_gen_subi_i64(ret, ret, 32); } =20 +static void gen_cpopw(TCGv ret, TCGv arg1) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_ctpop_tl(ret, arg1); +} + #endif =20 static bool gen_arith(DisasContext *ctx, arg_r *a, --=20 2.17.1