From nobody Tue Nov 18 11:51:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610406814; cv=none; d=zohomail.com; s=zohoarc; b=kHKS+hk4YRQAWLE1fOPtADcfP5XQ4YOEz0EvUxlkKCpP8GcWhBqQQYkepgXfAaGF02Z+wu1Ws4GLYGEKjuShESdI5LDmbfZFuUzT8RKHyWPlFWFj4IeqAzyIJQH5mKOYr5PajqWLrCj9hlAB8MGqcNxC3vYogZEn/LaYm6yf62k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610406814; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U455LnEVSnoXmT1SthMNmvTNVVMjJpc4M0FyXL5sXrI=; b=FjPNXLq2zk/fukV0X5wtJGDEITupmikJFaJzvUjVleOtfd1xgC3CJkgrspBBZ5msrXJPj2rAAzNf43Ao0l3FV1GflvEwlo5Y27T0qh1DqJUdD5msCFN2uGyeUemqeuImRUjHA8Adv7en2wqw/Vl7Q0mGcqwFz6C2UpLKSi2lMzk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610406814434194.59020138746382; Mon, 11 Jan 2021 15:13:34 -0800 (PST) Received: from localhost ([::1]:49638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kz6NR-0006cT-70 for importer@patchew.org; Mon, 11 Jan 2021 18:13:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz6LJ-0004f0-E7 for qemu-devel@nongnu.org; Mon, 11 Jan 2021 18:11:22 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:44841) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz6LF-0006CP-Ad for qemu-devel@nongnu.org; Mon, 11 Jan 2021 18:11:21 -0500 Received: by mail-pl1-x635.google.com with SMTP id r4so319969pls.11 for ; Mon, 11 Jan 2021 15:11:16 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id g202sm658105pfb.196.2021.01.11.15.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:11:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U455LnEVSnoXmT1SthMNmvTNVVMjJpc4M0FyXL5sXrI=; b=iu0T6y9EmcCQbyAlTyctcEd/3+Aoqz5w6T2srPCSv6s+E5GnBX+J2sMzTuYWpvcjfg UOMLsoJpNCRF7WD+ZmFQnfWESdlZmjf+gdSknibrcNvirL8j7V4Ch9RnbIAx1A3mLhOp MC/BOJMJsOv44sgnua4073qlezV0VPRvphY+LmddXN+1m3i0ccXuPRcnjs9NZ6jbw6mP 1/u1UbcpbE4PznyjhEQtdfwvskdOUc2hD6BtQ4QTmEd5I0V04xavd/Shxp0BZyiNH771 ozaVM6exLpFzjnQ+s2qvBUfxuvdrqY9ZhmVhjYMFtiw8gakerB7t8i8HzgJtpifuAcRZ Mn8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U455LnEVSnoXmT1SthMNmvTNVVMjJpc4M0FyXL5sXrI=; b=sgyjhn44n4+JNth7UU3AwI4pispoFwpUP4lo0eqVTibQXSA9FBPdcL7SURLhx9V41o 08ZOzi9w8ODJPX3A4el+pOzSLubTLauS1FbY2WxumLw8+os0G2B/mKz3kCgunLdamZlV rsprwo1Oe/2Un2XbaDDz4y8UdkJNdwfaUtZY2Y5JeUFYrnAFjt2SK9u6Z3kF9cpITnns ONb75RcJzjpAaGbJklHLowaXbR5XUpJE5cwg/DSsyEZbzcY+FZ60bnU1qeZ7BiCRnbOm KpkgS5JJMZrJHJ8ajHRNO8VKAzr9Hw8TUEEAUhEuRLWOROsoOuBWAxpxcM/9dSMPELJM wxEA== X-Gm-Message-State: AOAM530192nCNFMnPrPSREboiBZGPZ3irJpewT8RlOPJoYYmuBZtph7E I0Q/PcU+zzsigH94y9eeMhfnwwkocIj6rw== X-Google-Smtp-Source: ABdhPJyIS0almxyUub2B8VZ8TE9B0SK2lqI9ShNb6XWabwcV5iUYYpFY3UBFkZaee1N36Fh+rq/VJg== X-Received: by 2002:a17:90a:68ca:: with SMTP id q10mr1266866pjj.15.1610406675430; Mon, 11 Jan 2021 15:11:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 2/3] target/arm: Add cpu properties to control pauth Date: Mon, 11 Jan 2021 13:11:07 -1000 Message-Id: <20210111231108.461088-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111231108.461088-1-richard.henderson@linaro.org> References: <20210111231108.461088-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , peter.maydell@linaro.org, Andrew Jones , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The crypto overhead of emulating pauth can be significant for some workloads. Add two boolean properties that allows the feature to be turned off, on with the architected algorithm, or on with an implementation defined algorithm. We need two intermediate booleans to control the state while parsing properties lest we clobber ID_AA64ISAR1 into an invalid intermediate state. Tested-by: Mark Rutland Reviewed-by: Andrew Jones Signed-off-by: Richard Henderson --- v2: Use boolean properties instead of an enum (drjones). v3: Add tests (drjones). v6: Add documentation (pmm). --- docs/system/arm/cpu-features.rst | 21 +++++++++++++++++ target/arm/cpu.h | 10 ++++++++ target/arm/cpu.c | 13 +++++++++++ target/arm/cpu64.c | 40 ++++++++++++++++++++++++++++---- target/arm/monitor.c | 3 ++- tests/qtest/arm-cpu-features.c | 13 +++++++++++ 6 files changed, 95 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 35196a6b75..70e0e4ef78 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -211,6 +211,27 @@ the list of KVM VCPU features and their descriptions. influence the guest scheduler behavior and/or be exposed to the guest userspace. =20 +TCG VCPU Features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +TCG VCPU features are CPU features that are specific to TCG. +Below is the list of TCG VCPU features and their descriptions. + + pauth Enable or disable `FEAT_Pauth`, pointer + authentication. By default, the feature is + enabled with `-cpu max`. + + pauth-impdef When `FEAT_Pauth` is enabled, either the + *impdef* (Implementation Definined) algorithm + is enabled or the *architected* QARMA algorithm + is enabled. By default the impdef algorithm + is disabled, and QARMA is enabled. + + The architected QARMA algorithm has good + cryptographic properties, but can be quite slow + to emulate. The impdef algorithm is + non-cryptographic but significantly faster. + SVE CPU Properties =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 70e9618d13..06f5169f45 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -197,9 +197,11 @@ typedef struct { #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } +static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } #endif =20 typedef struct ARMVectorReg { @@ -947,6 +949,14 @@ struct ARMCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + + /* + * Intermediate values used during property parsing. + * Once finalized, the values should be read from ID_AA64ISAR1. + */ + bool prop_pauth; + bool prop_pauth_impdef; + /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; uint64_t rvbar; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8387e94b94..be18df5464 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1320,6 +1320,19 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) error_propagate(errp, local_err); return; } + + /* + * KVM does not support modifications to this feature. + * We have not registered the cpu properties when KVM + * is in use, so the user will not be able to set them. + */ + if (!kvm_enabled()) { + arm_cpu_pauth_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + } } =20 if (kvm_enabled()) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7cf9fc4bc6..d9feaa9cdb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -28,6 +28,8 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "qapi/visitor.h" +#include "hw/qdev-properties.h" + =20 #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) @@ -572,6 +574,36 @@ void aarch64_add_sve_properties(Object *obj) } } =20 +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +{ + int arch_val =3D 0, impdef_val =3D 0; + uint64_t t; + + /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ + if (cpu->prop_pauth) { + if (cpu->prop_pauth_impdef) { + impdef_val =3D 1; + } else { + arch_val =3D 1; + } + } else if (cpu->prop_pauth_impdef) { + error_setg(errp, "cannot enable pauth-impdef without pauth"); + error_append_hint(errp, "Add pauth=3Don to the CPU property list.\= n"); + } + + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); + t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); + t =3D FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); + t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); + cpu->isar.id_aa64isar1 =3D t; +} + +static Property arm_cpu_pauth_property =3D + DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); +static Property arm_cpu_pauth_impdef_property =3D + DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -627,10 +659,6 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected o= nly */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); - t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); @@ -720,6 +748,10 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT i= cache */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif + + /* Default to PAUTH on, with the architected algorithm. */ + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_proper= ty); } =20 aarch64_add_sve_properties(obj); diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 198b14e95e..1fdb965eb8 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -94,7 +94,8 @@ static const char *cpu_model_advertised_features[] =3D { "sve128", "sve256", "sve384", "sve512", "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", - "kvm-no-adjvtime", "kvm-steal-time", + "kvm-no-adjvtime", + "pauth", "pauth-impdef", NULL }; =20 diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index bc681a95d5..8252b85bb8 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -427,6 +427,18 @@ static void sve_tests_sve_off_kvm(const void *data) qtest_quit(qts); } =20 +static void pauth_tests_default(QTestState *qts, const char *cpu_type) +{ + assert_has_feature_enabled(qts, cpu_type, "pauth"); + assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); + assert_set_feature(qts, cpu_type, "pauth", false); + assert_set_feature(qts, cpu_type, "pauth", true); + assert_set_feature(qts, cpu_type, "pauth-impdef", true); + assert_set_feature(qts, cpu_type, "pauth-impdef", false); + assert_error(qts, cpu_type, "cannot enable pauth-impdef without pauth", + "{ 'pauth': false, 'pauth-impdef': true }"); +} + static void test_query_cpu_model_expansion(const void *data) { QTestState *qts; @@ -462,6 +474,7 @@ static void test_query_cpu_model_expansion(const void *= data) assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); =20 sve_tests_default(qts, "max"); + pauth_tests_default(qts, "max"); =20 /* Test that features that depend on KVM generate errors without. = */ assert_error(qts, "max", --=20 2.25.1