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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u3gPsRgSV9emvsK63Aw7U+QzPwKlYGtgQ7T1VzVraGc=; b=tsvogfq8bMSN8rPfJF/PwGWlTD/SgDMoQ36jhWYakN53EEajAbco025MdjTqVPY7+2 wujiCdqqbQcrwmnMvQkKKJ8woILa6Ysc/X5erETzpoeK8W3sLlqe2HbGJyJ0tk0KKWMr eynd8sVT24zn0yItzQ7Hc0Emv51+Rkpfa6vt3UvfbPcz/zIulgvGOT013D7R2rUVxP2X umm2Bcd5NELT9xVgFOPHRGuxmMT8dCPX5IJFkV//dDDmhBkmWTOhpXBZlZa6NKgZpOZE It4fBO2QoUp4TOR16a451D/bdpzd9HA50JZ+tuxPvv5eTsbMlJaiDZOBFUfSGJmSbuCA iDGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u3gPsRgSV9emvsK63Aw7U+QzPwKlYGtgQ7T1VzVraGc=; b=Gl/jT/MLCZJMSfhFBGrPpEy70faua9tOxBBHSwUlPnYAKo4vIb/bwCGFk8iKPfhEpE 6xrQTLR4AK+ekk8Ar7QeZWYAi+55MAOnl5PukfmlKq+GGhywx4BW7aoC+fJS4NGWBh2w I3YAylNtTXgQKSzrqoAVgaXyZew5tXiSYrRDR4+nnY+12VFGIpo8UaWArZe7KPDPeaHu su7vukyApQZ8o4ULkEolZ4541s37bkyWi5qha7Xo1/FKkHH7qQXClhXC1TrbhaWrJhpy m0fm+B8mGiPJU3YAnZ5xmDcaKoxUIlrUKqcbtXkpgE9Iuj2jjE6QSQu7AIYjORSxGVx6 ztMw== X-Gm-Message-State: AOAM53318uOxkL7dGB8KTFSRLm6CaisgcebHR2lNvCvbHeXwjiUQuoD5 ccg/57Z5deUQsRQ5y9s7js4vORgjfjOJVg== X-Google-Smtp-Source: ABdhPJzWfjzfYh6nVsorxA6m0aHVwuRGwLyUnxSpmw7rqO78uceHrd5bYJqU5zk14G/yyZUOAZ8dBw== X-Received: by 2002:a17:90a:e64e:: with SMTP id ep14mr276172pjb.5.1610391685019; Mon, 11 Jan 2021 11:01:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags Date: Mon, 11 Jan 2021 09:00:48 -1000 Message-Id: <20210111190113.303726-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In preparation for splitting tb->flags across multiple fields, introduce a structure to hold the value(s). So far this only migrates the one uint32_t and fixes all of the places that require adjustment to match. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 +++++++++++--------- target/arm/translate.h | 11 +++++++++ target/arm/helper.c | 50 +++++++++++++++++++++----------------- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 7 +++--- 5 files changed, 59 insertions(+), 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 894266ef02..c7700c9c85 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -218,6 +218,10 @@ typedef struct ARMPACKey { } ARMPACKey; #endif =20 +/* See the commentary above the TBFLAG field definitions. */ +typedef struct CPUARMTBFlags { + uint32_t flags; +} CPUARMTBFlags; =20 typedef struct CPUARMState { /* Regs for current mode. */ @@ -246,7 +250,7 @@ typedef struct CPUARMState { uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.n= RW */ =20 /* Cached TBFLAGS state. See below for which bits are included. */ - uint32_t hflags; + CPUARMTBFlags hflags; =20 /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access @@ -3336,21 +3340,21 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) * Helpers for using the above. */ #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL)) #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL)) =20 -#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH) -#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH) -#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH) -#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH) +#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH) =20 /** * cpu_mmu_index: diff --git a/target/arm/translate.h b/target/arm/translate.h index 423b0e08df..f30287e554 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -394,6 +394,17 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TC= Gv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); =20 +/** + * arm_tbflags_from_tb: + * @tb: the TranslationBlock + * + * Extract the flag values from @tb. + */ +static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) +{ + return (CPUARMTBFlags){ tb->flags }; +} + /* * Enum for argument to fpstatus_ptr(). */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 76bb306f26..cc73acc927 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12743,8 +12743,9 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif =20 -static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags +rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); @@ -12755,8 +12756,9 @@ static uint32_t rebuild_hflags_common(CPUARMState *= env, int fp_el, return flags; } =20 -static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags +rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { bool sctlr_b =3D arm_sctlr_b(env); =20 @@ -12771,10 +12773,10 @@ static uint32_t rebuild_hflags_common_32(CPUARMSt= ate *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_m32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags =3D 0; + CPUARMTBFlags flags =3D {}; =20 if (arm_v7m_is_handler_mode(env)) { DP_TBFLAG_M32(flags, HANDLER, 1); @@ -12794,18 +12796,19 @@ static uint32_t rebuild_hflags_m32(CPUARMState *e= nv, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +static CPUARMTBFlags +rebuild_hflags_aprofile(CPUARMState *env) { - int flags =3D 0; + CPUARMTBFlags flags =3D {}; =20 DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); return flags; } =20 -static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags =3D rebuild_hflags_aprofile(env); + CPUARMTBFlags flags =3D rebuild_hflags_aprofile(env); =20 if (arm_el_is_aa64(env, 1)) { DP_TBFLAG_A32(flags, VFPEN, 1); @@ -12819,10 +12822,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *e= nv, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags =3D rebuild_hflags_aprofile(env); + CPUARMTBFlags flags =3D rebuild_hflags_aprofile(env); ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; @@ -12937,7 +12940,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_internal(CPUARMState *env) +static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) { int el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, el); @@ -12966,6 +12969,7 @@ void HELPER(rebuild_hflags_m32_newel)(CPUARMState *= env) int el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, el); ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); } =20 @@ -12986,6 +12990,7 @@ void HELPER(rebuild_hflags_a32_newel)(CPUARMState *= env) int el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, el); ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + env->hflags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); } =20 @@ -13008,12 +13013,12 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env,= int el) static inline void assert_hflags_rebuild_correctly(CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG - uint32_t env_flags_current =3D env->hflags; - uint32_t env_flags_rebuilt =3D rebuild_hflags_internal(env); + CPUARMTBFlags c =3D env->hflags; + CPUARMTBFlags r =3D rebuild_hflags_internal(env); =20 - if (unlikely(env_flags_current !=3D env_flags_rebuilt)) { + if (unlikely(c.flags !=3D r.flags)) { fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08= x)\n", - env_flags_current, env_flags_rebuilt); + c.flags, r.flags); abort(); } #endif @@ -13022,11 +13027,12 @@ static inline void assert_hflags_rebuild_correctl= y(CPUARMState *env) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags =3D env->hflags; + CPUARMTBFlags flags; uint32_t pstate_for_ss; =20 *cs_base =3D 0; assert_hflags_rebuild_correctly(env); + flags =3D env->hflags; =20 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { *pc =3D env->pc; @@ -13094,7 +13100,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } =20 - *pflags =3D flags; + *pflags =3D flags.flags; } =20 #ifdef TARGET_AARCH64 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c260fc573d..010e81e0b4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14685,7 +14685,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D env_archcpu(env); - uint32_t tb_flags =3D dc->base.tb->flags; + CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(dc->base.tb); int bound, core_mmu_idx; =20 dc->isar =3D &arm_cpu->isar; diff --git a/target/arm/translate.c b/target/arm/translate.c index 87ba22d1b6..189b2ee3cb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8799,7 +8799,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D env_archcpu(env); - uint32_t tb_flags =3D dc->base.tb->flags; + CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(dc->base.tb); uint32_t condexec, core_mmu_idx; =20 dc->isar =3D &cpu->isar; @@ -9311,12 +9311,13 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb, int max_insns) { DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; + CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(tb); =20 - if (EX_TBFLAG_AM32(tb->flags, THUMB)) { + if (EX_TBFLAG_AM32(tb_flags, THUMB)) { ops =3D &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) { ops =3D &aarch64_translator_ops; } #endif --=20 2.25.1