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bh=ug6VeOhu1tQ4Kdbb2mf2+tuNKGgEI0pMs9tZg89YZ0w=; b=h7jf0bClOIKGKP0FRzPr6o/vd4lyvaDTQ0ZOMtTpcajRUIivSiGymJJnvetBEH2Zg+89xO LoHXVA/crHFQqUmEQ04ObITVOfyNzCDT09D+veI8g8EiR+jqKSFBV0PLoUo+2eN00QtYjo lwm2iJxj/GoN7p3RALuTA+E2Sqn4rcM= X-MC-Unique: rBshehE6PMq1wrkJa3XGfg-1 From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v3 3/5] s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x" Date: Mon, 11 Jan 2021 17:38:43 +0100 Message-Id: <20210111163845.18148-4-david@redhat.com> In-Reply-To: <20210111163845.18148-1-david@redhat.com> References: <20210111163845.18148-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Richard Henderson , Heiko Carstens , Cornelia Huck , Nick Desaulniers , Christian Borntraeger , qemu-s390x@nongnu.org, Guenter Roeck Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Using get_address() with register identifiers comming from an "r" field is wrong: if the "r" field designates "r0", we don't read the content and instead assume 0 - which should only be applied when the register was specified via "b" or "x". PoP 5-11 "Operand-Address Generation": "A zero in any of the B1, B2, X2, B3, or B4 fields indicates the absence of the corresponding address component. For the absent component, a zero is used in forming the intermediate sum, regardless of the contents of general register 0. A displacement of zero has no special significance." This BUG became visible for CSPG as generated by LLVM-12 in the upstream Linux kernel (v5.11-rc2), used while creating the linear mapping in vmem_map_init(): Trying to store to address 0 results in a Low Address Protection exception. Debugging this was more complicated than it could have been: The program interrupt handler in the kernel will try to crash the kernel: doing so, it will enable DAT. As the linear mapping is not created yet (asce=3D0), we run into an addressing exception while tring to walk non-existant DAT tables, resulting in a program exception loop. This allows for booting upstream Linux kernels compiled by clang-12. Most of these cases seem to be broken forever. Reported-by: Nick Desaulniers Reviewed-by: Richard Henderson Tested-by: Nick Desaulniers Tested-by: Guenter Roeck Cc: Guenter Roeck Cc: Christian Borntraeger Cc: Heiko Carstens Signed-off-by: David Hildenbrand --- target/s390x/insn-data.def | 8 ++++---- target/s390x/translate.c | 15 +++++++++------ 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index eac5136ee5..e5b6efabf3 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1290,8 +1290,8 @@ F(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0, IF_PRIV) F(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV) /* LOAD USING REAL ADDRESS */ - E(0xb24b, LURA, RRE, Z, 0, 0, new, r1_32, lura, 0, MO_TEUL, IF_= PRIV) - E(0xb905, LURAG, RRE, Z, 0, 0, r1, 0, lura, 0, MO_TEQ, IF_PRIV) + E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_TEUL, I= F_PRIV) + E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_TEQ, IF_PRIV) /* MOVE TO PRIMARY */ F(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0, IF_PRIV) /* MOVE TO SECONDARY */ @@ -1344,8 +1344,8 @@ /* STORE THEN OR SYSTEM MASK */ F(0xad00, STOSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV) /* STORE USING REAL ADDRESS */ - E(0xb246, STURA, RRE, Z, r1_o, 0, 0, 0, stura, 0, MO_TEUL, IF_PR= IV) - E(0xb925, STURG, RRE, Z, r1_o, 0, 0, 0, stura, 0, MO_TEQ, IF_PRI= V) + E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUL, IF_= PRIV) + E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEQ, IF_P= RIV) /* TEST BLOCK */ F(0xb22c, TB, RRE, Z, 0, r2_o, 0, 0, testblock, 0, IF_PRIV) /* TEST PROTECTION */ diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 39e33eeb67..61dd0341e4 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3285,8 +3285,7 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps= *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_lura(DisasContext *s, DisasOps *o) { - o->addr1 =3D get_address(s, 0, get_field(s, r2), 0); - tcg_gen_qemu_ld_tl(o->out, o->addr1, MMU_REAL_IDX, s->insn->data); + tcg_gen_qemu_ld_tl(o->out, o->in2, MMU_REAL_IDX, s->insn->data); return DISAS_NEXT; } #endif @@ -4234,7 +4233,8 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOp= s *o) tcg_gen_addi_i64(o->in1, regs[b1], d1); o->in2 =3D tcg_temp_new_i64(); tcg_gen_addi_i64(o->in2, regs[b2], d2); - o->addr1 =3D get_address(s, 0, r3, 0); + o->addr1 =3D tcg_temp_new_i64(); + gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0); =20 /* load the third operand into r3 before modifying anything */ tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s)); @@ -4539,8 +4539,7 @@ static DisasJumpType op_stnosm(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_stura(DisasContext *s, DisasOps *o) { - o->addr1 =3D get_address(s, 0, get_field(s, r2), 0); - tcg_gen_qemu_st_tl(o->in1, o->addr1, MMU_REAL_IDX, s->insn->data); + tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); =20 if (s->base.tb->flags & FLAG_MASK_PER) { update_psw_addr(s); @@ -5923,7 +5922,11 @@ static void in2_x2l(DisasContext *s, DisasOps *o) =20 static void in2_ra2(DisasContext *s, DisasOps *o) { - o->in2 =3D get_address(s, 0, get_field(s, r2), 0); + int r2 =3D get_field(s, r2); + + /* Note: *don't* treat !r2 as 0, use the reg value. */ + o->in2 =3D tcg_temp_new_i64(); + gen_addi_and_wrap_i64(s, o->in2, regs[r2], 0); } #define SPEC_in2_ra2 0 =20 --=20 2.29.2