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d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DeqTT9bQe601rNKQruQY32X1jef+Fy7gHPQ2b7isJy4=; b=a8to+ayE8SnCMNluZt6xwWut47ofmxon3h4ctee96RrEcGx61wtbuvXYktvefngGe0 S0vN8bPAyyfM5eiWw8lFRd5kmxdAZEWs/kyZzVGlzSVb9XTR0k4NXgr7pD8HrMbsg/tO QZg+GJIwDwNtaQRTjnKKB6Gd050PL/EbI2THKr9DMM1uKA+4NrJaH+15GvHX/PIGsDP1 NvP/tEck0ei3q0ZIgQz/ZWCq3mh7O5jnKfr5wwXFOx4MfOcR3MR3lXjkZ9LfopQ7GXgX ZcumEFRiedZt4A/5waYUaL1bnHlLXvcPxxTd0IQz0T2GK47Z+ATzD3ut76Z4iqxZyaon gLZw== X-Gm-Message-State: AOAM53340mFf+4Nu9t4/L4fxwlWX7KNcGkD0SCL88WHnxJMo56oH8RUx 6WkguwZfu7yb12yqxWUzWlg= X-Google-Smtp-Source: ABdhPJwXFzM3ElJbn3Phkz1nf1Bm39YR6rdNCCWFZ5kzxcJB6GnKoUsPhjg7kRi2Ezk+YIGitqevqQ== X-Received: by 2002:ac2:43bb:: with SMTP id t27mr5525107lfl.93.1610304683333; Sun, 10 Jan 2021 10:51:23 -0800 (PST) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v7 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Date: Sun, 10 Jan 2021 21:51:08 +0300 Message-Id: <20210110185109.29841-6-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210110185109.29841-1-space.monkey.delivers@gmail.com> References: <20210110185109.29841-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 19 +++++++++++++++++++ target/riscv/translate.c | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 37ea7f7802..b3c63ca5ff 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -397,6 +397,7 @@ FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, PM_ENABLED, 10, 1) =20 bool riscv_cpu_is_32bit(CPURISCVState *env); =20 @@ -454,6 +455,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } } + if (riscv_has_ext(env, RVJ)) { + int priv =3D cpu_mmu_index(env, false); + bool pm_enabled =3D false; + switch (priv) { + case PRV_U: + pm_enabled =3D env->mmte & U_PM_ENABLE; + break; + case PRV_S: + pm_enabled =3D env->mmte & S_PM_ENABLE; + break; + case PRV_M: + pm_enabled =3D env->mmte & M_PM_ENABLE; + break; + default: + g_assert_not_reached(); + } + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); + } #endif =20 *pflags =3D flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5da7330f33..980604935d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; +/* globals for PM CSRs */ +static TCGv pm_mask[4]; +static TCGv pm_base[4]; =20 #include "exec/gen-icount.h" =20 @@ -64,6 +67,10 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + /* PointerMasking extension */ + bool pm_enabled; + TCGv pm_mask; + TCGv pm_base; } DisasContext; =20 #ifdef TARGET_RISCV64 @@ -103,13 +110,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) } =20 /* - * Temp stub: generates address adjustment for PointerMasking + * Generates address adjustment for PointerMasking */ static void gen_pm_adjust_address(DisasContext *s, TCGv_i64 dst, TCGv_i64 src) { - tcg_gen_mov_i64(dst, src); + if (!s->pm_enabled) { + /* Load unmodified address */ + tcg_gen_mov_i64(dst, src); + } else { + tcg_gen_andc_i64(dst, src, s->pm_mask); + tcg_gen_or_i64(dst, dst, s->pm_base); + } } =20 /* @@ -828,6 +841,10 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + int priv =3D cpu_mmu_index(env, false); + ctx->pm_mask =3D pm_mask[priv]; + ctx->pm_base =3D pm_base[priv]; } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -947,4 +964,17 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); + /* Assign PM CSRs to tcg globals */ + pm_mask[PRV_U] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmma= sk"); + pm_base[PRV_U] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmba= se"); + pm_mask[PRV_S] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmma= sk"); + pm_base[PRV_S] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmba= se"); + pm_mask[PRV_M] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmma= sk"); + pm_base[PRV_M] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmba= se"); } --=20 2.20.1