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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id j2sm18627240wrt.35.2021.01.09.15.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 15:34:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=EQmWTMNEnmOXFRLXHxzUIYYQ8gDqL9FEvBCfnJalq6c=; b=U14EFcDqfKNPTVzEWQiJvs5ZLPzpx9rLgs5NfW2Eg53PO/dDedUXnTwm0An/9NQlvv pV+n93jyHYYhDP6ygOSupW5BJyOKvXVJ1b7X4FC/tGfR2EoQDoN+0twxETw7zgZKsU+/ T3THWKPux18GoyEIuGlPA3+1ZTiFV/ICaHN4/JYo903xprYQ/RXKvAX8XNyVzoXBypff EIvdox0xqe+hlypgccSsN53T7pdugT81ji9o3hxDslXPdxdALT/KY+s+c/4eXMBVSqH3 +jOKGa/0v4r8CE6uD6ss1xjaQqX+20dls1xk4B6Ltj/3FYkQZ9eM0k9uE7iKHn9I5Zox JI4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=EQmWTMNEnmOXFRLXHxzUIYYQ8gDqL9FEvBCfnJalq6c=; b=FoqCZSniQDuvucxm1LaVr53QLI0L4xV98QCOqEQKCBsazOjjiA/SoMV9wZLZrpDfIu W0zCg/rMk2CCMdGMTtCNHlPsjw0kOCB0qgFir4fT1RjbhbZovHcxr1URxvDk6gjMD/kz SXSCTXRTxyD3vfqWb4Id6GN05Fm+6JUXBAaw4sHSP9eR8JhrqKTmAyqvAVgy2w/ZFPL5 f4/CMhVpb3GTJ2RdDFk5MXRXYcNlFECISz/+5+hqEkQ075n3jKa3ocYiecaGYd9MEVUw 8HbIKNGUBYNjJcWQBL3eckWOmoaeH+5x0WMM6y4hcTg/g5RT1W0TYtqg5C2JUlTc9P9z 1VXQ== X-Gm-Message-State: AOAM531Dtr3eTv4x9eTE0shyqkPNXvMxgWZmGQKrXMsvFshnxMDF0Pvu Dl7Nepj49hFVucYdygkfog0= X-Google-Smtp-Source: ABdhPJypgxDLZgSKmXiyD2xpt4/sj1QhW08frsyAEhyzAefeItPed9+B3b3kqcvIsushFPWnrYlQ5Q== X-Received: by 2002:a1c:99d7:: with SMTP id b206mr8864753wme.12.1610235270090; Sat, 09 Jan 2021 15:34:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] target/i386: Use X86Seg enum for segment registers Date: Sun, 10 Jan 2021 00:34:27 +0100 Message-Id: <20210109233427.749748-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the dedicated X86Seg enum type for segment registers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/cpu.h | 4 ++-- target/i386/gdbstub.c | 2 +- target/i386/tcg/seg_helper.c | 8 ++++---- target/i386/tcg/translate.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index af130512e22..d23a5b340a8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1807,7 +1807,7 @@ void cpu_sync_bndcs_hflags(CPUX86State *env); /* this function must always be used to load data in the segment cache: it synchronizes the hflags with the segment cache values */ static inline void cpu_x86_load_seg_cache(CPUX86State *env, - int seg_reg, unsigned int select= or, + X86Seg seg_reg, unsigned int sel= ector, target_ulong base, unsigned int limit, unsigned int flags) @@ -1896,7 +1896,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigne= d int selector, /* cpu-exec.c */ /* the following helpers are only usable in user mode simulation as they can trigger unexpected exceptions */ -void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); +void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 4a3de5f69da..41e265fc67a 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -232,7 +232,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 -static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf) +static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf) { CPUX86State *env =3D &cpu->env; uint16_t selector =3D ldl_p(mem_buf); diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 5f2ee6aa7ea..180d47f0e9b 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -176,8 +176,8 @@ static inline void get_ss_esp_from_tss(CPUX86State *env= , uint32_t *ss_ptr, } } =20 -static void tss_load_seg(CPUX86State *env, int seg_reg, int selector, int = cpl, - uintptr_t retaddr) +static void tss_load_seg(CPUX86State *env, X86Seg seg_reg, int selector, + int cpl, uintptr_t retaddr) { uint32_t e1, e2; int rpl, dpl; @@ -2098,7 +2098,7 @@ void helper_iret_real(CPUX86State *env, int shift) env->hflags2 &=3D ~HF2_NMI_MASK; } =20 -static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl) +static inline void validate_seg(CPUX86State *env, X86Seg seg_reg, int cpl) { int dpl; uint32_t e2; @@ -2623,7 +2623,7 @@ void helper_verw(CPUX86State *env, target_ulong selec= tor1) } =20 #if defined(CONFIG_USER_ONLY) -void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector) +void cpu_x86_load_seg(CPUX86State *env, X86Seg seg_reg, int selector) { if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { int dpl =3D (env->eflags & VM_MASK) ? 3 : 0; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 11db2f3c8d2..6a4c31f933b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2287,13 +2287,13 @@ static void gen_cmovcc1(CPUX86State *env, DisasCont= ext *s, MemOp ot, int b, } } =20 -static inline void gen_op_movl_T0_seg(DisasContext *s, int seg_reg) +static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg) { tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State,segs[seg_reg].selector)); } =20 -static inline void gen_op_movl_seg_T0_vm(DisasContext *s, int seg_reg) +static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) { tcg_gen_ext16u_tl(s->T0, s->T0); tcg_gen_st32_tl(s->T0, cpu_env, @@ -2303,7 +2303,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext= *s, int seg_reg) =20 /* move T0 to seg_reg and compute if the CPU state may change. Never call this function with seg_reg =3D=3D R_CS */ -static void gen_movl_seg_T0(DisasContext *s, int seg_reg) +static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) { if (s->pe && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); --=20 2.26.2