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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v1sm13540456wrr.48.2021.01.08.09.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 09:12:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wuOEdc6sJv7210rqPS2JK6djR5iIRiMSjHWOe1yhw6I=; b=iq/z28TGKPlHHJ7lI0bppy+1UZkMJSfm8Zqr9u5FJT3qmclrRUiRQA5XNT7/J18/j4 TJMVxiCVaNlv+z+QqS1BK7D99+6d5mnu1tFtUmkeB6jGKmnc7JPfA7B+ewQSeD2di2ZE 8B9wvtWTaa7tY9chHQ0PGRwEpDmu8kDoWLBB1Wot0eO551Jqlqr0v1l5cYpE0IUGaouW SIqjvNjeRhw/PXjDcCU5m6VjHsy2l4yCjtAqJk7N3I4buj3GDKiegipigCCBcF5EM4g7 JyFb9wvXI2rrX5AgSXW8nbw9FsCipchOC++9sD00wQHz24v9tyBAV3md5mQO59WThBsA fBJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wuOEdc6sJv7210rqPS2JK6djR5iIRiMSjHWOe1yhw6I=; b=a8NC/HltszRpYCV6IAyjsTzrpB4YO+HYHTnnqEKVTOFucf1/O/ZMiGL/Uwn+Nbfbfg j38oIqcYzLBwsMIAp2F30y5Jd9PE1QrUdBBJZl3LsZQlE7zhaDzCXbcX7THL6Vxg+Sef i4C7lsTvj5n2wxGNXTMeInvdbgAx1lb2zBzTabq74WFVl7KCZ/z0RfPtNPP1ojAyU6lT DulIIveWR50vSAPm7+rpvOXGmOOk59TplIQAN9C+eS2mAUpgR1h5IfKkr05yvvczDrYo S2AGmmtnhzPVzWfLVUF7G/a1FZIM7gWtxULSzG34+dvwLwm9SMOcWrPQzjcHSVMcgzBH Is6Q== X-Gm-Message-State: AOAM531R3Qwj2hjRGwz/Ay7DuG1pLosRwPslI6ailMSUQE/uu8j5FwgW zWDlUcSJhZWK/oPabPFHmlSudzCnvsEuAg== X-Google-Smtp-Source: ABdhPJziA0qEPZfgaAy99tNw/Xwf3255/Rr995PKi6rokuwVvLCjPO5ekKbKriHKYFTz2DZc+p0ijw== X-Received: by 2002:adf:dd09:: with SMTP id a9mr4598396wrm.90.1610125936329; Fri, 08 Jan 2021 09:12:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 1/4] hw/ppc/sam460ex: Drop use of ppcuic_init() Date: Fri, 8 Jan 2021 17:12:09 +0000 Message-Id: <20210108171212.16500-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108171212.16500-1-peter.maydell@linaro.org> References: <20210108171212.16500-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the sam460ex board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. Signed-off-by: Peter Maydell Reviewed-by: BALATON Zoltan --- v1->v2 changes: * fix typo in UIC 0 CINT wiring * move local var declarations up * drop unnecessary TODO comment * improve comment about what the input_ints[] array is doing --- hw/ppc/sam460ex.c | 69 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 53 insertions(+), 16 deletions(-) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 14e6583eb0d..45721ad6c73 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -39,6 +39,7 @@ #include "hw/usb/hcd-ehci.h" #include "hw/ppc/fdt.h" #include "hw/qdev-properties.h" +#include "hw/intc/ppc-uic.h" =20 #include =20 @@ -281,7 +282,9 @@ static void sam460ex_init(MachineState *machine) hwaddr ram_bases[SDRAM_NR_BANKS] =3D {0}; hwaddr ram_sizes[SDRAM_NR_BANKS] =3D {0}; MemoryRegion *l2cache_ram =3D g_new(MemoryRegion, 1); - qemu_irq *irqs, *uic[4]; + DeviceState *uic[4]; + qemu_irq mal_irqs[4]; + int i; PCIBus *pci_bus; PowerPCCPU *cpu; CPUPPCState *env; @@ -312,13 +315,38 @@ static void sam460ex_init(MachineState *machine) ppc4xx_plb_init(env); =20 /* interrupt controllers */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT= _INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPU= T_CINT]; - uic[0] =3D ppcuic_init(env, irqs, 0xc0, 0, 1); - uic[1] =3D ppcuic_init(env, &uic[0][30], 0xd0, 0, 1); - uic[2] =3D ppcuic_init(env, &uic[0][10], 0xe0, 0, 1); - uic[3] =3D ppcuic_init(env, &uic[0][16], 0xf0, 0, 1); + for (i =3D 0; i < ARRAY_SIZE(uic); i++) { + SysBusDevice *sbd; + /* + * UICs 1, 2 and 3 are cascaded through UIC 0. + * input_ints[n] is the interrupt number on UIC 0 which + * the INT output of UIC n is connected to. The CINT output + * of UIC n connects to input_ints[n] + 1. + * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's + * INT and CINT outputs are connected to the CPU. + */ + const int input_ints[] =3D { -1, 30, 10, 16 }; + + uic[i] =3D qdev_new(TYPE_PPC_UIC); + sbd =3D SYS_BUS_DEVICE(uic[i]); + + qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); + object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(sbd, &error_fatal); + + if (i =3D=3D 0) { + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_= INT]); + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_= CINT]); + } else { + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + qdev_get_gpio_in(uic[0], input_ints[i])); + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, + qdev_get_gpio_in(uic[0], input_ints[i] + 1)= ); + } + } =20 /* SDRAM controller */ /* put all RAM on first bank because board has one slot @@ -331,7 +359,8 @@ static void sam460ex_init(MachineState *machine) ram_bases, ram_sizes, 1); =20 /* IIC controllers and devices */ - dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]); + dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, + qdev_get_gpio_in(uic[0], 2)); i2c =3D PPC4xx_I2C(dev)->bus; /* SPD EEPROM on RAM module */ spd_data =3D spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2, @@ -341,7 +370,8 @@ static void sam460ex_init(MachineState *machine) /* RTC */ i2c_slave_create_simple(i2c, "m41t80", 0x68); =20 - dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]); + dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, + qdev_get_gpio_in(uic[0], 3)); =20 /* External bus controller */ ppc405_ebc_init(env); @@ -356,7 +386,10 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdr_init(env); =20 /* MAL */ - ppc4xx_mal_init(env, 4, 16, &uic[2][3]); + for (i =3D 0; i < ARRAY_SIZE(mal_irqs); i++) { + mal_irqs[0] =3D qdev_get_gpio_in(uic[2], 3 + i); + } + ppc4xx_mal_init(env, 4, 16, mal_irqs); =20 /* DMA */ ppc4xx_dma_init(env, 0x200); @@ -369,21 +402,23 @@ static void sam460ex_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_= ram); =20 /* USB */ - sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]); + sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, + qdev_get_gpio_in(uic[2], 29)); dev =3D qdev_new("sysbus-ohci"); qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); qdev_prop_set_uint32(dev, "num-ports", 6); sbdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sbdev, &error_fatal); sysbus_mmio_map(sbdev, 0, 0x4bffd0000); - sysbus_connect_irq(sbdev, 0, uic[2][30]); + sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); usb_create_simple(usb_bus_find(-1), "usb-kbd"); usb_create_simple(usb_bus_find(-1), "usb-mouse"); =20 /* PCI bus */ ppc460ex_pcie_init(env); /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ - dev =3D sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0= ]); + dev =3D sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, + qdev_get_gpio_in(uic[1], 0)); pci_bus =3D (PCIBus *)qdev_get_child_bus(dev, "pci.0"); if (!pci_bus) { error_report("couldn't create PCI controller!"); @@ -405,12 +440,14 @@ static void sam460ex_init(MachineState *machine) /* SoC has 4 UARTs * but board has only one wired and two are present in fdt */ if (serial_hd(0) !=3D NULL) { - serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1], + serial_mm_init(address_space_mem, 0x4ef600300, 0, + qdev_get_gpio_in(uic[1], 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) !=3D NULL) { - serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1], + serial_mm_init(address_space_mem, 0x4ef600400, 0, + qdev_get_gpio_in(uic[0], 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } --=20 2.20.1 From nobody Fri May 17 07:07:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610126089; cv=none; d=zohomail.com; s=zohoarc; b=SMPmlyKiq8wBra65+xsDj65sPM7/tDrQNiDlSjHbcWMKQyxrTNMLIfiEFLDTue/HsWwfHXg41KSpNRTgrPzV+3wYeK62yxOQ/CP7SOZGR4bJHq8FWHgEiWXFuj5it7iby44yQMiGdKf5way67N0wMxbSrNoY40pKTPl5Y6AjHK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610126089; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E3wLZ5ZQgEBY3BL5WGa0zC+m36hgQAMvpdbWNLUcHrw=; b=keRMCT1bG6Oh+NLfaZ3maCybOi8STpUqgnMOFJyf8wBycIYh+tLOnKMZGU5LY3+jPDDzGNY/z78jf5rVj9GUl2AwT5/7mf3a054cG34CdJqcGLi/xygjVjrTl1UfdQUezajsxbVhWnCLLO8q/4HBpPNG4E5GekZh5X/8cukXX20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610126089226989.5354513705297; Fri, 8 Jan 2021 09:14:49 -0800 (PST) Received: from localhost ([::1]:40984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kxvLb-0003FZ-Vm for importer@patchew.org; Fri, 08 Jan 2021 12:14:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxvJW-0000b0-Oq for qemu-devel@nongnu.org; Fri, 08 Jan 2021 12:12:39 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:46789) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxvJF-0004sd-2P for qemu-devel@nongnu.org; Fri, 08 Jan 2021 12:12:35 -0500 Received: by mail-wr1-x42e.google.com with SMTP id d13so9656765wrc.13 for ; Fri, 08 Jan 2021 09:12:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v1sm13540456wrr.48.2021.01.08.09.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 09:12:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E3wLZ5ZQgEBY3BL5WGa0zC+m36hgQAMvpdbWNLUcHrw=; b=V0G9wM/6lZGIBU98HR7IZk1iSi5i2x3gfU9Y+zINP7D29/XWgmUoX9NztYQAGLmh1R uWATs6pcTcvvMksJJ2Y6IzrlQz7NJAUkMK/F0+mverBPRDdwq1UzJBEiy38AGhy4HjDg Hg7f0G6VBStPkAKnOOYlLkeWP2i6/1R0IIiV7uQe1DBsqE6IsB9l7rwqiohmSh0Lt0Hv ZjRBbXjcisBZdbTLQwFFvuk5iRAujGBzT8+u3sI4PZRNMEeiKLMCAU2giwFYeMz8AZ2f m7C+01FfYdgvDObilhDAqkcwu7+4GUF9MqTT54YIav97o5rS5kYeiHjxFIyiOVZYL+M3 ujfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E3wLZ5ZQgEBY3BL5WGa0zC+m36hgQAMvpdbWNLUcHrw=; b=AJiB+rowikE8+PM8PZG9P1cWl8e0vEid9e4vJkkGJm2JkVEDt64BYpwy48fE8k8XwO nEN9T2Xd8hAT6DqPdtvQnmRwUaJ1RykWCef3YlRvvIyiRz8ovYAtwA5fgL23t8xPoKNw 1PzaMs9dm0YMUTT+dGH+aWnxXH/nJVk1zxKM16atrnwsI/UuTys1Dv25rbHD4Oe5LOyr Bino7LtJoedkt4CCMd2zmseJhgBt45GjDN1ESicAmEe4QEe/cIhhNmLC0Z+5joNouRxS Xr9N7uPfff0tjkB28kWk+6tc2ifg1x6iZS0cTNZEax8xXbaGoYdr4ebNw75QMb3pH5Xp LcSg== X-Gm-Message-State: AOAM530pxfnds+y8aeyiBIVAXiaU8vJiPkNlLZF+qXCUA6Z9VRT+sguB j12TyMJzWgd+cXVcUxoqKN750yAtjA0Leg== X-Google-Smtp-Source: ABdhPJz6J1xjG8i2eZvuYPccR/Yk1AedWp136gIseRPhuMsmhEbnROQoYX7haYdpaAqGtDv0XfI1cA== X-Received: by 2002:adf:a201:: with SMTP id p1mr4619555wra.65.1610125937526; Fri, 08 Jan 2021 09:12:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 2/4] hw/ppc: Delete unused ppc405cr_init() code Date: Fri, 8 Jan 2021 17:12:10 +0000 Message-Id: <20210108171212.16500-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108171212.16500-1-peter.maydell@linaro.org> References: <20210108171212.16500-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The function ppc405cr_init() has apparently been unused since it was added in commit 8ecc7913525ecb in 2007. Remove this dead code, so we don't have to convert it away from using ppcuic_init(). Signed-off-by: Peter Maydell --- hw/ppc/ppc405.h | 6 - hw/ppc/ppc405_uc.c | 345 --------------------------------------------- 2 files changed, 351 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 7ed25cfa1bf..e6c702f7e0d 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -62,12 +62,6 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx= _bd_info_t *bd, void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); =20 -CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, - MemoryRegion ram_memories[4], - hwaddr ram_bases[4], - hwaddr ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init); CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 381720aced9..3e191ae4af5 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1155,351 +1155,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq i= rqs[5]) qemu_register_reset(ppc4xx_gpt_reset, gpt); } =20 -/*************************************************************************= ****/ -/* PowerPC 405CR */ -enum { - PPC405CR_CPC0_PLLMR =3D 0x0B0, - PPC405CR_CPC0_CR0 =3D 0x0B1, - PPC405CR_CPC0_CR1 =3D 0x0B2, - PPC405CR_CPC0_PSR =3D 0x0B4, - PPC405CR_CPC0_JTAGID =3D 0x0B5, - PPC405CR_CPC0_ER =3D 0x0B9, - PPC405CR_CPC0_FR =3D 0x0BA, - PPC405CR_CPC0_SR =3D 0x0BB, -}; - -enum { - PPC405CR_CPU_CLK =3D 0, - PPC405CR_TMR_CLK =3D 1, - PPC405CR_PLB_CLK =3D 2, - PPC405CR_SDRAM_CLK =3D 3, - PPC405CR_OPB_CLK =3D 4, - PPC405CR_EXT_CLK =3D 5, - PPC405CR_UART_CLK =3D 6, - PPC405CR_CLK_NB =3D 7, -}; - -typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; -struct ppc405cr_cpc_t { - clk_setup_t clk_setup[PPC405CR_CLK_NB]; - uint32_t sysclk; - uint32_t psr; - uint32_t cr0; - uint32_t cr1; - uint32_t jtagid; - uint32_t pllmr; - uint32_t er; - uint32_t fr; -}; - -static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) -{ - uint64_t VCO_out, PLL_out; - uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_= clk; - int M, D0, D1, D2; - - D0 =3D ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ - if (cpc->pllmr & 0x80000000) { - D1 =3D (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ - D2 =3D 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ - M =3D D0 * D1 * D2; - VCO_out =3D (uint64_t)cpc->sysclk * M; - if (VCO_out < 400000000 || VCO_out > 800000000) { - /* PLL cannot lock */ - cpc->pllmr &=3D ~0x80000000; - goto bypass_pll; - } - PLL_out =3D VCO_out / D2; - } else { - /* Bypass PLL */ - bypass_pll: - M =3D D0; - PLL_out =3D (uint64_t)cpc->sysclk * M; - } - CPU_clk =3D PLL_out; - if (cpc->cr1 & 0x00800000) - TMR_clk =3D cpc->sysclk; /* Should have a separate clock */ - else - TMR_clk =3D CPU_clk; - PLB_clk =3D CPU_clk / D0; - SDRAM_clk =3D PLB_clk; - D0 =3D ((cpc->pllmr >> 10) & 0x3) + 1; - OPB_clk =3D PLB_clk / D0; - D0 =3D ((cpc->pllmr >> 24) & 0x3) + 2; - EXT_clk =3D PLB_clk / D0; - D0 =3D ((cpc->cr0 >> 1) & 0x1F) + 1; - UART_clk =3D CPU_clk / D0; - /* Setup CPU clocks */ - clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); - /* Setup time-base clock */ - clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); - /* Setup PLB clock */ - clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); - /* Setup SDRAM clock */ - clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); - /* Setup OPB clock */ - clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); - /* Setup external clock */ - clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); - /* Setup UART clock */ - clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); -} - -static uint32_t dcr_read_crcpc (void *opaque, int dcrn) -{ - ppc405cr_cpc_t *cpc; - uint32_t ret; - - cpc =3D opaque; - switch (dcrn) { - case PPC405CR_CPC0_PLLMR: - ret =3D cpc->pllmr; - break; - case PPC405CR_CPC0_CR0: - ret =3D cpc->cr0; - break; - case PPC405CR_CPC0_CR1: - ret =3D cpc->cr1; - break; - case PPC405CR_CPC0_PSR: - ret =3D cpc->psr; - break; - case PPC405CR_CPC0_JTAGID: - ret =3D cpc->jtagid; - break; - case PPC405CR_CPC0_ER: - ret =3D cpc->er; - break; - case PPC405CR_CPC0_FR: - ret =3D cpc->fr; - break; - case PPC405CR_CPC0_SR: - ret =3D ~(cpc->er | cpc->fr) & 0xFFFF0000; - break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; - } - - return ret; -} - -static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) -{ - ppc405cr_cpc_t *cpc; - - cpc =3D opaque; - switch (dcrn) { - case PPC405CR_CPC0_PLLMR: - cpc->pllmr =3D val & 0xFFF77C3F; - break; - case PPC405CR_CPC0_CR0: - cpc->cr0 =3D val & 0x0FFFFFFE; - break; - case PPC405CR_CPC0_CR1: - cpc->cr1 =3D val & 0x00800000; - break; - case PPC405CR_CPC0_PSR: - /* Read-only */ - break; - case PPC405CR_CPC0_JTAGID: - /* Read-only */ - break; - case PPC405CR_CPC0_ER: - cpc->er =3D val & 0xBFFC0000; - break; - case PPC405CR_CPC0_FR: - cpc->fr =3D val & 0xBFFC0000; - break; - case PPC405CR_CPC0_SR: - /* Read-only */ - break; - } -} - -static void ppc405cr_cpc_reset (void *opaque) -{ - ppc405cr_cpc_t *cpc; - int D; - - cpc =3D opaque; - /* Compute PLLMR value from PSR settings */ - cpc->pllmr =3D 0x80000000; - /* PFWD */ - switch ((cpc->psr >> 30) & 3) { - case 0: - /* Bypass */ - cpc->pllmr &=3D ~0x80000000; - break; - case 1: - /* Divide by 3 */ - cpc->pllmr |=3D 5 << 16; - break; - case 2: - /* Divide by 4 */ - cpc->pllmr |=3D 4 << 16; - break; - case 3: - /* Divide by 6 */ - cpc->pllmr |=3D 2 << 16; - break; - } - /* PFBD */ - D =3D (cpc->psr >> 28) & 3; - cpc->pllmr |=3D (D + 1) << 20; - /* PT */ - D =3D (cpc->psr >> 25) & 7; - switch (D) { - case 0x2: - cpc->pllmr |=3D 0x13; - break; - case 0x4: - cpc->pllmr |=3D 0x15; - break; - case 0x5: - cpc->pllmr |=3D 0x16; - break; - default: - break; - } - /* PDC */ - D =3D (cpc->psr >> 23) & 3; - cpc->pllmr |=3D D << 26; - /* ODP */ - D =3D (cpc->psr >> 21) & 3; - cpc->pllmr |=3D D << 10; - /* EBPD */ - D =3D (cpc->psr >> 17) & 3; - cpc->pllmr |=3D D << 24; - cpc->cr0 =3D 0x0000003C; - cpc->cr1 =3D 0x2B0D8800; - cpc->er =3D 0x00000000; - cpc->fr =3D 0x00000000; - ppc405cr_clk_setup(cpc); -} - -static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) -{ - int D; - - /* XXX: this should be read from IO pins */ - cpc->psr =3D 0x00000000; /* 8 bits ROM */ - /* PFWD */ - D =3D 0x2; /* Divide by 4 */ - cpc->psr |=3D D << 30; - /* PFBD */ - D =3D 0x1; /* Divide by 2 */ - cpc->psr |=3D D << 28; - /* PDC */ - D =3D 0x1; /* Divide by 2 */ - cpc->psr |=3D D << 23; - /* PT */ - D =3D 0x5; /* M =3D 16 */ - cpc->psr |=3D D << 25; - /* ODP */ - D =3D 0x1; /* Divide by 2 */ - cpc->psr |=3D D << 21; - /* EBDP */ - D =3D 0x2; /* Divide by 4 */ - cpc->psr |=3D D << 17; -} - -static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], - uint32_t sysclk) -{ - ppc405cr_cpc_t *cpc; - - cpc =3D g_malloc0(sizeof(ppc405cr_cpc_t)); - memcpy(cpc->clk_setup, clk_setup, - PPC405CR_CLK_NB * sizeof(clk_setup_t)); - cpc->sysclk =3D sysclk; - cpc->jtagid =3D 0x42051049; - ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc405cr_clk_init(cpc); - qemu_register_reset(ppc405cr_cpc_reset, cpc); -} - -CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, - MemoryRegion ram_memories[4], - hwaddr ram_bases[4], - hwaddr ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init) -{ - clk_setup_t clk_setup[PPC405CR_CLK_NB]; - qemu_irq dma_irqs[4]; - PowerPCCPU *cpu; - CPUPPCState *env; - qemu_irq *pic, *irqs; - - memset(clk_setup, 0, sizeof(clk_setup)); - cpu =3D ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"), - &clk_setup[PPC405CR_CPU_CLK], - &clk_setup[PPC405CR_TMR_CLK], sysclk); - env =3D &cpu->env; - /* Memory mapped devices registers */ - /* PLB arbitrer */ - ppc4xx_plb_init(env); - /* PLB to OPB bridge */ - ppc4xx_pob_init(env); - /* OBP arbitrer */ - ppc4xx_opba_init(0xef600600); - /* Universal interrupt controller */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic =3D ppcuic_init(env, irqs, 0x0C0, 0, 1); - *picp =3D pic; - /* SDRAM controller */ - ppc4xx_sdram_init(env, pic[14], 1, ram_memories, - ram_bases, ram_sizes, do_init); - /* External bus controller */ - ppc405_ebc_init(env); - /* DMA controller */ - dma_irqs[0] =3D pic[26]; - dma_irqs[1] =3D pic[25]; - dma_irqs[2] =3D pic[24]; - dma_irqs[3] =3D pic[23]; - ppc405_dma_init(env, dma_irqs); - /* Serial ports */ - if (serial_hd(0) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hd(0), - DEVICE_BIG_ENDIAN); - } - if (serial_hd(1) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hd(1), - DEVICE_BIG_ENDIAN); - } - /* IIC controller */ - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); - /* GPIO */ - ppc405_gpio_init(0xef600700); - /* CPU control */ - ppc405cr_cpc_init(env, clk_setup, sysclk); - - return env; -} - /*************************************************************************= ****/ /* PowerPC 405EP */ /* CPU control */ --=20 2.20.1 From nobody Fri May 17 07:07:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610126588; cv=none; d=zohomail.com; s=zohoarc; b=ZE/XPnfohfDLNp+tQggQWHV3yLHGtcHlxOJPT/W51EtYubwY+hZLqAovYvLItodUtLfTCK0Km2zxnQE42c9hoC3/bS36uOu9EIR3Mou1MgMY9zv+PHkrHimOvSbgwXU4btQbzIjQokyo26n5b/zKwMa8KgbD1bAx2mn0y6GqQ/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v1sm13540456wrr.48.2021.01.08.09.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 09:12:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9vrnHXTMsZjfdHKV6SCdqqT25waiXTd0JncR/beyVqQ=; b=QHMsg99GgDV2FyJefgaixvLG+3Ypu/C0bFrAC7sIG7NhIgidMpRO9UCAtg3Ud4RSzH Cbh7DupmbF7iYyNlcfiC0wLrJoHc/ZkBifsbvWuGAZkPg16etLwgvPnNtimDi4QjPe4q i75jUl6kEUhdVFsxL9dRvTktQU+w3+5l6NMQtERPz03+TJl8W/0+X+E7t5/NFV4a3zTU 1MDPAFGbGaKyydOYHO5zPtiqtkDVtcIULbOHCPGnWls3OnOG087v3eZIdP+GS6ygtLfG Ii9p4xzwZ8EwL+CrEuaZr2RFCsPbVnG2Vn2qpAtElNiFEqnILExHCm94ncIj8kIjsGMG 2/fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9vrnHXTMsZjfdHKV6SCdqqT25waiXTd0JncR/beyVqQ=; b=m68fZUKU9kd/IZ3nrXRWeUGULTq/EHESvzuQ+tZ2VD4QYWTA3DGVbZ9C3WZogfy45i WUsoTEpD3Awc9K64Ohw0uE3aMoNtSN3H09L9q+M7k6d9y/aOybn8/Ai0kIdkG3zCfCAP ZhkIVqKmPuIKWihqECV31A/BA+ISRFC0YRLZYukfo33t06Y2CpsrKJhO+SSC291KCmtb xmyx5hT4Xs7zvkJ6qAaUj3gDYsg+n0CMLZ4flr4oyY0o+QJ6VsErI6Bps1X08UZjLAI2 OXqNfVpUOnDaVPR8Jl9kARJGYZb46k7gJGx/HuD9x9MDjOF+CsmFn3pRaV3ZQBOIeP9X Qz/g== X-Gm-Message-State: AOAM530ju98GxKdbL3PRzkdaVzsrKPoQwO+Kt058SqQM72VD/ynNavp+ WCE5N5GNGYXPL2fqh8NiketMF5GpwW7u5Q== X-Google-Smtp-Source: ABdhPJxuDI19HV/AHzCdjEroU77lLE2H8QZwsYlev9W5AET8ZhCjIK9Wc3Aiv0oST8ZoCr21dbIxTA== X-Received: by 2002:a5d:674c:: with SMTP id l12mr4548899wrw.399.1610125938937; Fri, 08 Jan 2021 09:12:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 3/4] hw/ppc/ppc405_uc: Drop use of ppcuic_init() Date: Fri, 8 Jan 2021 17:12:11 +0000 Message-Id: <20210108171212.16500-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108171212.16500-1-peter.maydell@linaro.org> References: <20210108171212.16500-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the ppc405_uc boards to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. We retain the API feature of ppc405ep_init() where it passes back something allowing the callers to wire up devices to the UIC if they need to, even though neither of the callsites currently makes use of this ability -- instead of passing back the qemu_irq array we pass back the UIC DeviceState. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 8 ++--- hw/ppc/ppc405_uc.c | 70 +++++++++++++++++++++++++----------------- 3 files changed, 47 insertions(+), 33 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index e6c702f7e0d..c58f739886a 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -66,7 +66,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_me= m, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, + uint32_t sysclk, DeviceState **uicdev, int do_init); =20 #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index b7249f21cf2..8f77887fb18 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -151,7 +151,6 @@ static void ref405ep_init(MachineState *machine) CPUPPCState *env; DeviceState *dev; SysBusDevice *s; - qemu_irq *pic; MemoryRegion *bios; MemoryRegion *sram =3D g_new(MemoryRegion, 1); ram_addr_t bdloc; @@ -167,6 +166,7 @@ static void ref405ep_init(MachineState *machine) int len; DriveInfo *dinfo; MemoryRegion *sysmem =3D get_system_memory(); + DeviceState *uicdev; =20 if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); @@ -184,7 +184,7 @@ static void ref405ep_init(MachineState *machine) ram_bases[1] =3D 0x00000000; ram_sizes[1] =3D 0x00000000; env =3D ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, - 33333333, &pic, kernel_filename =3D=3D NULL ? 0 : = 1); + 33333333, &uicdev, kernel_filename =3D=3D NULL ? 0= : 1); /* allocate SRAM */ sram_size =3D 512 * KiB; memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, @@ -429,7 +429,6 @@ static void taihu_405ep_init(MachineState *machine) const char *kernel_filename =3D machine->kernel_filename; const char *initrd_filename =3D machine->initrd_filename; char *filename; - qemu_irq *pic; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *bios; MemoryRegion *ram_memories =3D g_new(MemoryRegion, 2); @@ -440,6 +439,7 @@ static void taihu_405ep_init(MachineState *machine) int linux_boot; int fl_idx; DriveInfo *dinfo; + DeviceState *uicdev; =20 if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); @@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine) "taihu_405ep.ram-1", machine->ram, ram_bases[= 1], ram_sizes[1]); ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, - 33333333, &pic, kernel_filename =3D=3D NULL ? 0 : 1); + 33333333, &uicdev, kernel_filename =3D=3D NULL ? 0 : 1); /* allocate and load BIOS */ fl_idx =3D 0; #if defined(USE_FLASH_BIOS) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3e191ae4af5..fe047074a17 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -36,6 +36,9 @@ #include "sysemu/sysemu.h" #include "qemu/log.h" #include "exec/address-spaces.h" +#include "hw/intc/ppc-uic.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" =20 //#define DEBUG_OPBA //#define DEBUG_SDRAM @@ -1446,14 +1449,15 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_sp= ace_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, + uint32_t sysclk, DeviceState **uicdevp, int do_init) { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; PowerPCCPU *cpu; CPUPPCState *env; - qemu_irq *pic, *irqs; + DeviceState *uicdev; + SysBusDevice *uicsbd; =20 memset(clk_setup, 0, sizeof(clk_setup)); /* init CPUs */ @@ -1474,59 +1478,69 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_sp= ace_mem, /* Initialize timers */ ppc_booke_timers_init(cpu, sysclk, 0); /* Universal interrupt controller */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic =3D ppcuic_init(env, irqs, 0x0C0, 0, 1); - *picp =3D pic; + uicdev =3D qdev_new(TYPE_PPC_UIC); + uicsbd =3D SYS_BUS_DEVICE(uicdev); + + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); + + *uicdevp =3D uicdev; + /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc4xx_sdram_init(env, pic[17], 2, ram_memories, + ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ - dma_irqs[0] =3D pic[5]; - dma_irqs[1] =3D pic[6]; - dma_irqs[2] =3D pic[7]; - dma_irqs[3] =3D pic[8]; + dma_irqs[0] =3D qdev_get_gpio_in(uicdev, 5); + dma_irqs[1] =3D qdev_get_gpio_in(uicdev, 6); + dma_irqs[2] =3D qdev_get_gpio_in(uicdev, 7); + dma_irqs[3] =3D qdev_get_gpio_in(uicdev, 8); ppc405_dma_init(env, dma_irqs); /* IIC controller */ - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); + sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, + qdev_get_gpio_in(uicdev, 2)); /* GPIO */ ppc405_gpio_init(0xef600700); /* Serial ports */ if (serial_hd(0) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + serial_mm_init(address_space_mem, 0xef600300, 0, + qdev_get_gpio_in(uicdev, 0), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + serial_mm_init(address_space_mem, 0xef600400, 0, + qdev_get_gpio_in(uicdev, 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } /* OCM */ ppc405_ocm_init(env); /* GPT */ - gpt_irqs[0] =3D pic[19]; - gpt_irqs[1] =3D pic[20]; - gpt_irqs[2] =3D pic[21]; - gpt_irqs[3] =3D pic[22]; - gpt_irqs[4] =3D pic[23]; + gpt_irqs[0] =3D qdev_get_gpio_in(uicdev, 19); + gpt_irqs[1] =3D qdev_get_gpio_in(uicdev, 20); + gpt_irqs[2] =3D qdev_get_gpio_in(uicdev, 21); + gpt_irqs[3] =3D qdev_get_gpio_in(uicdev, 22); + gpt_irqs[4] =3D qdev_get_gpio_in(uicdev, 23); ppc4xx_gpt_init(0xef600000, gpt_irqs); /* PCI */ - /* Uses pic[3], pic[16], pic[18] */ + /* Uses UIC IRQs 3, 16, 18 */ /* MAL */ - mal_irqs[0] =3D pic[11]; - mal_irqs[1] =3D pic[12]; - mal_irqs[2] =3D pic[13]; - mal_irqs[3] =3D pic[14]; + mal_irqs[0] =3D qdev_get_gpio_in(uicdev, 11); + mal_irqs[1] =3D qdev_get_gpio_in(uicdev, 12); + mal_irqs[2] =3D qdev_get_gpio_in(uicdev, 13); + mal_irqs[3] =3D qdev_get_gpio_in(uicdev, 14); ppc4xx_mal_init(env, 4, 2, mal_irqs); /* Ethernet */ - /* Uses pic[9], pic[15], pic[17] */ + /* Uses UIC IRQs 9, 15, 17 */ /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); =20 --=20 2.20.1 From nobody Fri May 17 07:07:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1610126322; cv=none; d=zohomail.com; s=zohoarc; b=eDA5PCYtVP5jb2H1KMOEXcpMx5LV65+CtmrYJIaJlrcA5XW6n0hqiJe3jX+13s4kRGN/yl9A0zSDljTS2Fa7ULZI1FkfG/5r7grqrGE0mDdqjB+Q+4nKCnkViWxam9iIa5jmV6iuIoYRss+Hfj9GcBSuLshJ23gOLM6sDNnL5HU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610126322; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v1sm13540456wrr.48.2021.01.08.09.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 09:12:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=65MIWpvfEizz0gfsIhaa+4GtpcZafIaROxnZgCMDZXM=; b=TiiAOFS9KGw0LxTSjgQs0AbYAO4aJtPltXBeUv2ozAaHqk9gu0UcjSDGNuWB+u0HZL q44jgynceIbo7FgH8MdtlHVWMizQVmCvtKLPQ1DuKEUxXO7r1Ksyt0qsxF4d4+iIOKeR VTPhJ7Qww47UXvvkXbbPNy79nmaw7RmhwkJZ/78bbhEzB74XC67TBjR8B5slfNE/oKZv 1magPrIRFNTxWaU57+BMJebTjZR5cB7D2RG5q0vipdw4LAubPgEwuKBjJZmgSCEKNobs ANeAaQh7SKOlamCzjY9E9GcRIpKzW6O6okGc4fyISfsz2ukzeKZXZQeH061xewIKT+dl /aGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=65MIWpvfEizz0gfsIhaa+4GtpcZafIaROxnZgCMDZXM=; b=OnFpGmdDE9hv53AyvrC2wYmiQRzM6j2Ql9MuCTjxdmIxIHF9SE3ELdxq3OjU8XmOPH uFTJ5kdu+GI7ifeBv5RLzeq2zxowwTi4sZbuJPDHxnlEvl4s3wZbZQ/n2Jj+NHzw9GtO LJpXMlisbXtvSMmoeG14xT2J8v3DKBTfV/6Pxds5Xm4IVIil1F2rr74/4P1rKMxyZTNx l0inCOAoI0kpeZSfEGMKhe42ouSR48IN5k4zp+VS0T65gqpqm7Xn8IqnNDyEL8MFLxLO Ud/pRhRtWfi+UfpEiyqVPOGsA6UQxflQ/eJSk4Tlkerco+BheaZlkha4iakplVTzfItQ dMRA== X-Gm-Message-State: AOAM532Lv4VljHODgyLfP0PsTqXAaTbce/Zj+iMq3TweDvl2nugTATis Cb30VXHWGfDiN0Wu4bUdyL6q1kT5AZgMnQ== X-Google-Smtp-Source: ABdhPJze9VzEmbdR14oJSJur2WD6wXB5biDlcLXaq0M8ETEBCLSA3YlicP70o+7o64HlrZfZMZ4Usw== X-Received: by 2002:a1c:68d6:: with SMTP id d205mr3975283wmc.154.1610125940241; Fri, 08 Jan 2021 09:12:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 4/4] hw/ppc: Remove unused ppcuic_init() Date: Fri, 8 Jan 2021 17:12:12 +0000 Message-Id: <20210108171212.16500-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108171212.16500-1-peter.maydell@linaro.org> References: <20210108171212.16500-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now we've converted all the callsites to directly create the QOM UIC device themselves, the ppcuic_init() function is unused and can be removed. The enum defining PPCUIC symbolic constants can be moved to the ppc-uic.h header where it more naturally belongs. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- include/hw/intc/ppc-uic.h | 7 +++++++ include/hw/ppc/ppc4xx.h | 9 --------- hw/ppc/ppc4xx_devs.c | 38 -------------------------------------- 3 files changed, 7 insertions(+), 47 deletions(-) diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h index e614e2ffd80..22dd5e5ac2c 100644 --- a/include/hw/intc/ppc-uic.h +++ b/include/hw/intc/ppc-uic.h @@ -47,6 +47,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC) =20 #define UIC_MAX_IRQ 32 =20 +/* Symbolic constants for the sysbus IRQ outputs */ +enum { + PPCUIC_OUTPUT_INT =3D 0, + PPCUIC_OUTPUT_CINT =3D 1, + PPCUIC_OUTPUT_NB, +}; + struct PPCUIC { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index cc19c8da5be..980f964b5a9 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -33,15 +33,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk); =20 -/* PowerPC 4xx universal interrupt controller */ -enum { - PPCUIC_OUTPUT_INT =3D 0, - PPCUIC_OUTPUT_CINT =3D 1, - PPCUIC_OUTPUT_NB, -}; -qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, - uint32_t dcr_base, int has_ssr, int has_vr); - void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[], diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index ffe4cf43e88..fe9d4f7155e 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -77,44 +77,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type, return cpu; } =20 -/*************************************************************************= ****/ -/* "Universal" Interrupt controller */ - -qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, - uint32_t dcr_base, int has_ssr, int has_vr) -{ - DeviceState *uicdev =3D qdev_new(TYPE_PPC_UIC); - SysBusDevice *uicsbd =3D SYS_BUS_DEVICE(uicdev); - qemu_irq *uic_irqs; - int i; - - qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base); - qdev_prop_set_bit(uicdev, "use-vectors", has_vr); - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)), - &error_fatal); - sysbus_realize_and_unref(uicsbd, &error_fatal); - - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]); - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT= ]); - - /* - * Return an allocated array of the UIC's input IRQ lines. - * This is an ugly temporary API to retain compatibility with - * the ppcuic_init() interface from the pre-QOM-conversion UIC. - * None of the callers free this array, so it is leaked -- but - * so was the array allocated by qemu_allocate_irqs() in the - * old code. - * - * The callers should just instantiate the UIC and wire it up - * themselves rather than passing qemu_irq* in and out of this functio= n. - */ - uic_irqs =3D g_new0(qemu_irq, UIC_MAX_IRQ); - for (i =3D 0; i < UIC_MAX_IRQ; i++) { - uic_irqs[i] =3D qdev_get_gpio_in(uicdev, i); - } - return uic_irqs; -} - /*************************************************************************= ****/ /* SDRAM controller */ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; --=20 2.20.1