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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/23] target/arm: Implement Cortex-M55 model
Date: Fri, 8 Jan 2021 15:36:05 +0000
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Now that we have implemented all the features needed by the v8.1M
architecture, we can add the model of the Cortex-M55. This is the
configuration without MVE support; we'll add MVE later.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201210201433.26262-5-peter.maydell@linaro.org
---
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0013e25412f..98544db2df3 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -401,6 +401,46 @@ static void cortex_m33_initfn(Object *obj)
cpu->ctr =3D 0x8000c000;
}
=20
+static void cortex_m55_initfn(Object *obj)
+{
+ ARMCPU *cpu =3D ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr =3D 0x410fd221; /* r0p1 */
+ cpu->revidr =3D 0;
+ cpu->pmsav7_dregion =3D 16;
+ cpu->sau_sregion =3D 8;
+ /*
+ * These are the MVFR* values for the FPU, no MVE configuration;
+ * we will update them later when we implement MVE
+ */
+ cpu->isar.mvfr0 =3D 0x10110221;
+ cpu->isar.mvfr1 =3D 0x12100011;
+ cpu->isar.mvfr2 =3D 0x00000040;
+ cpu->isar.id_pfr0 =3D 0x20000030;
+ cpu->isar.id_pfr1 =3D 0x00000230;
+ cpu->isar.id_dfr0 =3D 0x10200000;
+ cpu->id_afr0 =3D 0x00000000;
+ cpu->isar.id_mmfr0 =3D 0x00111040;
+ cpu->isar.id_mmfr1 =3D 0x00000000;
+ cpu->isar.id_mmfr2 =3D 0x01000000;
+ cpu->isar.id_mmfr3 =3D 0x00000011;
+ cpu->isar.id_isar0 =3D 0x01103110;
+ cpu->isar.id_isar1 =3D 0x02212000;
+ cpu->isar.id_isar2 =3D 0x20232232;
+ cpu->isar.id_isar3 =3D 0x01111131;
+ cpu->isar.id_isar4 =3D 0x01310132;
+ cpu->isar.id_isar5 =3D 0x00000000;
+ cpu->isar.id_isar6 =3D 0x00000000;
+ cpu->clidr =3D 0x00000000; /* caches not implemented */
+ cpu->ctr =3D 0x8303c003;
+}
+
static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D {
/* Dummy the TCM region regs for the moment */
{ .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .=
opc2 =3D 0,
@@ -655,6 +695,8 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D {
.class_init =3D arm_v7m_class_init },
{ .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn,
.class_init =3D arm_v7m_class_init },
+ { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn,
+ .class_init =3D arm_v7m_class_init },
{ .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn },
{ .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn },
{ .name =3D "ti925t", .initfn =3D ti925t_initfn },
--=20
2.20.1