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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id o124sm10003482wmb.5.2021.01.07.14.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SLgFG7YcdrjVHzWVWnO7xpT2n5lITWbqMk/I8sXWfOk=; b=d/2kXACMCYQclLA1uft/PbEWTToOKXFyqPw7O1axl2zel4sbNPxpmJ5XC3TjHwoKyb CEzzvJI4PAqaea5ghcON4a6gP4M65sPAYy7wEC2imtZENY4uqrK0U6GLXZoPEZmTbNFO Np8//S9+Sl80Rp9AsJZ/sD/GMGolPSyN7A8loIZENr/TZNM45KsGZ1hIzHPRSqUOIj1Q r8lsYqMDqomOL6eczMsHZ4A5ZPjr6gArW2M+DOv6QJzEmGkAflMzXJ1cDfjaBSf5F5cj oC5/V/JYLot/Yg2ZuVl7Hc40x8cq5/jIAU/b4ld7YGv+wvO0wTR70yV/5b+r/zJAPjES PgcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SLgFG7YcdrjVHzWVWnO7xpT2n5lITWbqMk/I8sXWfOk=; b=KUsC4rea1rGfzhfMM5m7boDdqtto5i8ir+XRYoDOS484oKx20IDTtMr1AaicQXRe/U CyIsWbrM6uCGrFxb4LpEpp88MuvMbCcnEDs11RiueuPXTmJ/oXfk6GVniDBACUyqV5L7 TOwtRY+GAjMOlm9cvXWB4j1Xgqj8St0rj8RixZx5ubtZ7SnJ7qUDHLOj2yrrCDu6Ahsx uXqBPz0TwIXnzo7tZEpx2CwaxYo3pWAcjbe6iMyJzWopAvUcPcmp0SiEg8QZxmOvz7UA p13wMfzTwg50Ppp+vyb3BpruHl+MScTdCLdKUGgftlxjtp65QdeCVa2TAua9HL9TjJ6C xt+A== X-Gm-Message-State: AOAM532lNVe0AfA/u7r7C3D3Loj6o3PQJ++XGD8vtHYL6yJTzPHFbL0f eq8V16aV1G2GFKeXPDgeLv8= X-Google-Smtp-Source: ABdhPJwABwkMalCqlOIOuUNqZu3FWRSiPZD48Pp+/a8H7j6j4kjy5sVuElCjluc7YUiLCJi3AklShw== X-Received: by 2002:a5d:6944:: with SMTP id r4mr688892wrw.134.1610058392803; Thu, 07 Jan 2021 14:26:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers Date: Thu, 7 Jan 2021 23:22:29 +0100 Message-Id: <20210107222253.20382-43-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. It is not very clear to have FPU registers displayed with MSA register names, even if MSA ASE is not present. Instead of aliasing FPU registers to the MSA ones (even when MSA is absent), we now alias the MSA ones to the FPU ones (only when MSA is present). Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-7-f4bug@amsat.org> --- target/mips/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e3cea5899f3..30354fee828 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31561,16 +31561,20 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); - for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - msa_wr_d[i * 2] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + + fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); + } + /* MSA */ + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + /* - * The scalar floating-point unit (FPU) registers are mapped on - * the MSA vector registers. + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. */ - fpu_f64[i] =3D msa_wr_d[i * 2]; + msa_wr_d[i * 2] =3D fpu_f64[i]; off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); --=20 2.26.2