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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id i9sm10795243wrs.70.2021.01.07.14.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xMINXm1sTVzeUT3ZE6sRQjEA5ZHRpEpLUaOQgOSkVsQ=; b=EHAE3Ol5/HOD8NEgpNC9Z7QLjkfjlPScUCA/+1Ni7Wvc/Ouh8RmBNpTvF44ACC+O94 ui3rGx1wKxHQQoWQyUnB9heNVZifzrLk54YRq8z3DH4E8rDIK8hHUaSM/Kf04dakP5vJ Fd/RQeSsatodFbulCqF6x8TiPphBSmQSoE2oFdRH4mW2S4ao8xDf4CPQc974T0fgAWgw KUM9zTusnII0RIHXs5cxNPaR4GTj5lKYOe9TbQos2ZzdL0gfkCVrktIaf+TvwrLhWRw7 fAdNPsepUBUnfdlphWJmcp2vcwOQupadPCDedEMM2CG1BB56BBZBMIvmFZBdizHwPzJH WgPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xMINXm1sTVzeUT3ZE6sRQjEA5ZHRpEpLUaOQgOSkVsQ=; b=XpRHYzH+Kd7zO3pDjXhFSYanIKrije2R6PyNf+FuK4wlyd5SyqiAZo7uS/atKK6bTD +b9FdM7sqsyCYbhPuIyw6w8q/cu6b1NHR3lWsiSUcBp5mBnLriqSYsKhRVdh5Y5d8iVc GrbujrdTyUqXsfOesvaXyHR3fKhj6wbrdXQLWC6I0wp6JA2Xu7GghiRc5LS15nzfPcYW fhFeq8DjT5KjR7qj5w+bagpPD7FvNJECP1EuGS3ZE+GzAB1FdTATvmnYunBQwV/N5pDJ IZ0t9eRHzYvF7Qn0Z3eBeSKoZhHrXfdKu9W55u9YTCOxBCJuafFiCwWP74ujpG+Smhw6 Z2gg== X-Gm-Message-State: AOAM532nNJffPOQCzKGBTYCURp8q5w26MwO/0gtH0qhs2ww+RLEMbE4C McDU6wMWu3wWAt9HY48evV8= X-Google-Smtp-Source: ABdhPJwjVucGLGwLTP8ZlzahNzVV4CW6S2hcO4HB4SrTqZzAZcO7bXWXd4P/foDdI4h565pPc3KKDw== X-Received: by 2002:a5d:60c1:: with SMTP id x1mr660228wrt.271.1610058362338; Thu, 07 Jan 2021 14:26:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton Subject: [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode Date: Thu, 7 Jan 2021 23:22:23 +0100 Message-Id: <20210107222253.20382-37-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Message-Id: <20201215225757.764263-3-f4bug@amsat.org> --- target/mips/translate.h | 2 -- target/mips/translate.c | 8 +++----- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index c70bca998fb..402bc5e8846 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -128,9 +128,7 @@ void generate_exception_err(DisasContext *ctx, int excp= , int err); void generate_exception_end(DisasContext *ctx, int excp); void gen_reserved_instruction(DisasContext *ctx); void check_insn(DisasContext *ctx, uint64_t flags); -#ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); -#endif void check_cp1_enabled(DisasContext *ctx); =20 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); diff --git a/target/mips/translate.c b/target/mips/translate.c index 7d2120dd51c..69fa8a50790 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2972,18 +2972,16 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } =20 -#ifdef TARGET_MIPS64 /* - * This code generates a "reserved instruction" exception if 64-bit - * instructions are not enabled. + * This code generates a "reserved instruction" exception if cpu is not + * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { + if (unlikely((TARGET_LONG_BITS !=3D 64) || !(ctx->hflags & MIPS_HFLAG_= 64))) { gen_reserved_instruction(ctx); } } -#endif =20 #ifndef CONFIG_USER_ONLY static inline void check_mvh(DisasContext *ctx) --=20 2.26.2