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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id z15sm10584113wrv.67.2021.01.07.14.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QRsQWA6DviCLjfaBDg1WbGaXrnSa2ioMMoOlaaR//h8=; b=o0OBpaG8YioPmnh4pCi8uEIllIPToQK4Y/ZurcH7/jBgzM0iX59PpRROfAX9KSm9Qv y1M/po13UpDx0ukSBaTIFxHYx4VHSUOnpOezCQWu3EYtKGgUVDXSvNIKYeSmL+QOqnJ3 H3LDJGFF/dNekLL+AvkIY3R91mTDJTumFY9rCML71mGVTSCTUkRJh+qP8r3Y1PO7DNwe +vVhhyT1Goj5s5FDV6ldmMGa/D7ylClNjaujOItzpFp/UtcLBZrmMSInI5/Tm27RIoiW qOJaAURMH/V8wGZ1oYMX4RaTnB5af38vnwNyLA0iYwxXzmtjAbdKRecF63ma5xT19Ny3 7LQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QRsQWA6DviCLjfaBDg1WbGaXrnSa2ioMMoOlaaR//h8=; b=btrxXoVjCcSzdXlCMYblszlF1s5S9wHR7U0ysV+WlTdlz0QG3596z84kccbibKFpkr Lx4YOWnqhfu3o+GzrObaNDc5VNqCRlozQhC7NhacUwp5uuWK0lSeMOIge73qe3GQSHvd 9ePljVRGpXXr547sR3Igb1ptJzJfdlwT6tx4WRNLfXApYwtL0YCkjDJRNXPVGCWu4CO6 CDbpQ+YAYv7SB9TqaG5ntR21kcjF+eMRGW+8iwhZFTy2e9Ohfd65C1eznyBhTgbZ+Kik 4eUXzw2tBETW9guhqXikrMldw+YXpypVclcyCgKwb7Ftvl/o5z91R/gtYb9x3EBsesSL NW6A== X-Gm-Message-State: AOAM532vTVcifDWsZB7rj2HifV6Om+0NBCI5GeB5tI+TDa12ZGfQlt42 Y9alQGk0fuBmpq6nHsOPonM= X-Google-Smtp-Source: ABdhPJzGmA4+ysp4m5XSrF57IUOYG8Bi+WA1SU7PAOx6p4FBWbHHquxLpd7/0eknqJS8F6BCz/U/mA== X-Received: by 2002:a1c:65d4:: with SMTP id z203mr509895wmb.65.1610058342032; Thu, 07 Jan 2021 14:25:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h' Date: Thu, 7 Jan 2021 23:22:19 +0100 Message-Id: <20210107222253.20382-33-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Some FPU translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-15-f4bug@amsat.org> --- target/mips/translate.h | 7 +++++++ target/mips/translate.c | 12 ++++++------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 5f744c63374..4c30a328e4b 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -60,12 +60,19 @@ void check_insn(DisasContext *ctx, uint64_t flags); #ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); #endif +void check_cp1_enabled(DisasContext *ctx); =20 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); =20 +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +int get_fp_bit(int cc); + extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv_i32 fpu_fcr0, fpu_fcr31; +extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; =20 #define LOG_DISAS(...) = \ diff --git a/target/mips/translate.c b/target/mips/translate.c index 7c20ed33df7..610fba61de4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; -static TCGv_i32 fpu_fcr0, fpu_fcr31; -static TCGv_i64 fpu_f64[32]; +TCGv_i32 fpu_fcr0, fpu_fcr31; +TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 #if defined(TARGET_MIPS64) @@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_= i32 t, int reg) } } =20 -static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(t, fpu_f64[reg]); @@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i6= 4 t, int reg) } } =20 -static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(fpu_f64[reg], t); @@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i= 64 t, int reg) } } =20 -static inline int get_fp_bit(int cc) +int get_fp_bit(int cc) { if (cc) { return 24 + cc; @@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ct= x) } } =20 -static inline void check_cp1_enabled(DisasContext *ctx) +void check_cp1_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); --=20 2.26.2