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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id w21sm9110700wmi.45.2021.01.07.14.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:25 -0800 (PST) X-MC-Unique: FHEBk4hgMk6CKfmGwHF8NA-1 X-MC-Unique: ZjgmIABBPVWr58q3MaG7AQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Md8yMDtPFL047sc9GnACrU93Gm/4UH0JKJe4iaxMljk=; b=EGWJtgA8gEjVlg/a9y8oKoXqTsbBRMnfNH/svaV8YugysrnnuW/7sfNbDJSUyAMcny Q7qSp8cQs/1430Efa/fd9z8XhnvgysQTvnYT3ys90vT6qhxc/Ln+RZj0gMwrs7oZxyl+ 2dIvoZSo19Sj0NO9Xdn4vgcRAlhmR765AyDnpyHbXmg1mO3AF1rRT9EUKs+zMN2Vu8s7 YY+WSoucJafuyZU9tN6N1WL49VYrH/AcI9lPN0jr9xjs8OOG+Pg4FJJg/7EqW8F7DIq4 QMqRSCGTWWtrMDykr17SFAP1+yh4Z4/heb5RSzCow5k0+SWgUmPXAEDRZv2fG4ND5wAy 42NA== X-Gm-Message-State: AOAM532i6qkxogECOSrn/DyA9tktCSnxlOYQnCmERH5Qzjqyf/SvmWmv TY5gijNG2RA1Gh7BrLGIEL3AmpLwa7o= X-Google-Smtp-Source: ABdhPJx/wlXEytr69sTyc89ncUwNXATKyBRfUcaBAbtdnUC6Nhbkylim6JvAaQ2HSmkJNXRQw6PVOQ== X-Received: by 2002:a7b:c7d3:: with SMTP id z19mr521782wmk.31.1610058326194; Thu, 07 Jan 2021 14:25:26 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 29/66] target/mips/translate: Add declarations for generic code Date: Thu, 7 Jan 2021 23:22:16 +0100 Message-Id: <20210107222253.20382-30-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-3-f4bug@amsat.org> --- target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++++ target/mips/translate.c | 45 ++++++++++------------------------------- 2 files changed, 49 insertions(+), 34 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index fcda1a99001..d9d4d3943af 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -10,6 +10,8 @@ =20 #include "exec/translator.h" =20 +#define MIPS_DEBUG_DISAS 0 + typedef struct DisasContext { DisasContextBase base; target_ulong saved_pc; @@ -47,4 +49,40 @@ typedef struct DisasContext { int gi; } DisasContext; =20 +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +void generate_exception(DisasContext *ctx, int excp); +void generate_exception_err(DisasContext *ctx, int excp, int err); +void generate_exception_end(DisasContext *ctx, int excp); +void check_insn(DisasContext *ctx, uint64_t flags); +#ifdef TARGET_MIPS64 +void check_mips_64(DisasContext *ctx); +#endif + +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); +void gen_load_gpr(TCGv t, int reg); +void gen_store_gpr(TCGv t, int reg); + +extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv bcond; + +#define LOG_DISAS(...) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ + } = \ + } while (0) + +#define MIPS_INVAL(op) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ + TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ + ctx->base.pc_next, ctx->opcode, op, = \ + ctx->opcode >> 26, ctx->opcode & 0x3F, = \ + ((ctx->opcode >> 16) & 0x1F)); = \ + } = \ + } while (0) + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 9e824e12d44..5889d24eb65 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -38,11 +38,6 @@ #include "fpu_helper.h" #include "translate.h" =20 -#define MIPS_DEBUG_DISAS 0 - -/* MIPS major opcodes */ -#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) - enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), @@ -2491,9 +2486,10 @@ enum { }; =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_PC; +TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget, bcond; +static TCGv cpu_dspctrl, btarget; +TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] =3D { }; #endif =20 -#define LOG_DISAS(...) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ - } = \ - } while (0) - -#define MIPS_INVAL(op) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ - ctx->base.pc_next, ctx->opcode, op, = \ - ctx->opcode >> 26, ctx->opcode & 0x3F, = \ - ((ctx->opcode >> 16) & 0x1F)); = \ - } = \ - } while (0) - /* General purpose registers moves. */ -static inline void gen_load_gpr(TCGv t, int reg) +void gen_load_gpr(TCGv t, int reg) { if (reg =3D=3D 0) { tcg_gen_movi_tl(t, 0); @@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg) } } =20 -static inline void gen_store_gpr(TCGv t, int reg) +void gen_store_gpr(TCGv t, int reg) { if (reg !=3D 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); @@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static inline void generate_exception_err(DisasContext *ctx, int excp, int= err) +void generate_exception_err(DisasContext *ctx, int excp, int err) { TCGv_i32 texcp =3D tcg_const_i32(excp); TCGv_i32 terr =3D tcg_const_i32(err); @@ -2774,12 +2752,12 @@ static inline void generate_exception_err(DisasCont= ext *ctx, int excp, int err) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static inline void generate_exception(DisasContext *ctx, int excp) +void generate_exception(DisasContext *ctx, int excp) { gen_helper_0e0i(raise_exception, excp); } =20 -static inline void generate_exception_end(DisasContext *ctx, int excp) +void generate_exception_end(DisasContext *ctx, int excp) { generate_exception_err(ctx, excp, 0); } @@ -3013,7 +2991,7 @@ static inline void check_dsp_r3(DisasContext *ctx) * This code generates a "reserved instruction" exception if the * CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(DisasContext *ctx, uint64_t flags) +void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { generate_exception_end(ctx, EXCP_RI); @@ -3064,7 +3042,7 @@ static inline void check_ps(DisasContext *ctx) * This code generates a "reserved instruction" exception if 64-bit * instructions are not enabled. */ -static inline void check_mips_64(DisasContext *ctx) +void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { generate_exception_end(ctx, EXCP_RI); @@ -3390,8 +3368,7 @@ OP_LD_ATOMIC(lld, ld64); #endif #undef OP_LD_ATOMIC =20 -static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, - int base, int offset) +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et) { if (base =3D=3D 0) { tcg_gen_movi_tl(addr, offset); --=20 2.26.2