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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id j9sm9990483wrm.14.2021.01.07.14.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:52 -0800 (PST) X-MC-Unique: rAaCkRvqMveSXhP6KxF1jQ-1 X-MC-Unique: aXlHywnZNVWgXtg83r5fZQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Sk0GjPOwaKw1OtxDzWJCyQVWdlOOm+hBJhH4fWESj5c=; b=sxSdd2RJ1046XV+FDvjzoy1UnRRGAp+agbWGUoN3anJPh469t1qQ8NgkHlvXqFbku+ xJb9NUzLSOsfqV5Bw5exWFeigoxM/qB0wawo0Wl9K+pcEzIeIlEZC5MByIw5aOvu8qmJ 2eDobGAkhptoghKkZa8GmtwfVXjxqmmClv6TZBe60jJ/Ja9U/Svr+YsO0ZyHKg530IzJ zp97DYb0lckqmUVqNAioG3CfsOzTGDQCHEMvOhVtt+7ijPukNWiWt/W8cAkmcZ2A5qNU re4zMyDCLwVR3Xb4jwNS54abO58qkqH2IRwXOGZDSozi0W/W/6ogUVzESD8IEpH+dnno tiFg== X-Gm-Message-State: AOAM531JharInFU5vjUUWNUHHl4rohl9Zzn2M8XZ2cVcV9M8pyA+ogBP GEngQru4kn1yuc7L8CDB46s= X-Google-Smtp-Source: ABdhPJxfMY/2VlzrtrNQv5zadl7d7OP9CwGcm/sT/2JQXSTpWmw1iz3t3qwI+FOR73I7mUwUdKKAgA== X-Received: by 2002:adf:e688:: with SMTP id r8mr687398wrm.20.1610058233425; Thu, 07 Jan 2021 14:23:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Date: Thu, 7 Jan 2021 23:21:58 +0100 Message-Id: <20210107222253.20382-12-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-9-f4bug@amsat.org> --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b36b59c12d3..ccdde0b4a43 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,7 +19,6 @@ #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL -#define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -81,7 +80,7 @@ =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) --=20 2.26.2