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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id u12sm2010pfh.98.2021.01.05.09.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 09:20:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KX8SYTYaScyamvEyH934P5SIRrediuz1DR0OI/8HBNE=; b=dKwlu+VYmpnZdiRCXMbGYKcAX/SZ8Kwb5PIAZ0hk/JMJsgcol6D5TyIzv5lGhEQLoB fJBkG+Q9KRFyvsr6zZ+ZrL/xGC1TdoqPxM9nSMD7vASCjE6rq+ntK6bq/xNqNkvuMhhk Jclgd2FzAX6wl9JmMmrlgZZByhulQoNnMTeqbEqhibKCZqC6ZtDnCUGpCYDEvwJI5JR6 grlkAKeVtniflrwuLJGQ3qRt3D+JsXCP1Gv4bk+gxSN+BvK3xQWhTrkWiBbuUOeNUh1N uL4mKhQu9oFVqE2Yed7yWYzM76Odd26NLnq4r4uyfQaZFbrpU5dXw0fAVcoXhMmhLin4 KFVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KX8SYTYaScyamvEyH934P5SIRrediuz1DR0OI/8HBNE=; b=uerYPGhMtUgEzpQhJNYAfMB/1JVKA1FV/cV4BY2jjnhAxGBekuHzlSDKAgENrMWWOz njyc3AaLFGld7SJuppZurBYKAfTp9ZjReYMDW1AgkLs0T7O3UsCl6c3UyulFh/9arH1e n6hyGySKvLdC8SFd5Wa2yr+WysEy60Ep1Ks3fiwtchX8F55MMya6ikXCoTMR09bOHW6k a5k7gu6Xy/Rv9ZiqLY5oZwU518VKlvCmt/MJ3Ze+WJoH6ThGm/SPGRJoh5YxzHYbimjK res7KtvoZ90rh0X8bHO2JbfjICJsMjECwOITNIot/SD7cMktV3mW7JBv99xmdeW/cUMv Cy4A== X-Gm-Message-State: AOAM532ktwi/sTTvMw3JcnwgUTnhmi2STlM0KSnMp2VXqBgxfVnNJfvE 2e8Cy7ux5q03g/r6JibEkf316RhjpmoPqw== X-Google-Smtp-Source: ABdhPJwsdIum+gbiUCXq0Oe7tHlv3PvtY3opDOitHH38vu1Dq1dqim4n/WXCyIsdIbgM3U6Lgn27xQ== X-Received: by 2002:a17:90a:a012:: with SMTP id q18mr209882pjp.223.1609867219543; Tue, 05 Jan 2021 09:20:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 13/43] tcg: Adjust tb_target_set_jmp_target for split-wx Date: Tue, 5 Jan 2021 07:19:20 -1000 Message-Id: <20210105171950.415486-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210105171950.415486-1-richard.henderson@linaro.org> References: <20210105171950.415486-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joelle van Dyne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/arm/tcg-target.h | 2 +- tcg/i386/tcg-target.h | 6 +++--- tcg/mips/tcg-target.h | 2 +- tcg/ppc/tcg-target.h | 2 +- tcg/riscv/tcg-target.h | 2 +- tcg/s390/tcg-target.h | 8 ++++---- tcg/sparc/tcg-target.h | 2 +- tcg/tci/tcg-target.h | 6 +++--- accel/tcg/cpu-exec.c | 4 +++- tcg/aarch64/tcg-target.c.inc | 12 ++++++------ tcg/mips/tcg-target.c.inc | 8 ++++---- tcg/ppc/tcg-target.c.inc | 16 ++++++++-------- tcg/sparc/tcg-target.c.inc | 14 +++++++------- 14 files changed, 44 insertions(+), 42 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 108a1fa969..5ec30dba25 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -149,7 +149,7 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 1e18fefd0e..8d1fee6327 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -136,7 +136,7 @@ enum { #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index f3836a4d0c..b693d3692d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -210,11 +210,11 @@ extern bool have_movbe; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) =3D=3D 32) =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t = addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, + uintptr_t jmp_rw, uintptr_t ad= dr) { /* patch the branch destination */ - qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); /* no need to flush icache explicitly */ } =20 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 624248b81e..c2c32fb38f 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -202,7 +202,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 301173c97e..d1339afc66 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -176,7 +176,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 888288d54c..727c8df418 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -161,7 +161,7 @@ typedef enum { #endif =20 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) =20 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 69576f4a9a..641464eea4 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -146,12 +146,12 @@ enum { TCG_AREG0 =3D TCG_REG_R10, }; =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t = addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, + uintptr_t jmp_rw, uintptr_t ad= dr) { /* patch the branch destination */ - intptr_t disp =3D addr - (jmp_addr - 2); - qatomic_set((int32_t *)jmp_addr, disp / 2); + intptr_t disp =3D addr - (jmp_rx - 2); + qatomic_set((int32_t *)jmp_rw, disp / 2); /* no need to flush icache explicitly */ } =20 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 9dce305253..95ab9af955 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -169,7 +169,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index e8277caee2..bb784e018e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -199,11 +199,11 @@ void tci_disas(uint8_t opc); =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t = addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, + uintptr_t jmp_rw, uintptr_t ad= dr) { /* patch the branch destination */ - qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); /* no need to flush icache explicitly */ } =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e01045f66c..8b74ad8d97 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -371,7 +371,9 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uin= tptr_t addr) if (TCG_TARGET_HAS_direct_jump) { uintptr_t offset =3D tb->jmp_target_arg[n]; uintptr_t tc_ptr =3D (uintptr_t)tb->tc.ptr; - tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); + uintptr_t jmp_rx =3D tc_ptr + offset; + uintptr_t jmp_rw =3D jmp_rx - tcg_splitwx_diff; + tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr); } else { tb->jmp_target_arg[n] =3D addr; } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 9ace859db3..fea784cf75 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1340,21 +1340,21 @@ static inline void tcg_out_call(TCGContext *s, cons= t tcg_insn_unit *target) } } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { tcg_insn_unit i1, i2; TCGType rt =3D TCG_TYPE_I64; TCGReg rd =3D TCG_REG_TMP; uint64_t pair; =20 - ptrdiff_t offset =3D addr - jmp_addr; + ptrdiff_t offset =3D addr - jmp_rx; =20 if (offset =3D=3D sextract64(offset, 0, 26)) { i1 =3D I3206_B | ((offset >> 2) & 0x3ffffff); i2 =3D NOP; } else { - offset =3D (addr >> 12) - (jmp_addr >> 12); + offset =3D (addr >> 12) - (jmp_rx >> 12); =20 /* patch ADRP */ i1 =3D I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5= - 2) | rd; @@ -1362,8 +1362,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintp= tr_t jmp_addr, i2 =3D I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd; } pair =3D (uint64_t)i2 << 32 | i1; - qatomic_set((uint64_t *)jmp_addr, pair); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set((uint64_t *)jmp_rw, pair); + flush_idcache_range(jmp_rx, jmp_rw, 8); } =20 static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e9c8c24741..52638e920c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2657,11 +2657,11 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer = */ } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { - qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); + flush_idcache_range(jmp_rx, jmp_rw, 4); } =20 typedef struct { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index a0a5bac13f..0eb9c4ebe2 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1722,13 +1722,13 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, insn); } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_insn_unit i1, i2; intptr_t tb_diff =3D addr - tc_ptr; - intptr_t br_diff =3D addr - (jmp_addr + 4); + intptr_t br_diff =3D addr - (jmp_rx + 4); uint64_t pair; =20 /* This does not exercise the range of the branch, but we do @@ -1752,13 +1752,13 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uin= tptr_t jmp_addr, =20 /* As per the enclosing if, this is ppc64. Avoid the _Static_asse= rt within qatomic_set that would fail to build a ppc32 host. */ - qatomic_set__nocheck((uint64_t *)jmp_addr, pair); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set__nocheck((uint64_t *)jmp_rw, pair); + flush_idcache_range(jmp_rx, jmp_rw, 8); } else { - intptr_t diff =3D addr - jmp_addr; + intptr_t diff =3D addr - jmp_rx; tcg_debug_assert(in_range_b(diff)); - qatomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc)); + flush_idcache_range(jmp_rx, jmp_rw, 4); } } =20 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 4c81d5f1c2..d599ae27b5 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1821,11 +1821,11 @@ void tcg_register_jit(const void *buf, size_t buf_s= ize) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { intptr_t tb_disp =3D addr - tc_ptr; - intptr_t br_disp =3D addr - jmp_addr; + intptr_t br_disp =3D addr - jmp_rx; tcg_insn_unit i1, i2; =20 /* We can reach the entire address space for ILP32. @@ -1834,9 +1834,9 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintp= tr_t jmp_addr, tcg_debug_assert(br_disp =3D=3D (int32_t)br_disp); =20 if (!USE_REG_TB) { - qatomic_set((uint32_t *)jmp_addr, + qatomic_set((uint32_t *)jmp_rw, deposit32(CALL, 0, 30, br_disp >> 2)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + flush_idcache_range(jmp_rx, jmp_rw, 4); return; } =20 @@ -1859,6 +1859,6 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintp= tr_t jmp_addr, | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); } =20 - qatomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set((uint64_t *)jmp_rw, deposit64(i2, 32, 32, i1)); + flush_idcache_range(jmp_rx, jmp_rw, 8); } --=20 2.25.1