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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id m8sm1021961wmc.27.2021.01.04.14.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b89sinWdwnRaR4NOd/DWOz5P627eErMVEbtVQAm5vR4=; b=mFQ66HgUEH1VSy7mQoonZ6iC92jq6SdwfXdQ5Nxf5fDEDXepk+1HxvHqAJteeLSbly jBKbwBvdO6zTIY3ZnwZpTB45rnm95qpc8kXk1jJsG8Y2Si6t92rInjLkGp5IbRKMS/Mi EQgzp5/nNtMcBwySLyuUL0r/uXLTmhIwQJtpW/dadfupidr9nmDSqagwu2rQT8eSqesX UQRpomHH94cTXKc3oVVrH7PcRsuWif4DUFZewadI4t27lkVWLiO6/Zs6iGdzrrPvG3QB u9Jgf1J500rvRoCutiteYmKlaUy1bgQ48pxB6hiKcO5A8rbbAA4YrsWRsZtI9xXPuGEP nmBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=b89sinWdwnRaR4NOd/DWOz5P627eErMVEbtVQAm5vR4=; b=Hum+mmEaFN/VXuc0dc5ix4hlHd67n2T/Xd2HSwlT8MXJQhvE27pHQR1raRa1EQ6hb0 oY4AILLgK7NNaQj+7LmgFQmRgwlR6Baa492LeuW/szCw1uKA6kDzrEkOjvhxV8fkdwu6 KwdLEILctUTPhHmXs2YNKwAdQag5x4HRCXQ+WXHJQc5FngBSvj/3Fr70kG5r5Ub243bK hNm8kSr/TPHaquqBKhMjf9JYL54cLpp1QR8XeUBdF9b1ZorgRU4Lym66JXjpkS6TusG2 brjByCRLSmGHxniP0aOXR501pjP9vD+vOPvU9rdgTABsVMMPgKbgwwz0gRBc6hkU3twZ qnxA== X-Gm-Message-State: AOAM532F5lSWgKJhhes6Hhuhs7Mt0aumycPW0xzSggRNmxsGe8j2D75C 5gtdFhQIJ4oe4OTZGnFgSus= X-Google-Smtp-Source: ABdhPJyZzr40x+ZZbPMqjzlXIzRjSJz5ZeXla1+uHP/pg2bEXS5guMqjKr/y4nyNnDsdWqqviFXVDQ== X-Received: by 2002:a5d:40ce:: with SMTP id b14mr80470579wrq.350.1609798370305; Mon, 04 Jan 2021 14:12:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 10/15] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Date: Mon, 4 Jan 2021 23:11:49 +0100 Message-Id: <20210104221154.3127610-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 3 +-- target/mips/helper.c | 6 +++--- target/mips/translate.c | 2 +- 5 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index e4d2d9f44f9..3466725b761 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS64R6) { + } else if (env->insn_flags & ISA_MIPS32R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b71127ddd7c..fea547508f0 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -21,7 +21,6 @@ #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL -#define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -87,7 +86,7 @@ =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index f0831379cc4..e400166c583 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,8 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/helper.c b/target/mips/helper.c index 87296fbad69..5b74815beb0 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 9fc9dedf30d..fc93b9da8eb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | ISA= _MIPS64R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, --=20 2.26.2