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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id o74sm1492021wme.36.2021.01.04.14.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R0fUu3amHo0lA4w4O2ssd05dqOIAFEftWBDmfRDtfjY=; b=ZAqI1Lwp6ggpOLrNcdsQzCa3HnOgw2whicGGVc85/VlrEMUSE/ruVbppAlwaIqDzXZ 9ywuFT67ga3+3r4US30uKJyYuFVF4ahzFDVZCH0yUQcMH1ppXh2N+bCikCgaGX/gc7Eo mNBeCVkGXYm+FNcmj5NpmMt9JPOXqehz6WH/lwID6y36n8Is86K/y9DoD5/I7IlJ/aqk EI8ljxkCyXvjzNO/py7mG1wfggrcFwFAiruVPBz/mTS6LUHO7dvLxQtmWAWcxfrQsv6n b/NTlyCsNGvgiIel0iESHsGF3rCVZgHwGy/wKz3r/LYhBLICcWbfCe3WvdAkgEj9GpkD IZpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=R0fUu3amHo0lA4w4O2ssd05dqOIAFEftWBDmfRDtfjY=; b=V15w4N8O3x7b2HLNSMsDZI6Unlg+KuqUG3zYafY2WDVEMgkYCGCZjSxRp9m3DSs1f9 DQeANF7sQ1YCAq9oSECtYWOWS9tGmYrNJJS15DYYEpv3aq8vlPhKf5x5aVgW166Ph1u3 DZQJ1xGTUCjmKAwHnMRo+NjlhwHL77WWboWJd87eo6OdQqC8kw08W+2EWFHPKd9oxBph 4urOiGE1/G7qmUMF0G2pGzbzG1SDvrO7JRWs4790cMIvOb7CpwTYXDOu4C8jWaWCK2kq XGnyMy6pwhUQEG6QkLh8lPiVABJX/7UlorNPMaWwWTW4Xe/9WjR2VTD+KkgJre+LjoUo RL3g== X-Gm-Message-State: AOAM532yJUWQJ5P00ow99JMV7Hoo0IFgscUkgNicp0kQOWtW6sdiJKFN Mqj0jzlpWqYpJ9gLaXX4UcA= X-Google-Smtp-Source: ABdhPJw2JgWhLMn7o5554E4TVhpOlDWDdbCKKjMPvX+4jl7z5gJyAwsMrBGqMuMFwiqKBl6hDKw+JQ== X-Received: by 2002:adf:a543:: with SMTP id j3mr59698413wrb.175.1609798322698; Mon, 04 Jan 2021 14:12:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Date: Mon, 4 Jan 2021 23:11:40 +0100 Message-Id: <20210104221154.3127610-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ed6a7a9e545..555e165fb01 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -1,12 +1,6 @@ #ifndef QEMU_MIPS_DEFS_H #define QEMU_MIPS_DEFS_H =20 -/* - * If we want to use host float regs... - * - * #define USE_HOST_FLOAT_REGS - */ - /* Real pages are variable size... */ #define MIPS_TLB_MAX 128 =20 --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1609798330; cv=none; d=zohomail.com; s=zohoarc; b=LINRr/sFp/b7g4EjIAkqj3iQlR9AT+yfW5rQ4cV7Pg0T5SuK7TuV9NE4fdt6fvq8YbBElvS02K7aHWJqqfPuD58GaCswLgPWef4pRRP7URVLUU9hu4/rLHvePf7Pnc0XCH/4CvjXeSDsT5nRQdZLU5ZuBEM2CdxiQoWSQ1B10Oo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798330; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1xSZWIVn+fZ9mZfvZyHB6Qw66SpG//htqcx68delhkw=; b=WjdJxPnhqltt55x2r+6dzMCuldglJ7oVtN7y/OZCLsjBCEbm5o6mran02dU9SIs8FWATmcm4fUgiPwGOObKzPJa9XJl5haeEflJ+iiM+mufmiBXOzsGfD7zqBLFP0INW6FbbqTBmW+5VoTTUnjiZZWX2zTb5zouReSElOm3jxL0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1609798330059308.83368649794147; Mon, 4 Jan 2021 14:12:10 -0800 (PST) Received: by mail-wr1-f50.google.com with SMTP id w5so33598049wrm.11 for ; Mon, 04 Jan 2021 14:12:09 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 555e165fb01..48544ba73b4 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -65,13 +65,12 @@ #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) #define CPU_R5900 (CPU_MIPS3 | INSN_R5900) #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 -#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) - /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id k10sm87981974wrq.38.2021.01.04.14.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mf1NXGoh/iaVlyRR50VUiVMtSin249waJuI6gSQgqVE=; b=DM7inBfD0ZeQVZvEtUgTlMRGd524a1scT+jy3CY95rtTR+sX3H5MvOPXYYuZ3lfdsg pK3UoqFyp72AQ7gaZjbGmlcHBEadM+KTStVmalT8PVdfHqQHfpv3/KAZLMatKwK29G74 WDswOMqefSDOeuV1H274rc8W4aalI3OWjjNZpPDmN3mK7SJzEWgQsiYISEF2p5tenKlr 5WsD8tBDAtdBefnF7AUh1rNEqO+ET0ly2EtMAxW2gwgehQAYoEnDAOl5XhwqI3bCb/TL /G44rN+SqhI+lV0ME66aA5ome6xNLC/9gCElU+xB+FyXcf4eIAMllbdgF1P9hQGdBkL1 oIdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Mf1NXGoh/iaVlyRR50VUiVMtSin249waJuI6gSQgqVE=; b=A427gIxLbv3+1PuWgApJmGGVYGEvWjX7ICowTKkC7tJwMDE7Wmg3ngpMl8WCvn1mYt Dmvs34r52dX/3F/BD0Lr+fnwCYH02iIPg9iVAUuwbZsSF0WKRIAHxRlXJrU8tK7pKQSy zGU9E0jDqekp6G7BuVdF7jihtJrkEV7j0TfIR23Ks0ItOb/jxLeOmuFGVqrurPa2WTok vByTBN7bjdq0+TN5k0s4ssRzU026bWagvOBe5RiLTVTx4ikAZyPCwVETjvm8vSmRH0m2 nQJgjP61bBjVXOee7s6WcokPS5pewRHGl4661XWZrnLZVJ7jXTP/w72CBZyx8H9PaNR0 ncew== X-Gm-Message-State: AOAM532VydyUN/NkGCOi5vf6FWBp6DKO43lJ7haZT7KR/KruBWRRAM3S i7Q31cbvkr9wNdYIZW82RRo= X-Google-Smtp-Source: ABdhPJxwmS9rZkEH6IGUSP5JK/jfE1ZrxdgxLd2vFraY1LTgj81LEL+G79Ud2mLAmUtclbKVmrYP9Q== X-Received: by 2002:a5d:4a44:: with SMTP id v4mr84457957wrs.106.1609798333853; Mon, 04 Jan 2021 14:12:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 03/15] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Date: Mon, 4 Jan 2021 23:11:42 +0100 Message-Id: <20210104221154.3127610-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) 'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 8 ++++---- target/mips/translate_init.c.inc | 14 +++++++------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 48544ba73b4..1630ae20d59 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -72,12 +72,12 @@ #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) =20 /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2) =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index f72fee3b40a..427da84768b 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -72,7 +72,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1278FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32, + .insn_flags =3D CPU_MIPS32R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -94,7 +94,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1258FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32 | ASE_MIPS16, + .insn_flags =3D CPU_MIPS32R1 | ASE_MIPS16, .mmu_type =3D MMU_TYPE_FMT, }, { @@ -114,7 +114,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1278FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32, + .insn_flags =3D CPU_MIPS32R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -134,7 +134,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1258FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32 | ASE_MIPS16, + .insn_flags =3D CPU_MIPS32R1 | ASE_MIPS16, .mmu_type =3D MMU_TYPE_FMT, }, { @@ -550,7 +550,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x12F8FFFF, .SEGBITS =3D 42, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64, + .insn_flags =3D CPU_MIPS64R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -576,7 +576,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 42, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64, + .insn_flags =3D CPU_MIPS64R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -605,7 +605,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64 | ASE_MIPS3D, + .insn_flags =3D CPU_MIPS64R1 | ASE_MIPS3D, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798340; cv=none; d=zohomail.com; s=zohoarc; b=VBJXYw/JBaV61ZtdDp4i0stPk3yjbchAXIh1YANt7KNa/UcO2kHq6qunwwUFfKUno5lQ5W4PBB13g21ShmhDusfZAvxp7hIuTnrxwvx24ws9EhAfkr3uk94Y/9/1FoftiG8Vr9Vw6E0x1S5gzpKS0ykF/fGGPgwlUw02BTfzf4s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798340; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FY8utL4BuRYo0iYGKc1d1mWLl6o5xAsuE1shmmN0tBE=; b=i2bg9oWaKN56AsHJDSNTHNceQSkNohuYemNTEzGC1cIdwAOEM5wNofyW1Xp9AfiK2J1WbzV3N0t1cN/No5RTuWNo1lHoKKz2Jc3tezNK92ZEK8ELldoZCGOk6zZcFgtVbrVf6nmFGknW5vIWlDbAply+Y975+xXUOxrCPm7YLhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.zohomail.com with SMTPS id 1609798340528682.7113175584245; Mon, 4 Jan 2021 14:12:20 -0800 (PST) Received: by mail-wm1-f44.google.com with SMTP id y23so657542wmi.1 for ; Mon, 04 Jan 2021 14:12:19 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id p15sm88509150wrt.15.2021.01.04.14.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FY8utL4BuRYo0iYGKc1d1mWLl6o5xAsuE1shmmN0tBE=; b=rYljLbzXCIn1OMxz2HKqwSXUZPYzBaGTmBMjCppocVx5ov25p1TQVdgmQOIzgPq+9s ojnS+MLn9TtFN6SVgmQv/+VYLPKFLVsz9J9pl1qsEEakYkExmH6JO7yYTSlEhLlBV7gW 6bJJ0fBQLMO5WjZSQPN+emsRNvfHuFNpEu924S+uTmRKXwSfeJ9H+zN334Rpjm9BGs1q a5Nkq7RrOXMovfCacBzUc04aqzLG/16KF3bnj4QIINg4NjDDCqM5lEh/MqWRWPORumK6 SrizRJiI3Zc9R5jkCh0K5DwbyVVqKqxQ55R2fnMHZqMpL/xaLpFH5tBWZZ+yuVWmpMvq DxoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=FY8utL4BuRYo0iYGKc1d1mWLl6o5xAsuE1shmmN0tBE=; b=uE9WPZoxOftDDRATP/wgTMdMCeOCzNf1KcKfEAkvvVo9t7qhxDcta3NHS4WNlJWQK5 g9TuIaZrP0ExLLsbXgOPBgIJAw0Dc/uvANq2TDhEfvW3/evfb3uLbZcRPXafCinxq1Zk VRRn/jMueymERh0IZyDS1JgwEvtCi3x1L0A5Ssm4UQyZUn23vFl7rkUd9rVNVCuSWzzi bEN06+k8a9ToskmsXKY/OBN0PL/Zzu+Qc/s1U77kpoqlhdlKmJ8zVVagnIDxu7jGcbE4 EhnQs/gagv2e7Q7Kus3mhWMuEFbykLZkQyLD3MX1ClAeJHXQb/P+rwTQCcxr7tnvcfev Tcyg== X-Gm-Message-State: AOAM530PBHGaRhv3yetWgRK1ZukS8rtql82ffr0+TfpY9nMcD4ab+0Kd UYTTcwFW8opm51SAs75qvf0= X-Google-Smtp-Source: ABdhPJzJIzvHrCKuPQkN5VHW9V+bBtdou94beS/hCueb9r5G8JOJfGSm+T6AzPVdyBB1UuW6qswjdQ== X-Received: by 2002:a7b:c157:: with SMTP id z23mr774658wmi.35.1609798338727; Mon, 04 Jan 2021 14:12:18 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Date: Mon, 4 Jan 2021 23:11:43 +0100 Message-Id: <20210104221154.3127610-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.h | 5 +++++ target/mips/mips-defs.h | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4cbc31c3e8d..7c60a335f97 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1297,6 +1297,11 @@ static inline bool ase_mt_available(CPUMIPSState *en= v) return env->CP0_Config3 & (1 << CP0C3_MT); } =20 +static inline bool cpu_type_is_64bit(const char *cpu_type) +{ + return cpu_type_supports_isa(cpu_type, CPU_MIPS64); +} + void cpu_set_exception_base(int vp_index, target_ulong address); =20 /* addr.c */ diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 1630ae20d59..89a9a4dda31 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -13,7 +13,7 @@ */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL -#define ISA_MIPS3 0x0000000000000004ULL +#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL @@ -71,6 +71,8 @@ #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 +#define CPU_MIPS64 (ISA_MIPS3) + /* MIPS Technologies "Release 1" */ #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798345; cv=none; d=zohomail.com; s=zohoarc; b=CPCR5v6PrX1FLiBWxQ0oeh5ZkKDu6ZqNfi+i2uTJVz5RHUuCbuBn1U4yzgJiIpD3IKmPBIgqcaXxBEmUVyoohRTvEDbYG/NhADYCP883YIK0XNdecPaayEJXAA2GrIIzgKAxB9o0rK99SLkokmtsVFF6Qs1ACkGXn3hTcl4MQaE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798345; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DwLakVX9UEsAH+MmXq72YbVgXyrXxgRV9mVJnolEV3k=; b=RdzcN4K19qwkKP0JY1NzyZdwj0UIj4Wouq2WVblAF6b24dzaTW43FESz7/jq4wFdVvvjtmTxjQXIL1DxIZvp65+x0wYLXNTD4ZoUxYctzDhu3Tm0jbqLJ8SahlN1g+ECgCN7rpd7Fk0m3q913clARkOWIPwr9oabmzT6ga53XiA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1609798345790909.6708752361806; Mon, 4 Jan 2021 14:12:25 -0800 (PST) Received: by mail-wm1-f50.google.com with SMTP id v14so625394wml.1 for ; Mon, 04 Jan 2021 14:12:25 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id 189sm1164064wma.22.2021.01.04.14.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DwLakVX9UEsAH+MmXq72YbVgXyrXxgRV9mVJnolEV3k=; b=Gmi94JhBkJXrVi0c/wi1jjurTWq1ybMc3PfRGPvjqZGeA88mzEBZ8Bp+ZvYFjAkmjV pm84gSTq4o6pG/1lTesmqZnUDekfh5VhAkY4TlPDIwTGC5WeTYucoEfwjVo3NwB6FBpO c3Hm9LLPkvWasM0mL2D+4x7yj3iV7vb914ZAlJ1DXYthZbzrfpeqCJUBSepkjc2EVqtd sBDXBPDgy3qRnOD1jaT0OXcnGISrTsw7jTiQ2H3yyngmtf7ZqRbQZHIAbh+nLxoKcV7p GgVZooE2mfQHNVpyV8m80QEJmZgXnGGPT253na5zu0MbhS/O0ty+G8FkLCNndfMwQe6Z NPmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DwLakVX9UEsAH+MmXq72YbVgXyrXxgRV9mVJnolEV3k=; b=qic1VfwcVCqgJjWszBuWw98qMvB37xWPxKIZUqhnBdbrHi8IwN87hI/DsAzOUm1ZL7 P+nnZue8G/D2rqa2vpsgjCt10rBDH4lB6JllFK81AU/0nVc9eaSg+sQ4rHcJKYdl5Fim v/gOy+6np4WbG85YlHKwJO1SAQ2LpbhjPTY3kf5JuM/ca8T1J3aIV3rh4YYD/kfwre1W nAx1MkTV++XJG1ii97I/IKog8hwDdG9nRErDwyUmk5sB4bdHf/HHSp7JwX/0LSQBSQwp XfIIxQHWZ6QOIuSswgjK10kq6Ur9fdAScJB5T433Ndh0IuKrULglX467mAcDG6++hxHF Dtlg== X-Gm-Message-State: AOAM530ey/NY2zZn8iztC/ymlLUjXo1E/ggbZDvSUnamzPsPdIwsqRS0 upzM0dlvvvWVU6BR4LG4+Jo= X-Google-Smtp-Source: ABdhPJwIK4BbFoJSoDNkYMQ+vRP1jUMVACf3J2HYogGdJlUZV83i0q2BZQ96oYsRigUS2VsRcWoAZA== X-Received: by 2002:a7b:cb93:: with SMTP id m19mr809192wmi.45.1609798344054; Mon, 04 Jan 2021 14:12:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 05/15] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Date: Mon, 4 Jan 2021 23:11:44 +0100 Message-Id: <20210104221154.3127610-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Directly check if the CPU supports 64-bit with the recently added cpu_type_is_64bit() helper (inlined). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/mips/boston.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index c3b94c68e1b..467fbc1c8be 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -444,7 +444,6 @@ static void boston_mach_init(MachineState *machine) DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; - bool is_64b; =20 if ((machine->ram_size % GiB) || (machine->ram_size > (2 * GiB))) { @@ -463,8 +462,6 @@ static void boston_mach_init(MachineState *machine) exit(1); } =20 - is_64b =3D cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); - object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS= ); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, &error_fatal); @@ -545,7 +542,8 @@ static void boston_mach_init(MachineState *machine) } =20 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, - s->kernel_entry, s->fdt_base, is_64b); + s->kernel_entry, s->fdt_base, + cpu_type_is_64bit(machine->cpu_type)); } else if (!qtest_enabled()) { error_report("Please provide either a -kernel or -bios argument"); exit(1); --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798350; cv=none; d=zohomail.com; s=zohoarc; b=EDuc+udeKewSJNo2rmfQ0KHBetlvW1ZpRJeC/v9YXd2TI17BYHhbH0gua+MhGpVv01zLks3L2gGZCHUvGfIAYaKy7huLguH8j6FRHyRv6g7LnMe+RTRvj7qo0AYL3R74juIN9nd/PWSnIeiTyEaXWXmNZfoH7OpprdY1hYoQQQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798350; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SP83Oiq02Qsq/8v5vGzHElDNDyEc9uZVrWLP/QNGOLI=; b=lK6kRHpoTZGuPiLiOmyMr+jMOA04mYPMPuegMbDKEkRpRjxR0dO+4uG6x13nhoHj0r0RvTuc5vYFucwZ2Hw1oAY8+Ws42LAJPVDYcGlHCBbzL6XeOeSq8kwo+lbBalGNqBNS7i6PY9aO0/R77hAIhU1f4zxEGF6iXBKppLVX2Rk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1609798350840847.9567461844944; Mon, 4 Jan 2021 14:12:30 -0800 (PST) Received: by mail-wr1-f43.google.com with SMTP id w5so33598674wrm.11 for ; Mon, 04 Jan 2021 14:12:30 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id o13sm73915718wrh.88.2021.01.04.14.12.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SP83Oiq02Qsq/8v5vGzHElDNDyEc9uZVrWLP/QNGOLI=; b=npV6HP0wYp1WCxbK211gY69wzSl++xV2RpnDo59x3R1k4CSbuhWgyCALKBWtAfs39u MB6SJcDlVpj3AZTn3+3pb3Zhis6n1PaxczMWYE5f4LmbpmdZthoQnJaZoVENaAco0lqq qB/aWGuv4PKFYgRV6PYQoYa3/y6z08Uxn3moTXQ1cX5XfdxiOMBa2BJLH9gdnn4lc9uL W5NAbiEJ3C8VLuSHxMf6fa/WnaXEWMTeYjt3WTUspHLaVKgAEj0yEO/U4gRCxSbuq8W0 Bv54x9+2tN8C7+SBmFwgtzBuBqIQmrFOcvlhj+GwCxV2FmlNoL9VUR/Enjew5tE4/iIC 9tHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SP83Oiq02Qsq/8v5vGzHElDNDyEc9uZVrWLP/QNGOLI=; b=peT7tf23q2VRVEwSSm41gf7AVa0EDvirUr472k3635jfeIY4jnQG4N8nOraYCJeRf0 8Qhc/FObc3sOdioC43TBkX3bgAkXX4sgP0oE+nANofibF/xfWAqyuEir5fB/k0EOCS5R y8ZNuBXnE5vlY4GwUJUYVghI3PGau1JmBUfCBxFAHn+2cLarUNCxnSvBFt+KTX3UUMwn lqSZoiatvkORxN62cGz3hZMm/0wDGxpVH42jX2ceKP/e0IucYWnilasH17ojEZER2Kcu MbQDgDa8djESzooQWdpJdFAeIWbEarYmpzQjT6cTa/RPwgNppbpqD87M0XC1rB3vtbkH /B7g== X-Gm-Message-State: AOAM532M/UHmSz00hgptmpSvkT8fgcliWL+7qlTc5CFnuXT+hsktVBbc s72fBlnL2hnfRLKn8XdGBTY= X-Google-Smtp-Source: ABdhPJx2MxvE1jHW2jCA74vyWWiZHEmHhH6yvj3KYZVhgF1VyhgeucK4WfiYdiDAcZj5O7iFKPqQJw== X-Received: by 2002:a5d:5147:: with SMTP id u7mr83404221wrt.114.1609798348962; Mon, 04 Jan 2021 14:12:28 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 06/15] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Date: Mon, 4 Jan 2021 23:11:45 +0100 Message-Id: <20210104221154.3127610-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- target/mips/translate.c | 10 +++++----- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 89a9a4dda31..23ce8b8406f 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -18,7 +18,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64 0x0000000000000080ULL #define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL @@ -75,7 +74,7 @@ =20 /* MIPS Technologies "Release 1" */ #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) +#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) diff --git a/target/mips/translate.c b/target/mips/translate.c index 19933b7868c..172027f9d6e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } =20 switch (reg) { @@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, D= isasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -27612,7 +27612,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) client-ip=209.85.128.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1609798356; cv=none; d=zohomail.com; s=zohoarc; b=Sj28TvxPVy2fvSjtBEPMFP4ppffRFzvj2YgJwP0lE3LXTqKYI9vOhRGbb7scR6Z147rNB1evLc9TDRFqjf27eCzKjkO3i4mZMvkSRs6e2+W8imKl27rwDrGThXYnqeFPXnkDzJYYC8l6aqmwYrBGEGolJN7KO2GzgJyd/2fSjiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798356; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mzS6CmYENIvHrXJm6AYrCynCfObCNaLAeaEBzOk9eFM=; b=B3N6y27TxPDgfz+omwMfWWs98QWuJFTA6jN/d70z2pIWl5vCRLS7cFdcGeqcF88R9bXsFbQld0ljsjUhA94poHsUKRkts9Gn4GWly/VO/YEDgV6kjnd7JvYHx8P4RzZFjuF27/CraOHN3aOjFHtn6ZUrblrifX/i28U2k8ZGTNg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.zohomail.com with SMTPS id 1609798356254359.95024842962914; Mon, 4 Jan 2021 14:12:36 -0800 (PST) Received: by mail-wm1-f53.google.com with SMTP id k10so613821wmi.3 for ; Mon, 04 Jan 2021 14:12:35 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id r82sm1203228wma.18.2021.01.04.14.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mzS6CmYENIvHrXJm6AYrCynCfObCNaLAeaEBzOk9eFM=; b=kuviyC3bvcNL1c3FKSBJyLtiz6cjb2Zu2xb4KFt+rvzbW/7e9vn9ThgXG6klLyO4SW 0N0gjOf9ZJcg73NeqTpTcoX/OY51VTPxN763ATmJyLdBh+2JbDVazq62f0Ve7BBz0PAZ H+ZeVWZMO4LZ3tEapHP0zVGD/hum148U6DXQuQbiAy8sdwsjpaTcEH7cnHKxbXpqi/Ck A/IpqKam4TLg83i7giX1xirJ+kic1BRkaJha0XytRhCQafs8ltc0AzKJ4gvL/jEpBUNz qy2VhVc5cfsRRpvMI9r+ni0EsmO/b4vYZzD2Av+lvDiNyX0fTjJCxiSc2C/X6wIfuXOF NPaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mzS6CmYENIvHrXJm6AYrCynCfObCNaLAeaEBzOk9eFM=; b=ZB0Fg8TUqCaRMOuIJ4lE/XDNMOflPvICJpxuxE+o4EXM5Mncu1CY46rErpsWUb7qTX pUr+YH8sA4tqAGq/BA6/zuxoontu3L1CaDa6ZGc6WqLcQLk3aFTccWnjuUKEAKPoQS92 wORNMLsLPDS/nh2PpddaEGaYJnkwIk237s/+HwpTnee1juRAe9RlEyhxFaBmp0yNAY1c lzYLPdU/+K/PiIJPr+yCIh6+N6BQmoN5T/eBMYYJdmu05JNVALcygOqHMPotIy4J5maS xiJEcFx80/enGco9FVFyBXAbyn54zXvpqa1PzPwUzHinLDMTs4nWkgSSycG9Fx/VJORW X9nQ== X-Gm-Message-State: AOAM532EbOfxixFz0kfqG/8tXHJXy5jUsG+mQfFaNU3zbqqA5azON7Ww CeMK71oihByIr889BdjT8tY= X-Google-Smtp-Source: ABdhPJxpry71DEsr5XhyFZGdUco/OCYn0NYd6V0jdZ1HCyUziiKXaQI1mBSao6vUBxsKQmnF/rK4Ow== X-Received: by 2002:a1c:c308:: with SMTP id t8mr823613wmf.22.1609798354425; Mon, 04 Jan 2021 14:12:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/15] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Date: Mon, 4 Jan 2021 23:11:46 +0100 Message-Id: <20210104221154.3127610-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 1 - target/mips/translate.c | 4 ++-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 23ce8b8406f..b36b59c12d3 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -18,7 +18,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -78,7 +77,7 @@ =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5c47d..f0831379cc4 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS64R2 || env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS64R6; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 172027f9d6e..9fc9dedf30d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); op2 =3D MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798361; cv=none; d=zohomail.com; s=zohoarc; b=Vg6sDr5CbU3CFWY506UG8bN0Pa32fWbsh+omKZ94q+NcxIUSswwwojpridT2/dJtbbxoVqMqfFI1uffZB82XfHPZgrQWOMS2YuSjkDbF0KjWmGHufYlqg0fRgQIxuWhPc4H1nW+vT6UZKW/fSqYZrldk7jIjpuEjOiLBR3OHprU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798361; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Jz6DSMJb3Okox6KqPHpjD4NrZ1Oy5kyq5dcv/sox1cM=; b=N/Mmuf2AiUjK+INfUMCTwooeNpKiwysOpirjYUE+M3JJyHtx/9OvNyvUsJX2wlKVpLo4T4zdYjVW1xeBN1lBaEHWoQZc/xeI0xxlXjK3paNNrV2w7TVTghs3XJKtZITbdKYX1uK1H+EmUgQjuGsSiwkVNhAE850HfHhsE9LP1zU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1609798361473339.96517669386253; Mon, 4 Jan 2021 14:12:41 -0800 (PST) Received: by mail-wr1-f53.google.com with SMTP id t16so33649727wra.3 for ; Mon, 04 Jan 2021 14:12:40 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id p15sm88510178wrt.15.2021.01.04.14.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jz6DSMJb3Okox6KqPHpjD4NrZ1Oy5kyq5dcv/sox1cM=; b=pp2MnUl3BSCRwLIgChnE04jDOb9qc+hyQ97eR7Vac9H/tjS4ju3aE29AGZOU97EZfo VvK59Rx8GoYH8xwBrJZdivsIvtFrG+JfoSnTDloFjCS+9hEKcT3ITjhQ9M3SU1r70GQe lMStQ31vtrRGBvYYtAm9x1E9+P0IjC+0NGP5hs7Z4pAfTaTY/21oJKti05pDhu5hsGog mBQI39aVWomrkKBA5Qah349+h6RDY1pVKLWKyzksC0n6id2B6hkXvydaNOHBI8kvQFuz eLjiksc6A4u8KChgZrpupr7/K9HMesmSOirbJOfSv2IcTNVV6SiZct2miV6iw3PQZEQ7 kNyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Jz6DSMJb3Okox6KqPHpjD4NrZ1Oy5kyq5dcv/sox1cM=; b=WsK/hpC+t8YXyMewhy6plzAW7Ylsb+U58FHaRwOii72EBJKzSYqTk8Nc/pMYR96g1s YORAp7CE7IVplUSfc4B7h0k3wemanDS4rlvcpF3aH+ewBgTdytV0S6ARNt93fKrmk41w Z5ErgpTGf+yLi38q5KGb+49vjRiIl4bb8XM5ij01/nah3R4RayqpqYYal6AW5YjJpnNu OhLxyHzOSgBtHa6OtlW23vkGxkDnpFJRnl8wF09mUg25ucW80SfrJ2mjdAwapTgSIffk oGdaFHnrMHa6b/WmjvcUCLs3vWcLx+gaZWpZl9MaE7fQEr/tfHbGempVSn/5eD1a+ARO b/Sg== X-Gm-Message-State: AOAM533UVNT0ZsvrcummXKqg1fmmfb0pV5VHqaDC5O3p5OkHy/Tv5VnU BxYKqA0ZtIGVEYBjGAvJL6M= X-Google-Smtp-Source: ABdhPJyMpc9ZRRvjT/31fMFhXdGmEUVQmt01comyrO0PNewJS14lAD4uMsVXhxzZiB5iAWsGXrGoZg== X-Received: by 2002:a5d:43cc:: with SMTP id v12mr55001311wrr.319.1609798359597; Mon, 04 Jan 2021 14:12:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 08/15] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Date: Mon, 4 Jan 2021 23:11:47 +0100 Message-Id: <20210104221154.3127610-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b36b59c12d3..ccdde0b4a43 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,7 +19,6 @@ #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL -#define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -81,7 +80,7 @@ =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798366; cv=none; d=zohomail.com; s=zohoarc; b=PXV7YRrRpBjiiPbyKY+FWawh7q21MDs8kpMU04x+khdXg7c8kjZwVd+3Eq65rWsFzTndNwR8hkHVeACDUgto9e5tS4EikXqAeMklknuJtXwZDu4Ao6BDNj6mRTxqzu4lvfXL7cKa9bPV+RVolF46cA7Vdcj7cI8F9YYAdtfz8iM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798366; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R7Zokvaf4P4DDS/Ik2Al7Dbfod5TeXUavdYyR3ya+5E=; b=NqSFp/vYFuRbTh78bnPGlxdWOhSbwvXG+nmxGEUs0ABjgRcGwxo4MRiBvfr8U/Ht4x+QPEZImKjoqGHmDo/ExHmXG9qaywwmg9A3P5k851IGy7kLYaIjgq8IUc/PH3sBCdKQeHsLJ2Xs3qswF5aCSYukYFo3ibCQbPQtYTUphTc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1609798366814268.58023834460687; Mon, 4 Jan 2021 14:12:46 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id q18so33691014wrn.1 for ; Mon, 04 Jan 2021 14:12:46 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id u26sm1148256wmm.24.2021.01.04.14.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R7Zokvaf4P4DDS/Ik2Al7Dbfod5TeXUavdYyR3ya+5E=; b=MZbkZF26uB+3tr8PXNXP86R9z7n3OhJf14S1iZdw0jwtsK3Pid2k7rcwZuSiGXSyTL bXe/csqdQ0T4Tcn8/gyCXArnUvQn6pmz6l+49h0wYvmCohTBoHMERcvGOXor7VjpsknG FUeL1tsB8WyjYb4fLKWFb/c+KOzLrBhA0/QkJE/uVCwIWyNSAgHZjMR60oKXu0+ipdKX QNUTZKudWyP3LMpYwtTope6lqQIz8GsOp9D95i0s/BWzZnqaiC/ekmAn6fKfJUKLvbVh 14r10igKs3V2tkp9ztwBIjoSraYBvsnIb67G6SHpAKPlp4WFoQqJdG9Mzg7VwuHHUn06 tqTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=R7Zokvaf4P4DDS/Ik2Al7Dbfod5TeXUavdYyR3ya+5E=; b=SaxZ3WnRzke5dKfJRjZjbWVk/hoTOdcOpySb9gzvs2APYQDBpws5W8L90Y8EQQiewz mHa+s575ZGbU5+eos6EtvnkSr8xirfnAV5Z01gCCoejnMXtyNLcS06XG8uHUGReJLuvm lgj8ueWahR6QuZufnGeN0NNVlITgc5BiHzGegerJ/57FlgC3e4aX9ujhYFQzHklOhtrN fLftWpPZ27iKebmi1a6ZM1iOehK+du3EPkM7WcrPqlGLV69KGoQkW3vJydcBgDy0cFAD W0Fub1FllQju3uFvyzlaXujJKsVTYyI0u5yCcS6LMmZP6BuK7QKt2kEXKF0/E/ZleGDP rjPw== X-Gm-Message-State: AOAM530nEjxLF+rfDICknxW/vRVEkZG4thEqmwmZffidV+9tNY+g7N/K ZgQ0EvCQhuyaRVIom0VLCZY= X-Google-Smtp-Source: ABdhPJwAis58vSm7ZKecqPQC0BZoKBIV3xFktINRlCsnNue7ZCk9QhLMBkSo1iuMj8UgVpUqBG35dw== X-Received: by 2002:adf:9467:: with SMTP id 94mr84116673wrq.235.1609798364989; Mon, 04 Jan 2021 14:12:44 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/15] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Date: Mon, 4 Jan 2021 23:11:48 +0100 Message-Id: <20210104221154.3127610-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ccdde0b4a43..b71127ddd7c 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -20,7 +20,6 @@ #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL -#define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -84,7 +83,7 @@ =20 /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) -#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798372; cv=none; d=zohomail.com; s=zohoarc; b=MFLClG9JeohzllpnRGEB6LEIQwfRpJxVyBLfd6K8vZID6Rpv6/GPCPgnQlmcj6EdJriYpNOG1QVKrbyN7i3Cfdg+lpg8PiHYOoni4WBaziDF0bj3dsyetbqCS6ah+l5pt/qRlxuMD4bN3Tu1nrWHIaVPFuR14ytVOUlvTlcu5MQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798372; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b89sinWdwnRaR4NOd/DWOz5P627eErMVEbtVQAm5vR4=; b=esAoyAZsTQcYDeIqjVPllqWOmRnXNRzZoFYFg45ym7hMN3yZhM/EkB+MzrwAlhbEvmYX8YGv4/9GOnIZ2ROrIVxC0DxaYkN7ZsQcyU7Wi4Ke6lrAYdqooPT6M+JfobrQM45kxRnEJm41jtBirYvd/I8AVYck0qWcNhuN3ZuUD6Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1609798372164492.787575563827; Mon, 4 Jan 2021 14:12:52 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id m5so33594321wrx.9 for ; Mon, 04 Jan 2021 14:12:51 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id m8sm1021961wmc.27.2021.01.04.14.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b89sinWdwnRaR4NOd/DWOz5P627eErMVEbtVQAm5vR4=; b=mFQ66HgUEH1VSy7mQoonZ6iC92jq6SdwfXdQ5Nxf5fDEDXepk+1HxvHqAJteeLSbly jBKbwBvdO6zTIY3ZnwZpTB45rnm95qpc8kXk1jJsG8Y2Si6t92rInjLkGp5IbRKMS/Mi EQgzp5/nNtMcBwySLyuUL0r/uXLTmhIwQJtpW/dadfupidr9nmDSqagwu2rQT8eSqesX UQRpomHH94cTXKc3oVVrH7PcRsuWif4DUFZewadI4t27lkVWLiO6/Zs6iGdzrrPvG3QB u9Jgf1J500rvRoCutiteYmKlaUy1bgQ48pxB6hiKcO5A8rbbAA4YrsWRsZtI9xXPuGEP nmBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=b89sinWdwnRaR4NOd/DWOz5P627eErMVEbtVQAm5vR4=; b=Hum+mmEaFN/VXuc0dc5ix4hlHd67n2T/Xd2HSwlT8MXJQhvE27pHQR1raRa1EQ6hb0 oY4AILLgK7NNaQj+7LmgFQmRgwlR6Baa492LeuW/szCw1uKA6kDzrEkOjvhxV8fkdwu6 KwdLEILctUTPhHmXs2YNKwAdQag5x4HRCXQ+WXHJQc5FngBSvj/3Fr70kG5r5Ub243bK hNm8kSr/TPHaquqBKhMjf9JYL54cLpp1QR8XeUBdF9b1ZorgRU4Lym66JXjpkS6TusG2 brjByCRLSmGHxniP0aOXR501pjP9vD+vOPvU9rdgTABsVMMPgKbgwwz0gRBc6hkU3twZ qnxA== X-Gm-Message-State: AOAM532F5lSWgKJhhes6Hhuhs7Mt0aumycPW0xzSggRNmxsGe8j2D75C 5gtdFhQIJ4oe4OTZGnFgSus= X-Google-Smtp-Source: ABdhPJyZzr40x+ZZbPMqjzlXIzRjSJz5ZeXla1+uHP/pg2bEXS5guMqjKr/y4nyNnDsdWqqviFXVDQ== X-Received: by 2002:a5d:40ce:: with SMTP id b14mr80470579wrq.350.1609798370305; Mon, 04 Jan 2021 14:12:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 10/15] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Date: Mon, 4 Jan 2021 23:11:49 +0100 Message-Id: <20210104221154.3127610-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 3 +-- target/mips/helper.c | 6 +++--- target/mips/translate.c | 2 +- 5 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index e4d2d9f44f9..3466725b761 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS64R6) { + } else if (env->insn_flags & ISA_MIPS32R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b71127ddd7c..fea547508f0 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -21,7 +21,6 @@ #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL -#define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -87,7 +86,7 @@ =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index f0831379cc4..e400166c583 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,8 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/helper.c b/target/mips/helper.c index 87296fbad69..5b74815beb0 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 9fc9dedf30d..fc93b9da8eb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | ISA= _MIPS64R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1609798377; cv=none; d=zohomail.com; s=zohoarc; b=WOqBjlqomMUeK9f2VohjAWZ6/IFdsa53MxJy+reCN8N6HICcPZSdP3acL9QJvzwlB2qzJHyPwG18vP9PY9pp4uBzEt8hvei1dHmlicwlcLT5DQaEDOkZRbhE1CXlAUpw99BkwsTnXVhlqSan8S30QnYW7cT9VLcEujxCQBWJoDM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798377; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U1becq45UPDqSn7+EhIiJXXnxLnIRFVYNM6dDyz1HXk=; b=ImmvkniPnyq5hgultqGC+tGtp7gO6AdkhByZYYwBlp3MCy7uZ1cEK8VFrjFQn+YZWxlYHIW9tH+ZEfkzdd/ZUEwUhg+h/83R55OinUnipZ3qNsSoxD6pApQLMoart8h4pGh6d6EKZU5D2f10u+sH+MQNL1bmXRbz7Z7vVJGMu/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1609798377483159.21726883718213; Mon, 4 Jan 2021 14:12:57 -0800 (PST) Received: by mail-wr1-f48.google.com with SMTP id d13so33608893wrc.13 for ; Mon, 04 Jan 2021 14:12:56 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id r15sm91888771wrq.1.2021.01.04.14.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:12:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U1becq45UPDqSn7+EhIiJXXnxLnIRFVYNM6dDyz1HXk=; b=N81PYBGArNHD5Ww8H1IK709UhOVM22hQ9Zq3TcQ9GrO+St+/0GNeffhEz9ECEdSnHL 3GFk+gq972pjmjBrC6lelpet2uWLvKefhy9zK/hFrbTmzH3RHtr1YYlfpCaYLM/dCWmX Me8aMTWfo1T8FaSz/j6Xr3cztewOHTHbfSQFRYNnwSkbkWOuYwAl81BVsGYzysE5+V8E zXM5tI8hdx5XzPsHCwD+LMqV6HB1DJaUQX7W+RNSv+ltHXNoEUVkBlXJ+UK1zFDcRPpQ z01pQeRw3ZSTz3bq1hCnNVgopNox+KeOl5VXAonGffI5KQotoxoxvR8QP2V8vMtj52fn DxDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=U1becq45UPDqSn7+EhIiJXXnxLnIRFVYNM6dDyz1HXk=; b=KxeSp3+2qzRcxY2oxKr0JX2+wxKl5lqp6U0O8+i3GKaxbhMKrSXNghpaiymDvpVPng q4G6Y1bp+K/E7G0oKKfuQkfm8fjZIbr0jogV37EwHOZFUXk6RULzxBTpAkLrdI4RmFNL yBcNFMY8UReCjKgzu4q5k9MqLwRtHzxkx+WNQ0FVj2N/xi2MK/qQY+68uEHfNslD+Hi4 SCWzbXetpVlbg4IsLlslqYowQPl4lheUe+rIu1inKTiC/4YZT0o6EIMqWiDam//aEWk2 VHTSn0VQn1k3QoMWyeDNQ4h9gknS/jjlJaTJ99YxOLU6ZXNIAOHr4vYdGd9/IMrpx+u3 5t2w== X-Gm-Message-State: AOAM532mq1frBehC6OILWmOhLHjE8TdmeJ5wP5zM6NtCEkM72bYvAFa/ MuQjmGvHQKsQ2+YfggOH0KM= X-Google-Smtp-Source: ABdhPJxssliuFblttFZcZ1LyHjUr08MTAA0x1KCO8A+uMBg9o29JRPrwv45T67axcXQriWg2QqPQcA== X-Received: by 2002:adf:dc10:: with SMTP id t16mr77561595wri.345.1609798375624; Mon, 04 Jan 2021 14:12:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 11/15] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Date: Mon, 4 Jan 2021 23:11:50 +0100 Message-Id: <20210104221154.3127610-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 +-- target/mips/translate.c | 54 ++++++++++++++++++++--------------------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 3466725b761..94910f75a61 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -411,7 +411,7 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |=3D MIPS_HFLAG_COP1X; } - } else if (env->insn_flags & ISA_MIPS32) { + } else if (env->insn_flags & ISA_MIPS_R1) { if (env->hflags & MIPS_HFLAG_64) { env->hflags |=3D MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index fea547508f0..a7048ffaffe 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -16,7 +16,7 @@ #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL -#define ISA_MIPS32 0x0000000000000020ULL +#define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -69,7 +69,7 @@ #define CPU_MIPS64 (ISA_MIPS3) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1) #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) =20 /* MIPS Technologies "Release 2" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index fc93b9da8eb..a59fbd94bac 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7411,7 +7411,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 switch (reg) { @@ -8179,7 +8179,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 switch (reg) { @@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -11006,7 +11006,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_DERET: opn =3D "deret"; - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -11021,7 +11021,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_WAIT: opn =3D "wait"; - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -11056,7 +11056,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, } =20 if (cc !=3D 0) { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); } =20 btarget =3D ctx->base.pc_next + 4 + offset; @@ -14425,7 +14425,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int xsregs =3D (ctx->opcode >> 24) & 0x7; int aregs =3D (ctx->opcode >> 16) & 0xf; @@ -14675,7 +14675,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) ((int8_t)ctx->opcode) << 3); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int do_ra =3D ctx->opcode & (1 << 6); int do_s0 =3D ctx->opcode & (1 << 5); @@ -14819,7 +14819,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) int ra =3D (ctx->opcode >> 5) & 0x1; =20 if (nd) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (link) { @@ -14840,7 +14840,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -14891,7 +14891,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) gen_HILO(ctx, OPC_MFHI, 0, rx); break; case RR_CNVT: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); switch (cnvt_op) { case RR_RY_CNVT_ZEB: tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); @@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, D= isasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -15831,7 +15831,7 @@ static void gen_pool16c_insn(DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -16175,7 +16175,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) case CLZ: mips32_op =3D OPC_CLZ; do_cl: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: @@ -16202,7 +16202,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) mips32_op =3D OPC_DIVU; goto do_div; do_div: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: @@ -16221,7 +16221,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) check_insn_opc_removed(ctx, ISA_MIPS32R6); mips32_op =3D OPC_MSUBU; do_mul: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; default: @@ -16369,7 +16369,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) if (is_uhi(extract32(ctx->opcode, 16, 10))) { gen_helper_do_semihosting(cpu_env); } else { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { generate_exception_end(ctx, EXCP_RI); } else { @@ -24889,7 +24889,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) switch (op1) { case OPC_MOVN: /* Conditional move */ case OPC_MOVZ: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_LOONGSON2E | INSN_LOONGSON2F); gen_cond_move(ctx, op1, rd, rs, rt); break; @@ -24902,7 +24902,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) gen_HILO(ctx, op1, rd & 3, rs); break; case OPC_MOVCI: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); if (env->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, @@ -27577,7 +27577,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MADDU: case OPC_MSUB: case OPC_MSUBU: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_MUL: @@ -27594,7 +27594,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_CLO: case OPC_CLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, op1, rd, rs); break; case OPC_SDBBP: @@ -27605,14 +27605,14 @@ static void decode_opc_special2_legacy(CPUMIPSSta= te *env, DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; @@ -31025,7 +31025,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_CACHE: check_insn_opc_removed(ctx, ISA_MIPS32R6); check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } @@ -31036,7 +31036,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); /* Treat as NOP. */ } break; --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id j2sm92145503wrt.35.2021.01.04.14.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:13:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XnjdGrLq3Lb9SW/8nNHP28HRwNkyifegoyRQR3pYkYc=; b=PQMRVoQ24gvQXvPGst7S7Ok8+ijffLcQW6UDF/nILulSnQo28iCPQYgop+62ECUaRM jY4u42xqir7tu0YXTbVtHskXlcRW3FKoo/2jSkUnBIgCfjSJRI9PFVsF/PRVHCHPsBlV vE4er/Td5lCKVjcyIOGNwmGlZvIWLBnmEhrpH1qlvfrVdUd7GoC6hbEO+E3Ig9JkUaxt 6/t0mb4sCv/XcELCuM7ojxmOOyWzsSKz4oBlrbEUpYcJveSYl+EFXDamddcaI1aOk40E T+uuWxArlx33LtenYs2mATYhu9wg8ouPYvJP9vIYjPRxpSkwHHxpTcRrIqDSBxEnB06j D/hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=XnjdGrLq3Lb9SW/8nNHP28HRwNkyifegoyRQR3pYkYc=; b=D5Fp+Kp5Y82mlTIj8Z6BBePZ9zEgSR3WGHQXLQIUZPz2rFBD2dITlZWv7tqolfyUhs za9j4Lf5IB8z3TKSgiWTwolLpQNEmviBRyIM4gMLvpVyaaMgaq+MIsZ/2A+v2l6YJN2E xyi5d6IOmubVFkdgAEHPVGGELbH3SUk8aBVARAK3S/719dpfILLpTApwrXqjmifgEVf5 rkgNyPlAzGigOwhWOWD02r/nIlreX9Gv3PMWE8Waj+DG3UPIFd4a+bMRmNkqUOhTBHUU 7WCYs2vzeZ8f+HxpTJn8DXxU8vRCw873b+spIeaQNZ6ugLpkIsU2WgZRf29NTndZf04p L7WA== X-Gm-Message-State: AOAM531eNt402iWZCUTiRgrwxovw3DS/jxiUllAfY//c/zpsPNODidnm /Yz1X3s7Wf6B4TQd/PB2HKM= X-Google-Smtp-Source: ABdhPJxU+XhSjJ5137mI4WqUHG5jHUXv8KH7My1UYV+HMbgqJuYps27tLacNhUVf1Q93/3HB+GBMYQ== X-Received: by 2002:a5d:5442:: with SMTP id w2mr81696385wrv.418.1609798381007; Mon, 04 Jan 2021 14:13:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 12/15] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Date: Mon, 4 Jan 2021 23:11:51 +0100 Message-Id: <20210104221154.3127610-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_timer.c | 4 +- target/mips/helper.c | 2 +- target/mips/translate.c | 138 ++++++++++++++++++------------------- 6 files changed, 76 insertions(+), 76 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 94910f75a61..23ae31ef989 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -407,7 +407,7 @@ static inline void compute_hflags(CPUMIPSState *env) } =20 } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |=3D MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index a7048ffaffe..d1eeb69dfd7 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -17,7 +17,7 @@ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL -#define ISA_MIPS32R2 0x0000000000000040ULL +#define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -73,7 +73,7 @@ #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) =20 /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) +#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2) #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index e400166c583..748e1c664f1 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -384,7 +384,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.frdefault &=3D interp_req.frdefault; prog_req.fre &=3D interp_req.fre; =20 - bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || + bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS_R2 || env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 5ec0d6249e9..70de95d338f 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env) static void cpu_mips_timer_expire(CPUMIPSState *env) { cpu_mips_timer_update(env); - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause |=3D 1 << CP0Ca_TI; } qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); @@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t v= alue) if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { cpu_mips_timer_update(env); } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause &=3D ~(1 << CP0Ca_TI); } qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); diff --git a/target/mips/helper.c b/target/mips/helper.c index 5b74815beb0..98d6ecaa65e 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -431,7 +431,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) uint32_t old =3D env->CP0_Cause; int i; =20 - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { mask |=3D 1 << CP0Ca_DC; } if (env->insn_flags & ISA_MIPS32R6) { diff --git a/target/mips/translate.c b/target/mips/translate.c index a59fbd94bac..9c71d306ee5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7612,7 +7612,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; @@ -7660,27 +7660,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; @@ -7696,7 +7696,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; break; @@ -7791,17 +7791,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; break; @@ -7837,13 +7837,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); tcg_gen_ext32s_tl(arg, arg); @@ -8357,7 +8357,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; ctx->base.is_jmp =3D DISAS_STOP; @@ -8403,27 +8403,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; @@ -8439,7 +8439,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; @@ -8522,21 +8522,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -8581,7 +8581,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; break; @@ -9120,7 +9120,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; @@ -9165,27 +9165,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; @@ -9201,7 +9201,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; break; @@ -9294,17 +9294,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; break; @@ -9339,12 +9339,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); register_name =3D "CMGCRBase"; @@ -9847,7 +9847,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; break; @@ -9892,27 +9892,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; @@ -9928,7 +9928,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; @@ -10015,21 +10015,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg= , int reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -10074,7 +10074,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; break; @@ -13453,7 +13453,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) * The Linux kernel will emulate rdhwr if it's not supported natively. * Therefore only check the ISA in system mode. */ - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); #endif t0 =3D tcg_temp_new(); =20 @@ -16269,12 +16269,12 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) switch (minor) { case RDPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rs, rt); break; case WRPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rs, rt); break; default: @@ -24984,7 +24984,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* rotr is decoded as srl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_ROTR; } /* Fallthrough */ @@ -25010,7 +25010,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* rotrv is decoded as srlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_ROTRV; } /* Fallthrough */ @@ -25083,7 +25083,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr is decoded as dsrl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTR; } /* Fallthrough */ @@ -25101,7 +25101,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTR32; } /* Fallthrough */ @@ -25133,7 +25133,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* drotrv is decoded as dsrlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTRV; } /* Fallthrough */ @@ -28594,7 +28594,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_EXT: case OPC_INS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_BSHFL: @@ -28609,7 +28609,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bshfl(ctx, op2, rt, rd); break; } @@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); op2 =3D MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); @@ -30741,7 +30741,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_SYNCI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* * Break the TB to be able to sync copied instructions * immediately. @@ -30858,7 +30858,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_DI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rt); @@ -30869,7 +30869,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) ctx->base.is_jmp =3D DISAS_STOP; break; case OPC_EI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rt); @@ -30890,11 +30890,11 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) #endif /* !CONFIG_USER_ONLY */ break; case OPC_RDPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rt, rd); break; case OPC_WRPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rt, rd); break; default: @@ -31056,7 +31056,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MFHC1: case OPC_MTHC1: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* fall through */ case OPC_MFC1: case OPC_CFC1: @@ -31250,21 +31250,21 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) switch (op1) { case OPC_LUXC1: case OPC_SUXC1: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_LWXC1: case OPC_LDXC1: case OPC_SWXC1: case OPC_SDXC1: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); break; case OPC_PREFX: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); /* Treat as NOP. */ break; case OPC_ALNV_PS: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_MADD_S: case OPC_MADD_D: @@ -31278,7 +31278,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_NMSUB_S: case OPC_NMSUB_D: case OPC_NMSUB_PS: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id u66sm1264709wmg.2.2021.01.04.14.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:13:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lb2RZp/b5dZkU06uPS3u8Lf6yQtKDoxin1D5fr6aVsg=; b=UTU3FK1HtbBl3rg7EkbGFAJ6TfVzTXxOxgCyUrMdjffFP4VOGHL29DyXG5BRMDMMJl CGi1N6USF6rieGDkUp5LXrwwjbe6n8Y40/t74OpPdA3sICRYl1q4gYkWOXk11vvnCJpN jZuQUxnBreXdf39WjrSvnjwXdTPyntWpyVHFJtFgqxNOjDsME6EoKon+OxXLWcyzkkUk +qqZ8RfSTrW3+kq27z19Stq3Co2PY0+H0Gtw49MeBhNkdp1NhPCxKVbuf3pJHgIPV9JB 6yCMP4f0atTeyUZi3BQhtKT9Q4Ms7ufuIZXKCTTjD1uu5bsE8qCWjbqqz+HaFPj6dqEb uo4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Lb2RZp/b5dZkU06uPS3u8Lf6yQtKDoxin1D5fr6aVsg=; b=SpxgMcm4M1aK1pVrQkIQQcK8rv/BSPUAkzpyxEfXiSXB3crAk9e6tKAXScDs7fuh5z 33CAhmLF6wkbY9b6vEf1mLz5TzVKXhW9LRVN/V7BRUmE2+8RlACjhaqp0SdhxZJ5BoYx pZtseMrifmKAUb3KkQ5Ef8ALtYrega2GgxXm21B70JjvcbHauLs3GeIaVl2pwKga4tfp wNSqYbYLJQ7owXBub/HBBgT9GJPdDdHnFaICGhbjq+y4DEJUltpKPrk/sDxH/DH8VQOX uXl8LIsWMSCuGwzXWvBxE8o7Wuzc3gQKyAwwM2WLBsgX9beGPk20AxGV8KZaMAuhIN8+ juEg== X-Gm-Message-State: AOAM533f4jfU62BbP6WXhk9RnmDv6d+ObP/AvAhccdnvda2eupcEk5j8 GEdVS40KyzMmja4doOVtbuY= X-Google-Smtp-Source: ABdhPJwCwKGvxTFO88kjPjeU6cxlRMLo10cUttc7MHHeG4qNKS9urwckYKVzFjQJmJAjEU+z+IeUlA== X-Received: by 2002:a5d:660b:: with SMTP id n11mr81968492wru.407.1609798386313; Mon, 04 Jan 2021 14:13:06 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 13/15] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Date: Mon, 4 Jan 2021 23:11:52 +0100 Message-Id: <20210104221154.3127610-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d1eeb69dfd7..12ff2b3280c 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -18,7 +18,7 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL -#define ISA_MIPS32R3 0x0000000000000200ULL +#define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -77,7 +77,7 @@ #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3) #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798393; cv=none; d=zohomail.com; s=zohoarc; b=GRrShLWSwnhhXTi9a2fTQ9I/iwYWguEYa2OYRyXpYu81g1EbR0p4UJiooBASUKHLEUE8nkDZ9XSYPVmIZkWP5wIKFxgdoRXZMWegnWNQeGW3rJG2PlZ8+zylxNWKfdV8xyKrD0eyGCw6ArxamFuW8HbiqgwQtDXcvcR5UcUrHiI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798393; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=l1w3yrD6Xzrx67l04pPoYDp8gom3Vu8h3R+Nb7NOQM0=; b=lNVpgy8B1d5/nvKC+kstwmANwIfoz+vu3h6+Qlc+DJ+ixjr3DV/xiGY2FZkKlPY9G6T5p8kI17b9w0xE8o3ECnl6fWK43BxuWi2OufsADiOCXbcdGdwj42tcbPPyEiSp+D0c/xX1SlMW+VeMt3uzc3BAbtfLZ9xRnI4kDO4tgAE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1609798393346284.546640477575; Mon, 4 Jan 2021 14:13:13 -0800 (PST) Received: by mail-wm1-f51.google.com with SMTP id a6so621857wmc.2 for ; Mon, 04 Jan 2021 14:13:12 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id z15sm95495737wrv.67.2021.01.04.14.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:13:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l1w3yrD6Xzrx67l04pPoYDp8gom3Vu8h3R+Nb7NOQM0=; b=tJGaENIrgnvqwq0rqeDF4WAjhLBQ7tzLg4KijZom/fAp70OgR6YdblD1lqI28Iqr0k lAdMdohd55XZMjJOfd6tZexYqxaqf2Ly8f07qvEP+qN+pY4k3tzzUePk6ZXkiPLCKgMf 4grkYighl94t1r0V/v7A+OpmEAZwYfkJQZiFt16TjykHJy++fGNZwqBNZk68a6W0bQy1 zvwnfrporadxYRj1PyBhwBmhxuvfWa7pwVD9BLZxvXyNZP/STZX5HyYkRZPSde95szUz mkzqnJrzc+PdhDtaiqShLA9f374iPOSsuU/lFsyOxrnRUNuZuLHmgUj1kme/VKOfxAP5 1hiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=l1w3yrD6Xzrx67l04pPoYDp8gom3Vu8h3R+Nb7NOQM0=; b=AIUNJJuuwE78NyK+VawC4qezR/7hGuDAPeCcoar33kzuYf/pfWwmsopR1JQu2RSByE DUQ53HHassb9BWzEpfj8RwzBUavlh/iWYgu5N2gtjbPpgPLHhLD40vNzsV5C1JUZhq19 jK71MtFXy2E4h5Uvm73hTPxucZbj1YJz43MfMbzD6rbilOQZgBhL4qa0KTN4zsKC9x6X i/xKWzfP/H3OU6CjJv9l+RHNEKE+MoT3N9Q3Zg8X9a3wca+caJoRYHk+d9WQE4va1uW2 osOIIXekmz6RT2WWaiYCK/um8XSYZlj3KkHcLG0u11mMIX6lDSxiCI5SqvSBq8hu533v OLZQ== X-Gm-Message-State: AOAM531WaLGS2bxlnrzOME9lZOKw17dx3CILiTJAEVYOxVH1wDCzOu2t YbEMaTzP2IlxLfXSkfZbmEk= X-Google-Smtp-Source: ABdhPJxSP9WziwuPE2JwUY/zEamaTZXb9yp/9L+BP0pqpUYL8FdZc8RaxDd8bFAuNolNFgAZomfz4A== X-Received: by 2002:a05:600c:214a:: with SMTP id v10mr778977wml.138.1609798391518; Mon, 04 Jan 2021 14:13:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 14/15] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Date: Mon, 4 Jan 2021 23:11:53 +0100 Message-Id: <20210104221154.3127610-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 12ff2b3280c..181f3715472 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,7 +19,7 @@ #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL -#define ISA_MIPS32R5 0x0000000000000800ULL +#define ISA_MIPS_R5 0x0000000000000100ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* @@ -81,7 +81,7 @@ #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5) #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 9c71d306ee5..83fd6c473a5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -10993,7 +10993,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, if (ctx->opcode & (1 << bit_shift)) { /* OPC_ERETNC */ opn =3D "eretnc"; - check_insn(ctx, ISA_MIPS32R5); + check_insn(ctx, ISA_MIPS_R5); gen_helper_eretnc(cpu_env); } else { /* OPC_ERET */ --=20 2.26.2 From nobody Mon Feb 9 14:54:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1609798399; cv=none; d=zohomail.com; s=zohoarc; b=c0TcQwVLJ0nVIWtr5/R7rV/+P32kGJm0COuuxKTep5Xmzc5ziqYffqCBljh1Z3R3A6EBTTDBPaBQtBu31Jqabs1Qf5dugULr+Mti33bnqtzD4+cioYw6yKd37sJrT5jWQMV9u3hAgrwlS1qXOen6vH3bespTEc4XvssDufu7y7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609798399; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eYHoCZ5M4sTy72CUZDyS74w0wjbAQb6bcc2irZaNU9U=; b=h7kDN7MsBHpWRBOOakXq2RwvzmT0z+LEND0+680id8zeXHCC9M5J3x+mG+ZZGwCID2+O94cSEUArGgHNVc3ITOWefJKJcKCQmWhUPNYdZmcF6++BdAMHMvw9Jz0CRt5mT1kQkF3bJheYqdAjAvdsQYe39FPpZbBLZ1meZXEwM5s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.zohomail.com with SMTPS id 1609798399348706.9174020726217; Mon, 4 Jan 2021 14:13:19 -0800 (PST) Received: by mail-wm1-f47.google.com with SMTP id n16so596372wmc.0 for ; Mon, 04 Jan 2021 14:13:18 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id p15sm88512235wrt.15.2021.01.04.14.13.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:13:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eYHoCZ5M4sTy72CUZDyS74w0wjbAQb6bcc2irZaNU9U=; b=SIFvkT/p6x2Sc1SQXfZXa9Oj6IY+uO3ORS3WO/ojDiL9Y2cWhKO8l9fVYURWD20ziw dG6uPIo5rgN379orGDyM63owUC/+9GZbS3SeqIac1gSjaNUenrbgoh8OiSAPUkjfXDlg Sm9QGyC/imJS06gLWt1kdWnRfO71PWEiB1UugbUK56l7/vTuX/KSRbtZ/9V7By57SMQ1 uEYbsRJ9llEfwjhMDg5G7O7hjSJZ0Y/HtCVOi+z1nuoolv0L6er8Z4rEreqxjva5Qe9l wRNrDokeo8WaRs4D3k+HqAr4n2VDyAPE4Iu+g8eIxVxRmAFNNuRGLm2a/JGYLmW6uTAs tsvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eYHoCZ5M4sTy72CUZDyS74w0wjbAQb6bcc2irZaNU9U=; b=PI8APJ6VRe6tjJ1BRPPtVJnj6GR4bRkv+5vB4Cmymni1LC+H1BHxFfMxivu5s/hHYC 0bMTxobL0NGB6XRFRmT19GR36/QFDkmjmPCuZ0zP3XXDRL3JLcidFHK+2BCq5NP460TJ fFqNQJGUvRxHwRjMoKPUrRIQNQEgqslC13TVfgdCpdWYfzj67K77FwCMYsGQ1Pc+CrlQ MZl6CcMXlBLcVmmk9qun+DULYfO7FTCMpRM22US+a0QbuZfCijZAT18qYc0UM4NH3HBy d8wSG+d6da/AabNj1SxYlIHrQ8EoFHXcaHHeH1IQ44aQlfESu+eYO6oKHRbTkYUzXXA/ Hskg== X-Gm-Message-State: AOAM532LlrwVWQeAY/mC3nEVcm/90Nb2bRpfTdxKDYtBdrUtO3V5K93T 7LxkTMZJqayQJkQL7VnRdoM= X-Google-Smtp-Source: ABdhPJzHHkTxQ9CSbBByJx5OBs1dUBaLH6GYcaAEMOe49/oB8bXNJ7jvzFtnUkb68TdkM30Nz7PNfg== X-Received: by 2002:a1c:2785:: with SMTP id n127mr798922wmn.148.1609798396841; Mon, 04 Jan 2021 14:13:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Richard Henderson , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 15/15] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Date: Mon, 4 Jan 2021 23:11:54 +0100 Message-Id: <20210104221154.3127610-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104221154.3127610-1-f4bug@amsat.org> References: <20210104221154.3127610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 4 +- target/mips/mips-defs.h | 4 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_helper.c | 18 +- target/mips/cpu.c | 6 +- target/mips/fpu_helper.c | 4 +- target/mips/helper.c | 10 +- target/mips/translate.c | 426 ++++++++++++++++++------------------- 8 files changed, 237 insertions(+), 237 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 23ae31ef989..77a648bcf9c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS32R6) { + } else if (env->insn_flags & ISA_MIPS_R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || @@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env) } #endif if (((env->CP0_Status & (1 << CP0St_CU0)) && - !(env->insn_flags & ISA_MIPS32R6)) || + !(env->insn_flags & ISA_MIPS_R6)) || !(env->hflags & MIPS_HFLAG_KSU)) { env->hflags |=3D MIPS_HFLAG_CP0; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 181f3715472..97866019a72 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -20,7 +20,7 @@ #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS_R5 0x0000000000000100ULL -#define ISA_MIPS32R6 0x0000000000002000ULL +#define ISA_MIPS_R6 0x0000000000000200ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -85,7 +85,7 @@ #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 748e1c664f1..19947448a25 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS_R2 || - env->insn_flags & ISA_MIPS32R6; + env->insn_flags & ISA_MIPS_R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index 36a92857bfb..aae2af6eccc 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -527,7 +527,7 @@ void helper_mtc0_index(CPUMIPSState *env, target_ulong = arg1) uint32_t index_p =3D env->CP0_Index & 0x80000000; uint32_t tlb_index =3D arg1 & 0x7fffffff; if (tlb_index < env->tlb->nb_tlb) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { index_p |=3D arg1 & 0x80000000; } env->CP0_Index =3D index_p | tlb_index; @@ -960,7 +960,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) uint32_t old_ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; uint32_t new_ptei =3D (arg1 >> CP0PF_PTEI) & 0x3FULL; =20 - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) { mask &=3D ~(0x3FULL << CP0PF_BDI); } @@ -980,7 +980,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) env->CP0_PWField =3D arg1 & mask; =20 if ((new_ptei >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptei =3D=3D 0 || new_ptei =3D=3D 1))) { env->CP0_PWField =3D (env->CP0_PWField & ~0x3FULL) | (old_ptei << CP0PF_PTEI); @@ -990,7 +990,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) uint32_t old_ptew =3D (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; uint32_t new_ptew =3D (arg1 >> CP0PF_PTEW) & 0x3F; =20 - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) { mask &=3D ~(0x3F << CP0PF_GDW); } @@ -1007,7 +1007,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ul= ong arg1) env->CP0_PWField =3D arg1 & mask; =20 if ((new_ptew >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptew =3D=3D 0 || new_ptew =3D=3D 1))) { env->CP0_PWField =3D (env->CP0_PWField & ~0x3F) | (old_ptew << CP0PF_PTEW); @@ -1026,7 +1026,7 @@ void helper_mtc0_pwsize(CPUMIPSState *env, target_ulo= ng arg1) =20 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { if (arg1 < env->tlb->nb_tlb) { env->CP0_Wired =3D arg1; } @@ -1075,10 +1075,10 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_u= long arg1) uint32_t mask =3D 0x0000000F; =20 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { mask |=3D (1 << 4); } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask |=3D (1 << 5); } if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { @@ -1149,7 +1149,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) =20 /* 1k pages not implemented */ #if defined(TARGET_MIPS64) - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { int entryhi_r =3D extract64(arg1, 62, 2); int config0_at =3D extract32(env->CP0_Config0, 13, 2); bool no_supervisor =3D (env->CP0_Status_rw_bitmask & 0x8) =3D=3D 0; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b2cd69ff7f9..136db626456 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -71,7 +71,7 @@ static bool mips_cpu_has_work(CPUState *cs) if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { has_work =3D true; } } @@ -287,13 +287,13 @@ static void cpu_state_reset(CPUMIPSState *env) /* XKPhys (note, SegCtl2.XR =3D 0, so XAM won't be used) */ env->CP0_SegCtl1 |=3D (CP0SC_AM_UK << CP0SC1_XAM); #endif /* !CONFIG_USER_ONLY */ - if ((env->insn_flags & ISA_MIPS32R6) && + if ((env->insn_flags & ISA_MIPS_R6) && (env->active_fpu.fcr0 & (1 << FCR0_F64))) { /* Status.FR =3D 0 mode in 64-bit FPU not allowed in R6 */ env->CP0_Status |=3D (1 << CP0St_FR); } =20 - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { /* PTW =3D 1 */ env->CP0_PWSize =3D 0x40; /* GDI =3D 12 */ diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index bdb65065ee7..91b6a2e11fc 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -145,7 +145,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, = uint32_t fs, uint32_t rt) } break; case 25: - if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { + if ((env->insn_flags & ISA_MIPS_R6) || (arg1 & 0xffffff00)) { return; } env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | @@ -172,7 +172,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, = uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask= )); break; default: - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { do_raise_exception(env, EXCP_RI, GETPC()); } return; diff --git a/target/mips/helper.c b/target/mips/helper.c index 98d6ecaa65e..d1b6bb6fb23 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -397,7 +397,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ul= ong val) uint32_t mask =3D env->CP0_Status_rw_bitmask; target_ulong old =3D env->CP0_Status; =20 - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; #if defined(TARGET_MIPS64) uint32_t ksux =3D (1 << CP0St_KX) & val; @@ -434,7 +434,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) if (env->insn_flags & ISA_MIPS_R2) { mask |=3D 1 << CP0Ca_DC; } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask &=3D ~((1 << CP0Ca_WP) & val); } =20 @@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 83fd6c473a5..e813add99c5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4014,7 +4014,7 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t= opc, } break; case OPC_LUI: - if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS32R6)) { + if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS_R6)) { /* OPC_AUI */ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); @@ -7399,7 +7399,7 @@ cp0_unimplemented: =20 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) { - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { tcg_gen_movi_tl(arg, 0); } else { tcg_gen_movi_tl(arg, ~0); @@ -7448,7 +7448,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; @@ -7964,7 +7964,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -8709,7 +8709,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -8980,7 +8980,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; @@ -9461,7 +9461,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -10191,7 +10191,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -10985,7 +10985,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, gen_helper_tlbr(cpu_env); break; case OPC_ERET: /* OPC_ERETNC */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } else { @@ -11007,7 +11007,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, case OPC_DERET: opn =3D "deret"; check_insn(ctx, ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -11022,7 +11022,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, case OPC_WAIT: opn =3D "wait"; check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -11050,7 +11050,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, target_ulong btarget; TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMAS= K)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK= )) { generate_exception_end(ctx, EXCP_RI); goto out; } @@ -11906,23 +11906,23 @@ static void gen_farith(DisasContext *ctx, enum fo= pcode op1, } break; case OPC_SEL_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i32 fp0; @@ -11938,7 +11938,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MOVN_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i32 fp0; @@ -11974,7 +11974,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MADDF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11990,7 +11990,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MSUBF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12006,7 +12006,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_RINT_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -12016,7 +12016,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_CLASS_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -12026,7 +12026,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MIN_S: /* OPC_RECIP2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12055,7 +12055,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MINA_S: /* OPC_RECIP1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12081,7 +12081,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAX_S: /* OPC_RSQRT1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12105,7 +12105,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAXA_S: /* OPC_RSQRT2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12207,7 +12207,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, case OPC_CMP_NGE_S: case OPC_CMP_LE_S: case OPC_CMP_NGT_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_s(ctx, func - 48, ft, fs, cc); } else { @@ -12450,23 +12450,23 @@ static void gen_farith(DisasContext *ctx, enum fo= pcode op1, } break; case OPC_SEL_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; @@ -12482,7 +12482,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MOVN_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; @@ -12520,7 +12520,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MADDF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12536,7 +12536,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MSUBF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12552,7 +12552,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_RINT_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12562,7 +12562,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_CLASS_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12572,7 +12572,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MIN_D: /* OPC_RECIP2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12599,7 +12599,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MINA_D: /* OPC_RECIP1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12623,7 +12623,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAX_D: /* OPC_RSQRT1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12647,7 +12647,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAXA_D: /* OPC_RSQRT2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12689,7 +12689,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, case OPC_CMP_NGE_D: case OPC_CMP_LE_D: case OPC_CMP_NGT_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_d(ctx, func - 48, ft, fs, cc); } else { @@ -13485,7 +13485,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) gen_store_gpr(t0, rt); break; case 4: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (sel !=3D 0) { /* * Performance counter registers are not implemented other than @@ -13497,7 +13497,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) gen_store_gpr(t0, rt); break; case 5: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_helper_rdhwr_xnp(t0, cpu_env); gen_store_gpr(t0, rt); break; @@ -16160,7 +16160,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) case 0x2c: switch (minor) { case BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_bitswap(ctx, OPC_BITSWAP, rs, rt); break; case SEB: @@ -16179,26 +16179,26 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, 0); break; case WSBH: gen_bshfl(ctx, OPC_WSBH, rs, rt); break; case MULT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MULT; goto do_mul; case MULTU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MULTU; goto do_mul; case DIV: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_DIV; goto do_div; case DIVU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_DIVU; goto do_div; do_div: @@ -16206,19 +16206,19 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD; goto do_mul; case MADDU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADDU; goto do_mul; case MSUB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB; goto do_mul; case MSUBU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUBU; do_mul: check_insn(ctx, ISA_MIPS_R1); @@ -16246,7 +16246,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) switch (minor) { case JALR: /* JALRC */ case JALR_HB: /* JALRC_HB */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* JALRC, JALRC_HB */ gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); } else { @@ -16257,7 +16257,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) break; case JALRS: case JALRS_HB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; @@ -16400,7 +16400,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) } break; case 0x35: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); switch (minor) { case MFHI32: gen_HILO(ctx, OPC_MFHI, 0, rs); @@ -16674,7 +16674,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) case COND_FLOAT_MOV(MOVT, 5): case COND_FLOAT_MOV(MOVT, 6): case COND_FLOAT_MOV(MOVT, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); break; case COND_FLOAT_MOV(MOVF, 0): @@ -16685,7 +16685,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) case COND_FLOAT_MOV(MOVF, 5): case COND_FLOAT_MOV(MOVF, 6): case COND_FLOAT_MOV(MOVF, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); break; default: @@ -16736,15 +16736,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_shift_imm(ctx, mips32_op, rt, rs, rd); break; case SELEQZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); break; case SELNEZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); break; case R6_RDHWR: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); break; default: @@ -16768,7 +16768,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) mips32_op =3D OPC_SUBU; goto do_arith; case MUL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MUL; do_arith: gen_arith(ctx, mips32_op, rd, rs, rt); @@ -16821,7 +16821,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) switch (minor) { /* Conditional moves */ case MOVN: /* MUL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUL */ gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); } else { @@ -16830,7 +16830,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MOVZ: /* MUH */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUH */ gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); } else { @@ -16839,15 +16839,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MULU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); break; case MUHU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); break; case LWXS: /* DIV */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* DIV */ gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); } else { @@ -16856,15 +16856,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOD: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); break; case R6_DIVU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); break; case MODU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); break; default: @@ -16875,12 +16875,12 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; case LSA: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_lsa(ctx, OPC_LSA, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case ALIGN: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case EXT: @@ -16893,7 +16893,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) generate_exception_end(ctx, EXCP_BREAK); break; case SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); generate_exception_end(ctx, EXCP_RI); break; default: @@ -16951,61 +16951,61 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) check_cp1_enabled(ctx); switch (minor) { case ALNV_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_ALNV_PS; goto do_madd; case MADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_S; goto do_madd; case MADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_D; goto do_madd; case MADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_PS; goto do_madd; case MSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_S; goto do_madd; case MSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_D; goto do_madd; case MSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_PS; goto do_madd; case NMADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_S; goto do_madd; case NMADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_D; goto do_madd; case NMADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_PS; goto do_madd; case NMSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_S; goto do_madd; case NMSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_D; goto do_madd; case NMSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_PS; do_madd: gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); break; case CABS_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond =3D (ctx->opcode >> 6) & 0xf; cc =3D (ctx->opcode >> 13) & 0x7; fmt =3D (ctx->opcode >> 10) & 0x3; @@ -17024,7 +17024,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case C_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond =3D (ctx->opcode >> 6) & 0xf; cc =3D (ctx->opcode >> 13) & 0x7; fmt =3D (ctx->opcode >> 10) & 0x3; @@ -17043,11 +17043,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case CMP_CONDN_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case CMP_CONDN_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case POOL32FXF: @@ -17069,7 +17069,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) mips32_op =3D OPC_PUU_PS; goto do_ps; case CVT_PS_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_CVT_PS_S; do_ps: gen_farith(ctx, mips32_op, rt, rs, rd, 0); @@ -17079,7 +17079,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MIN_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); @@ -17095,27 +17095,27 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) /* [LS][WDU]XC1 */ switch ((ctx->opcode >> 6) & 0x7) { case LWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWXC1; goto do_ldst_cp1; case SWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWXC1; goto do_ldst_cp1; case LDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDXC1; goto do_ldst_cp1; case SDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDXC1; goto do_ldst_cp1; case LUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LUXC1; goto do_ldst_cp1; case SUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SUXC1; do_ldst_cp1: gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); @@ -17125,7 +17125,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MAX_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); @@ -17139,7 +17139,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case 0x18: /* 3D insns */ - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); fmt =3D (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case RSQRT2_FMT: @@ -17190,7 +17190,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) fmt =3D (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case MOVF_FMT: /* RINT_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* RINT_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -17221,7 +17221,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MOVT_FMT: /* CLASS_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* CLASS_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -17252,7 +17252,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case PREFX: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); break; default: goto pool32f_invalid; @@ -17274,7 +17274,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) goto pool32f_invalid; \ } case MINA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); @@ -17287,7 +17287,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MAXA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); @@ -17329,7 +17329,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) /* cmovs */ switch ((ctx->opcode >> 6) & 0x7) { case MOVN_FMT: /* SELEQZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELEQZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -17347,11 +17347,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOVN_FMT_04: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVN); break; case MOVZ_FMT: /* SELNEZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELNEZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -17369,11 +17369,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOVZ_FMT_05: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVZ); break; case SEL_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); @@ -17386,7 +17386,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MADDF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op =3D OPC_MADDF_S; @@ -17399,7 +17399,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MSUBF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op =3D OPC_MSUBF_S; @@ -17432,45 +17432,45 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) minor =3D (ctx->opcode >> 21) & 0x1f; switch (minor) { case BLTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); break; case BLTZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BLTZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BGEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); break; case BGEZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BGEZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BLEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); break; case BGTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); break; =20 /* Traps */ case TLTI: /* BC1EQZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1EQZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0); @@ -17481,7 +17481,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case TGEI: /* BC1NEZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1NEZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0); @@ -17492,15 +17492,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case TLTIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TLTIU; goto do_trapi; case TGEIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TGEIU; goto do_trapi; case TNEI: /* SYNCI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SYNCI */ /* * Break the TB to be able to sync copied instructions @@ -17514,7 +17514,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case TEQI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TEQI; do_trapi: gen_trap(ctx, mips32_op, rs, -1, imm); @@ -17522,7 +17522,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) =20 case BNEZC: case BEQZC: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, minor =3D=3D BNEZC ? OPC_BNE : OPC_BEQ, 4, rs, 0, imm << 1, 0); /* @@ -17532,11 +17532,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) */ break; case LUI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); break; case SYNCI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* * Break the TB to be able to sync copied instructions * immediately. @@ -17545,24 +17545,24 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) break; case BC2F: case BC2T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* COP2: Not implemented. */ generate_exception_err(ctx, EXCP_CpU, 2); break; case BC1F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_B= C1F; goto do_cp1branch; case BC1T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_B= C1T; goto do_cp1branch; case BC1ANY4F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_BC1FANY4; goto do_cp1mips3d; case BC1ANY4T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_BC1TANY4; do_cp1mips3d: check_cop1x(ctx); @@ -17590,47 +17590,47 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) case POOL32C: minor =3D (ctx->opcode >> 12) & 0xf; offset =3D sextract32(ctx->opcode, 0, - (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); + (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12); switch (minor) { case LWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWL; goto do_ld_lr; case SWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWL; goto do_st_lr; case LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWR; goto do_ld_lr; case SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWR; goto do_st_lr; #if defined(TARGET_MIPS64) case LDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDL; goto do_ld_lr; case SDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDL; goto do_st_lr; case LDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDR; goto do_ld_lr; case SDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDR; goto do_st_lr; case LWU: @@ -17681,11 +17681,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) mips32_op =3D OPC_LHUE; goto do_ld_lr; case LWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWLE; goto do_ld_lr; case LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWRE; goto do_ld_lr; case LBE: @@ -17714,16 +17714,16 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) offset =3D sextract32(ctx->opcode, 0, 9); switch (minor2) { case SWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWLE; goto do_st_lr; case SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWRE; goto do_st_lr; case PREFE: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >=3D 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17750,7 +17750,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case PREF: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >=3D 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17762,7 +17762,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case ADDI32: /* AUI, LUI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* AUI, LUI */ gen_logic_imm(ctx, OPC_LUI, rt, rs, imm); } else { @@ -17800,13 +17800,13 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_slt_imm(ctx, mips32_op, rt, rs, imm); break; case JALX32: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); offset =3D (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case JALS32: /* BOVC, BEQC, BEQZALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs >=3D rt) { /* BOVC */ mips32_op =3D OPC_BOVC; @@ -17826,7 +17826,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BEQ32: /* BC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC */ gen_compute_compact_branch(ctx, OPC_BC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)= ); @@ -17836,7 +17836,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BNE32: /* BALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BALC */ gen_compute_compact_branch(ctx, OPC_BALC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)= ); @@ -17846,7 +17846,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case J32: /* BGTZC, BLTZC, BLTC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0 && rt !=3D 0) { /* BGTZC */ mips32_op =3D OPC_BGTZC; @@ -17865,7 +17865,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case JAL32: /* BLEZC, BGEZC, BGEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0 && rt !=3D 0) { /* BLEZC */ mips32_op =3D OPC_BLEZC; @@ -17900,7 +17900,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); break; case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ switch ((ctx->opcode >> 16) & 0x1f) { case ADDIUPC_00: @@ -17942,7 +17942,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BNVC: /* BNEC, BNEZALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs >=3D rt) { /* BNVC */ mips32_op =3D OPC_BNVC; @@ -17956,7 +17956,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case R6_BNEZC: /* JIALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt !=3D 0) { /* BNEZC */ gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0, @@ -17967,7 +17967,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case R6_BEQZC: /* JIC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt !=3D 0) { /* BEQZC */ gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, @@ -17978,7 +17978,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BLEZALC: /* BGEZALC, BGEUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs =3D=3D 0 && rt !=3D 0) { /* BLEZALC */ mips32_op =3D OPC_BLEZALC; @@ -17992,7 +17992,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case BGTZALC: /* BLTZALC, BLTUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs =3D=3D 0 && rt !=3D 0) { /* BGTZALC */ mips32_op =3D OPC_BGTZALC; @@ -18114,7 +18114,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) opc =3D OPC_SUBU; break; } - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* * In the Release 6, the register number location in * the instruction encoding has changed. @@ -18146,7 +18146,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case POOL16C: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_pool16c_r6_insn(ctx); } else { gen_pool16c_insn(ctx); @@ -18162,7 +18162,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case POOL16F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & 1) { generate_exception_end(ctx, EXCP_RI); } else { @@ -18280,14 +18280,14 @@ static int decode_micromips_opc(CPUMIPSState *env= , DisasContext *ctx) case B16: /* BC16 */ gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, sextract32(ctx->opcode, 0, 10) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); break; case BNEZ16: /* BNEZC16 */ case BEQZ16: /* BEQZC16 */ gen_compute_branch(ctx, op =3D=3D BNEZ16 ? OPC_BNE : OPC_BEQ, 2, mmreg(uMIPS_RD(ctx->opcode)), 0, sextract32(ctx->opcode, 0, 7) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); =20 break; case LI16: @@ -24970,7 +24970,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) case OPC_SLL: /* Shift with immediate */ if (sa =3D=3D 5 && rd =3D=3D 0 && rs =3D=3D 0 && rt =3D=3D 0) { /* PAUSE */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { generate_exception_end(ctx, EXCP_RI); break; @@ -25045,7 +25045,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS32R6) || + if ((ctx->insn_flags & ISA_MIPS_R6) || (env->CP0_Config3 & (1 << CP0C3_MSAP))) { decode_opc_special_r6(env, ctx); } else { @@ -25148,14 +25148,14 @@ static void decode_opc_special(CPUMIPSState *env,= DisasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS32R6) || + if ((ctx->insn_flags & ISA_MIPS_R6) || (env->CP0_Config3 & (1 << CP0C3_MSAP))) { decode_opc_special_r6(env, ctx); } break; #endif default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special_r6(env, ctx); } else if (ctx->insn_flags & INSN_R5900) { decode_opc_special_tx79(env, ctx); @@ -27565,7 +27565,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) int rs, rt, rd; uint32_t op1; =20 - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); =20 rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -28552,7 +28552,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_LWLE: case OPC_LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LBUE: case OPC_LHUE: @@ -28565,7 +28565,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) return; case OPC_SWLE: case OPC_SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SBE: case OPC_SHE: @@ -28605,7 +28605,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_ALIGN_2: case OPC_ALIGN_3: case OPC_BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28637,7 +28637,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DALIGN_6: case OPC_DALIGN_7: case OPC_DBITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28677,7 +28677,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) } break; default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special3_r6(env, ctx); } else { decode_opc_special3_legacy(env, ctx); @@ -30706,7 +30706,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BLTZALL: case OPC_BGEZALL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BLTZ: case OPC_BGEZ: @@ -30714,7 +30714,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_BLTZAL: case OPC_BGEZAL: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0) { /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); @@ -30733,11 +30733,11 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) =20 case OPC_TNEI: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_trap(ctx, op1, rs, -1, imm); break; case OPC_SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); generate_exception_end(ctx, EXCP_RI); break; case OPC_SYNCI: @@ -30757,14 +30757,14 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) break; #if defined(TARGET_MIPS64) case OPC_DAHI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs !=3D 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << = 32); } break; case OPC_DATI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs !=3D 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << = 48); @@ -30844,14 +30844,14 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) gen_store_gpr(t0, rt); break; case OPC_DVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_dvp(t0, cpu_env); gen_store_gpr(t0, rt); } break; case OPC_EVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_evp(t0, cpu_env); gen_store_gpr(t0, rt); @@ -30904,7 +30904,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -30933,7 +30933,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; /* Branch */ case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { generate_exception_end(ctx, EXCP_RI); break; @@ -30946,7 +30946,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { generate_exception_end(ctx, EXCP_RI); break; @@ -30963,7 +30963,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* OPC_BLEZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -30973,7 +30973,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* OPC_BGTZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -30981,7 +30981,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BEQL: case OPC_BNEL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BEQ: case OPC_BNE: @@ -30995,7 +30995,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* Fallthrough */ case OPC_LWL: case OPC_LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_LB: case OPC_LH: @@ -31007,7 +31007,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_SWL: case OPC_SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SB: case OPC_SH: @@ -31016,14 +31016,14 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) break; case OPC_SC: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); break; case OPC_CACHE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { @@ -31032,7 +31032,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { @@ -31076,7 +31076,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) #endif case OPC_BC1EQZ: /* OPC_BC1ANY2 */ check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC1EQZ */ gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); @@ -31090,19 +31090,19 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) break; case OPC_BC1NEZ: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); break; case OPC_BC1ANY4: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cop1x(ctx); check_insn(ctx, ASE_MIPS3D); /* fall through */ case OPC_BC1: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); break; @@ -31120,7 +31120,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) { int r6_op =3D ctx->opcode & FOP(0x3f, 0x1f); check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { switch (r6_op) { case R6_OPC_CMP_AF_S: case R6_OPC_CMP_UN_S: @@ -31205,7 +31205,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* Compact branches [R6] and COP2 [non-R6] */ case OPC_BC: /* OPC_LWC2 */ case OPC_BALC: /* OPC_SWC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC, OPC_BALC */ gen_compute_compact_branch(ctx, op, 0, 0, sextract32(ctx->opcode << 2, 0, 28)= ); @@ -31219,7 +31219,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs !=3D 0) { /* OPC_BEQZC, OPC_BNEZC */ gen_compute_compact_branch(ctx, op, rs, 0, @@ -31243,7 +31243,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; =20 case OPC_CP3: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); op1 =3D MASK_CP3(ctx->opcode); @@ -31300,7 +31300,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* fall through */ case OPC_LDL: case OPC_LDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LWU: case OPC_LD: @@ -31310,7 +31310,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_SDL: case OPC_SDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SD: check_insn(ctx, ISA_MIPS3); @@ -31318,7 +31318,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_st(ctx, op, rt, rs, imm); break; case OPC_SCD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_insn(ctx, ISA_MIPS3); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); @@ -31327,7 +31327,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -31344,7 +31344,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; #else case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); @@ -31353,7 +31353,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; #endif case OPC_DAUI: /* OPC_JALX */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); @@ -31387,7 +31387,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_PCREL: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); break; default: /* Invalid */ @@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS_R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, --=20 2.26.2