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Wed, 30 Dec 2020 10:38:12 -0500 Received: from host86-148-34-1.range86-148.btcentralplus.com ([86.148.34.1] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kudY0-00070L-SS; Wed, 30 Dec 2020 15:38:05 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, pbonzini@redhat.com, fam@euphon.net, laurent@vivier.eu Date: Wed, 30 Dec 2020 15:37:21 +0000 Message-Id: <20201230153745.30241-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201230153745.30241-1-mark.cave-ayland@ilande.co.uk> References: <20201230153745.30241-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.148.34.1 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 01/25] esp: checkpatch fixes X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/scsi/esp.c | 52 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 21 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index b84e0fe33e..7073166ad1 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -241,8 +241,9 @@ static void handle_satn(ESPState *s) } s->pdma_cb =3D satn_pdma_cb; len =3D get_cmd(s, buf, sizeof(buf)); - if (len) + if (len) { do_cmd(s, buf); + } } =20 static void s_without_satn_pdma_cb(ESPState *s) @@ -398,8 +399,8 @@ static void esp_do_dma(ESPState *s) * handle_ti_cmd() with do_cmd !=3D NULL (see the assert()) */ trace_esp_do_dma(s->cmdlen, len); - assert (s->cmdlen <=3D sizeof(s->cmdbuf) && - len <=3D sizeof(s->cmdbuf) - s->cmdlen); + assert(s->cmdlen <=3D sizeof(s->cmdbuf) && + len <=3D sizeof(s->cmdbuf) - s->cmdlen); if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); } else { @@ -445,15 +446,18 @@ static void esp_do_dma(ESPState *s) s->dma_left -=3D len; s->async_buf +=3D len; s->async_len -=3D len; - if (to_device) + if (to_device) { s->ti_size +=3D len; - else + } else { s->ti_size -=3D len; + } if (s->async_len =3D=3D 0) { scsi_req_continue(s->current_req); - /* If there is still data to be read from the device then - complete the DMA operation immediately. Otherwise defer - until the scsi layer has completed. */ + /* + * If there is still data to be read from the device then + * complete the DMA operation immediately. Otherwise defer + * until the scsi layer has completed. + */ if (to_device || s->dma_left !=3D 0 || s->ti_size =3D=3D 0) { return; } @@ -491,7 +495,8 @@ void esp_command_complete(SCSIRequest *req, uint32_t st= atus, ESPState *s =3D req->hba_private; =20 if (s->rregs[ESP_RSTAT] & STAT_INT) { - /* Defer handling command complete until the previous + /* + * Defer handling command complete until the previous * interrupt has been handled. */ trace_esp_command_complete_deferred(); @@ -513,8 +518,10 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len) if (s->dma_left) { esp_do_dma(s); } else if (s->dma_counter !=3D 0 && s->ti_size <=3D 0) { - /* If this was the last part of a DMA transfer then the - completion interrupt is deferred to here. */ + /* + * If this was the last part of a DMA transfer then the + * completion interrupt is deferred to here. + */ esp_dma_done(s); } } @@ -531,17 +538,18 @@ static void handle_ti(ESPState *s) dmalen =3D s->rregs[ESP_TCLO]; dmalen |=3D s->rregs[ESP_TCMID] << 8; dmalen |=3D s->rregs[ESP_TCHI] << 16; - if (dmalen=3D=3D0) { - dmalen=3D0x10000; + if (dmalen =3D=3D 0) { + dmalen =3D 0x10000; } s->dma_counter =3D dmalen; =20 - if (s->do_cmd) + if (s->do_cmd) { minlen =3D (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; - else if (s->ti_size < 0) + } else if (s->ti_size < 0) { minlen =3D (dmalen < -s->ti_size) ? dmalen : -s->ti_size; - else + } else { minlen =3D (dmalen < s->ti_size) ? dmalen : s->ti_size; + } trace_esp_handle_ti(minlen); if (s->dma) { s->dma_left =3D minlen; @@ -606,8 +614,10 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) } break; case ESP_RINTR: - /* Clear sequence step, interrupt register and all status bits - except TC */ + /* + * Clear sequence step, interrupt register and all status bits + * except TC + */ old_val =3D s->rregs[ESP_RINTR]; s->rregs[ESP_RINTR] =3D 0; s->rregs[ESP_RSTAT] &=3D ~STAT_TC; @@ -665,13 +675,13 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint6= 4_t val) } else { s->dma =3D 0; } - switch(val & CMD_CMD) { + switch (val & CMD_CMD) { case CMD_NOP: trace_esp_mem_writeb_cmd_nop(val); break; case CMD_FLUSH: trace_esp_mem_writeb_cmd_flush(val); - //s->ti_size =3D 0; + /*s->ti_size =3D 0;*/ s->rregs[ESP_RINTR] =3D INTR_FC; s->rregs[ESP_RSEQ] =3D 0; s->rregs[ESP_RFLAGS] =3D 0; @@ -787,7 +797,7 @@ static const VMStateDescription vmstate_esp_pdma =3D { }; =20 const VMStateDescription vmstate_esp =3D { - .name =3D"esp", + .name =3D "esp", .version_id =3D 4, .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { --=20 2.20.1