From nobody Tue Nov 18 09:18:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1609264738; cv=none; d=zohomail.com; s=zohoarc; b=KeYdLgw4WC+hexfW1mNHRO7NxCtj9GxJlQ5c5bjpSaYcVX1pdSDyFupzScaTvSEHe6mWdrnHEvnmUh9a+C0gl8rwTvUA+8k3XuZLJcSjhDU2t/GqJ1jdu9jII67xOO77FWA+zQ56tjVPJBtStz3WNvLkUNBERg7dkxxchm7ACbM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609264738; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T/QLbofimy3AO/pPHY7/KEJu1wugBIVC0LB8zhG9uZU=; b=W6HnifCb9eWEQ9ixb9yqRxdSM3KAvsS1LNQ8AXD6HSmiIm/V7EBQk1xjpO2dBREc+kE5ab0XzQTc9rnVMKS8is49dXQm4ZLxC5xmpHiEQm2huFaA5EEENeGUeLNt/W+TQLHdWKZIYlYud3lsajvuogePUVe7PKugaH7m2rNrRVs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1609264738228687.5724582008427; Tue, 29 Dec 2020 09:58:58 -0800 (PST) Received: from localhost ([::1]:57208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kuJGr-0001et-7m for importer@patchew.org; Tue, 29 Dec 2020 12:58:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kuJEy-0007S9-Vr; Tue, 29 Dec 2020 12:57:01 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:49892 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kuJEx-00055k-Bu; Tue, 29 Dec 2020 12:57:00 -0500 Received: from host86-148-34-1.range86-148.btcentralplus.com ([86.148.34.1] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kuJEv-0007wV-24; Tue, 29 Dec 2020 17:57:01 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, thuth@redhat.com Date: Tue, 29 Dec 2020 17:56:18 +0000 Message-Id: <20201229175619.6051-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201229175619.6051-1-mark.cave-ayland@ilande.co.uk> References: <20201229175619.6051-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.148.34.1 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 6/7] macio: wire macio GPIOs to OpenPIC using sysbus IRQs X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This both allows the wiring to be done as Ben suggested in his original com= ment in gpio.c and also enables the OpenPIC object property link to be removed. Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/gpio.c | 24 +++++------------------- hw/misc/macio/macio.c | 12 +++++++----- include/hw/misc/macio/gpio.h | 2 -- 3 files changed, 12 insertions(+), 26 deletions(-) diff --git a/hw/misc/macio/gpio.c b/hw/misc/macio/gpio.c index 0fef8fb335..b1bcf830c3 100644 --- a/hw/misc/macio/gpio.c +++ b/hw/misc/macio/gpio.c @@ -57,10 +57,7 @@ void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bo= ol state) =20 s->gpio_regs[gpio] =3D new_reg; =20 - /* This is will work until we fix the binding between MacIO and - * the MPIC properly so we can route all GPIOs and avoid going - * via the top level platform code. - * + /* * Note that we probably need to get access to the MPIC config to * decode polarity since qemu always use "raise" regardless. * @@ -152,25 +149,15 @@ static const MemoryRegionOps macio_gpio_ops =3D { }, }; =20 -static void macio_gpio_realize(DeviceState *dev, Error **errp) -{ - MacIOGPIOState *s =3D MACIO_GPIO(dev); - - s->gpio_extirqs[1] =3D qdev_get_gpio_in(DEVICE(s->pic), - NEWWORLD_EXTING_GPIO1); - s->gpio_extirqs[9] =3D qdev_get_gpio_in(DEVICE(s->pic), - NEWWORLD_EXTING_GPIO9); -} - static void macio_gpio_init(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); MacIOGPIOState *s =3D MACIO_GPIO(obj); + int i; =20 - object_property_add_link(obj, "pic", TYPE_OPENPIC, - (Object **) &s->pic, - qdev_prop_allow_set_link_before_realize, - 0); + for (i =3D 0; i < 10; i++) { + sysbus_init_irq(sbd, &s->gpio_extirqs[i]); + } =20 memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj, "gpio", 0x30); @@ -207,7 +194,6 @@ static void macio_gpio_class_init(ObjectClass *oc, void= *data) DeviceClass *dc =3D DEVICE_CLASS(oc); NMIClass *nc =3D NMI_CLASS(oc); =20 - dc->realize =3D macio_gpio_realize; dc->reset =3D macio_gpio_reset; dc->vmsd =3D &vmstate_macio_gpio; nc->nmi_monitor_handler =3D macio_gpio_nmi; diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 36be77cede..d17cffd868 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -324,14 +324,16 @@ static void macio_newworld_realize(PCIDevice *d, Erro= r **errp) =20 if (ns->has_pmu) { /* GPIOs */ - sysbus_dev =3D SYS_BUS_DEVICE(&ns->gpio); - object_property_set_link(OBJECT(&ns->gpio), "pic", OBJECT(pic_dev), - &error_abort); - memory_region_add_subregion(&s->bar, 0x50, - sysbus_mmio_get_region(sysbus_dev, 0)); if (!qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), errp)) { return; } + sysbus_dev =3D SYS_BUS_DEVICE(&ns->gpio); + sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, + NEWWORLD_EXTING_GPIO1)); + sysbus_connect_irq(sysbus_dev, 9, qdev_get_gpio_in(pic_dev, + NEWWORLD_EXTING_GPIO9)); + memory_region_add_subregion(&s->bar, 0x50, + sysbus_mmio_get_region(sysbus_dev, 0)); =20 /* PMU */ object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU); diff --git a/include/hw/misc/macio/gpio.h b/include/hw/misc/macio/gpio.h index 4dee09a9dd..7d2aa886c2 100644 --- a/include/hw/misc/macio/gpio.h +++ b/include/hw/misc/macio/gpio.h @@ -38,8 +38,6 @@ struct MacIOGPIOState { SysBusDevice parent; /*< public >*/ =20 - OpenPICState *pic; - MemoryRegion gpiomem; qemu_irq gpio_extirqs[10]; uint8_t gpio_levels[8]; --=20 2.20.1