From nobody Tue Nov 18 09:19:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608714718; cv=none; d=zohomail.com; s=zohoarc; b=YTcp9ig6i3/lJB/NOD2WXgFW5YKnJoBhQzc6tBPzv6qoXf/Gqsj/hApEKWR8yZEn+gR/pguqOb1AzahN9d6n/3k+KkpaRAcm2Jopd9EIARzv1zo9MdyYqBdUr4cXBJR4zpNAM5R7DZDZMqQwQ9pA0bwU26ZDY7ORQzehS/hPMew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608714718; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WKOaK+qo4rEsopxe6tW/Ow/I0caU6eJieDf+NuWOP/M=; b=nyEnqV5JG/uIDb/4QCgRqTQbmGA/1M6x2xVMzO6P+YqVmTX7Ry5mssgIzrsf7glzXG/8lmJgszQkIydginIJ7Dqa6qoPNkHPqnHal7A/QRpvrM2rB1iypmZjWaMQKd9dcbOK+CED3tFU6T4/Ev8iC4emcq8aW8DhdeO53rXhGYA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608714718133496.77937880594095; Wed, 23 Dec 2020 01:11:58 -0800 (PST) Received: from localhost ([::1]:40066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0BY-00057o-WC for importer@patchew.org; Wed, 23 Dec 2020 04:11:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09y-0003iJ-Ld for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:18 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09s-0002Zg-23 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:18 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D16pB19trzM8Jw; Wed, 23 Dec 2020 17:09:06 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:54 +0800 From: Jiahui Cen To: Subject: [PATCH v3 4/8] acpi/gpex: Exclude pxb's resources from PCI0 Date: Wed, 23 Dec 2020 17:08:32 +0800 Message-ID: <20201223090836.9075-5-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Exclude the resources of extra root bridges from PCI0's _CRS. Otherwise, the resource windows would overlap in guest, and the IO resource window would fail to be registered. Signed-off-by: Jiahui Cen --- hw/pci-host/gpex-acpi.c | 64 +++++++++++++------- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index c189306599..4bf1e94309 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -144,6 +144,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) Aml *method, *crs, *dev, *rbuf; PCIBus *bus =3D cfg->bus; CrsRangeSet crs_range_set; + CrsRangeEntry *entry; + int i; =20 /* start to construct the tables for pxb */ crs_range_set_init(&crs_range_set); @@ -191,7 +193,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) aml_append(scope, dev); } } - crs_range_set_free(&crs_range_set); =20 /* tables for the main */ dev =3D aml_device("%s", "PCI0"); @@ -209,36 +210,55 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig= *cfg) aml_append(method, aml_return(aml_int(cfg->ecam.base))); aml_append(dev, method); =20 + /* + * At this point crs_range_set has all the ranges used by pci + * busses *other* than PCI0. These ranges will be excluded from + * the PCI0._CRS. + */ rbuf =3D aml_resource_template(); aml_append(rbuf, aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, nr_pcie_buses)); if (cfg->mmio32.size) { - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, - cfg->mmio32.base, - cfg->mmio32.base + cfg->mmio32.size - = 1, - 0x0000, - cfg->mmio32.size)); + crs_replace_with_free_ranges(crs_range_set.mem_ranges, + cfg->mmio32.base, + cfg->mmio32.base + cfg->mmio32.size -= 1); + for (i =3D 0; i < crs_range_set.mem_ranges->len; i++) { + entry =3D g_ptr_array_index(crs_range_set.mem_ranges, i); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FI= XED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, entry->limit, + 0x0000, entry->limit - entry->base + 1)); + } } if (cfg->pio.size) { - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECO= DE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, - cfg->pio.size - 1, - cfg->pio.base, - cfg->pio.size)); + crs_replace_with_free_ranges(crs_range_set.io_ranges, + 0x0000, + cfg->pio.size - 1); + for (i =3D 0; i < crs_range_set.io_ranges->len; i++) { + entry =3D g_ptr_array_index(crs_range_set.io_ranges, i); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, entry->base, + entry->limit, cfg->pio.base, + entry->limit - entry->base + 1)); + } } if (cfg->mmio64.size) { - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, - cfg->mmio64.base, - cfg->mmio64.base + cfg->mmio64.size - = 1, - 0x0000, - cfg->mmio64.size)); + crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, + cfg->mmio64.base, + cfg->mmio64.base + cfg->mmio64.size -= 1); + for (i =3D 0; i < crs_range_set.mem_64bit_ranges->len; i++) { + entry =3D g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FI= XED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, + entry->limit, 0x0000, + entry->limit - entry->base + 1)); + } } aml_append(dev, aml_name_decl("_CRS", rbuf)); =20 @@ -257,4 +277,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) aml_append(dev_res0, aml_name_decl("_CRS", crs)); aml_append(dev, dev_res0); aml_append(scope, dev); + + crs_range_set_free(&crs_range_set); } --=20 2.29.2