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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- tcg/riscv/tcg-target-conset.h | 25 +++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------- 3 files changed, 49 insertions(+), 60 deletions(-) create mode 100644 tcg/riscv/tcg-target-conset.h diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h new file mode 100644 index 0000000000..116dd75db2 --- /dev/null +++ b/tcg/riscv/tcg-target-conset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * RISC-V target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(LZ, L) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I3(LZ, L, L) +C_O0_I3(LZ, LZ, L) +C_O0_I4(LZ, LZ, L, L) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..a357962e01 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 33047c1951..d222692704 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1571,50 +1571,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r - =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r - =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef rZ_r - =3D { .args_ct_str =3D { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - =3D { .args_ct_str =3D { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - =3D { .args_ct_str =3D { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - =3D { .args_ct_str =3D { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - =3D { .args_ct_str =3D { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - =3D { .args_ct_str =3D { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef r_r_L - =3D { .args_ct_str =3D { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - =3D { .args_ct_str =3D { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - =3D { .args_ct_str =3D { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - =3D { .args_ct_str =3D { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - =3D { .args_ct_str =3D { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - =3D { .args_ct_str =3D { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rM", "rM" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1646,7 +1607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -1655,7 +1616,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -1665,11 +1626,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); =20 case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); =20 case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: @@ -1687,7 +1648,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_rem_i64: case INDEX_op_remu_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -1695,39 +1656,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); =20 case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; + return C_O2_I4(r, r, rZ, rZ, rM, rM); =20 case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; + return C_O0_I4(rZ, rZ, rZ, rZ); =20 case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; + return C_O1_I4(r, rZ, rZ, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r,= L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS =3D=3D 64 ? &LZ_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(LZ, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(LZ, L= Z, L) + : C_O0_I4(LZ, LZ, L, L)); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1