From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608703486; cv=none; d=zohomail.com; s=zohoarc; b=Q2kzH9Bx1cdEfwXgVdd91+3NhWxynQFVR8NFB7rDzKuummXzQfLSxnyHh+Kn4LOJ3j97LqIDRiOj95y/RshiLPzdyzgvxPd5OiVLfubjXTK6FB26OMeeaRiu4oowsCYxPvoTjXaUGYOr0xqE+RI8xlG7ZzO2ZdyJ4bhCmMgLWWk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608703486; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rAW07Dku/fTSAeGLs/tMwXeih7Omsc2EM7pIkYPifgA=; b=N6KWfjVi3XIDOWZhaH7edA0ZWsXFW4ipHkGKDSGDDCCwZKAetzxWpk2cxBHQ20oAC6S7Vqe3gSe/pJ2QZDGeBiP/wyLaUIljJKWAjWvUDWOpwjUie7JOmdAzp8GAmO3udq44WzBJOqinFS8/BdLUnQ3LSM5OHrdD+YWpIvsSG3U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608703486912236.65350584638975; Tue, 22 Dec 2020 22:04:46 -0800 (PST) Received: from localhost ([::1]:54126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxGP-0001h0-Lu for importer@patchew.org; Wed, 23 Dec 2020 01:04:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxDy-0008Ot-8D for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:16 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:39799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDs-0000KF-Mr for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:11 -0500 Received: by mail-pj1-x1032.google.com with SMTP id hk16so2613492pjb.4 for ; Tue, 22 Dec 2020 22:02:08 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rAW07Dku/fTSAeGLs/tMwXeih7Omsc2EM7pIkYPifgA=; b=q6xztLYwFw1kzEMs+tCaA80dtPD5X3ysM8Xh1aKZb3jN+8JsyEkbKzA0Xw3ZwztEJ5 0ivL6zXErkq4YT12V1Gls9ImIsq10Ie7/0JYIAS8o/EjXclJ1InarV7dYxi4h8qoWXjr FiL9v37IZ0B6RzTjH1q8dAimn9o5PbhLHg3UmodUPr0N46rOaFMYwa5TaoUvZp5Xu8Vx C8z6gifNFZu1S7dW/7KtOMYwKht3e41rnkkfC+CPwQ5AijtqzIUhPpWViG0LXGYqTBla ltIMZPGnDgzgihWanAuPiGbIPMk9/w8wu2GgkowUXuZGcCo6jvBI7rknlUD94UAxmrdw 5BYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rAW07Dku/fTSAeGLs/tMwXeih7Omsc2EM7pIkYPifgA=; b=VoCCM3MIAXJvhUmIRo2YYG3URNrenpG0OukeCaMuEZmTZ27YOo0w8zFZ2DgXheCL82 NaQr7IJQyTWbD1zH2NvFt218b5S0pWDrZOdzqwoEmNRPefIUqKCU/Xocz5qDsQ6iFDlx UZXJQPsVXLJHUNFqSfZLlrsiCkn7BcE9xCwA8Ec4h62aLdUCzfqwPlOENG2CvyRpHrDj E7FT7sRybWV16x/pWBwTljVHU+lw0AiliDrzWO/Q9oduxUVy6O75nDcVetRCk2GSZ0NI K9myj4RySG9+pGCKI0lJl0eUQfaprMusJ40zxtU2CLhyG20IEW0QLJi4etTi4Khe1M5j hKbg== X-Gm-Message-State: AOAM532Aui3gToICIXLT0oxCY6EtAvxsuzoF9nhLkdC9aazWrrqZAFDD U8BT7yn5ws6kEQEmvqE+gYapkkx1V2lZxg== X-Google-Smtp-Source: ABdhPJwTRG18Ejh6Ybf3yH1Whp+ot+O+8PwT7Os85K8sWaPIsh+UcJJ6q8Ga62y2J9q3dNGV1WU5Xg== X-Received: by 2002:a17:90a:f00f:: with SMTP id bt15mr25500109pjb.209.1608703327270; Tue, 22 Dec 2020 22:02:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/22] tcg/tci: Drop L and S constraints Date: Tue, 22 Dec 2020 22:01:43 -0800 Message-Id: <20201223060204.576856-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These are identical to the 'r' constraint. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 231b9b1775..50a08bef03 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -46,11 +46,11 @@ # define R64 "r" #endif #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "L", "L" -# define S "S", "S" +# define L "r", "r" +# define S "r", "r" #else -# define L "L" -# define S "S" +# define L "r" +# define S "r" #endif =20 /* TODO: documentation. */ @@ -390,8 +390,6 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, { switch (*ct_str++) { case 'r': - case 'L': /* qemu_ld constraint */ - case 'S': /* qemu_st constraint */ ct->regs =3D BIT(TCG_TARGET_NB_REGS) - 1; break; default: --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608703877; cv=none; d=zohomail.com; s=zohoarc; b=b52rCzFIpobcZb5rc3nwIu1DmU4CT03JpVRbQGz+laDM+fbIGW8uH6CNwOaNu0rEDMSoAbWPXlm3j/XnHSHBADPFkfmyw1WVeDPHGX+CytxNRD3ScpfhBVdJV4EQRdOPoPvYaFDUvjkKsV4pjAIvvWcgB9K+b3F8SunGW9k4kqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608703877; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zGMNyIm+K/W3aZHsjQzBQ/qpcbywBXoHa8cbHlQEpxs=; b=K7fv1FhI1mmdmfpSmoDCH6SjoKV/6k9lctvIfzfSCkNus/++AKnlY1xs86tq8ndYakkUrNueFRsSdV1bdXptEtNGTi/mP63WgFsz3sPzi+7o6gYOmlFT/ma4Rp0Zf9k2oYEy/cjly+BqPTpE9/3I+ldngEq3NS07aU8UZNNMEB0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608703877822978.3770467759057; Tue, 22 Dec 2020 22:11:17 -0800 (PST) Received: from localhost ([::1]:42846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxMi-0000MO-KL for importer@patchew.org; Wed, 23 Dec 2020 01:11:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxDz-0008P0-1J for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:16 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:43329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDv-0000Kw-Kv for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:14 -0500 Received: by mail-pf1-x434.google.com with SMTP id c12so9757276pfo.10 for ; Tue, 22 Dec 2020 22:02:09 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zGMNyIm+K/W3aZHsjQzBQ/qpcbywBXoHa8cbHlQEpxs=; b=cRFinEUEnaaOyBNCL6bIgGjkVR8WRQ57xQm6lCRFAT+xhIiWua1Em9Ne6WdAb9Ia0M bwz8StynpWlz2n1uxbF34pZQl3pAyqwYKJ8Nb7xKwFPWSrb8O/obHhUALos2IrNIeOE7 bdySv01yNqXW0cKy/fUVOH9JH+a9esF7ldc0tnEibhDlHPxxJkiQKzwOIF6pDbPonpcg KDvqUyEYQVUBtLICrH2QhOF8U7ZPZd+0hZJMg8nOaiXqIGnBrTvDueqiDbmwbOSPQhl8 8cels7ZtbYIAascdCcgKjy+/5vsytp/l1H8YDvUsDb/r2cPZPqLh4ANm4nFApPHZiY/d 4THA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zGMNyIm+K/W3aZHsjQzBQ/qpcbywBXoHa8cbHlQEpxs=; b=Rm+Xs69B8JB84NCDXvb1187/UtHAQvQTgiyJ83Ww84or+f/lDfRjjQT1VfsOqMUvvs to4UFQqGoolfsU6xYdW9ld6q9kVHvChWFfHCCbWlyVHLBClZ34NbaDT/GA6VMVfmqz/O hGvZTkSJzqUbK2BfQgYNxsny0Sw3Qab1JQAmN0sOZZL6QHS634kz+LAfJjhsVSZCqLwy /dHMBZuBxAlKbQxdPTbSIine4IBOi+/HH+t0D412mNcTh+se8iX6g2EkQNInY3Scxynj zo0S5tgMGRMfEABoWB/x4YxXB2Qa7RpeWHc7LN+gS64h1LjyDG+sjU+obPYvD+knhGDQ cDcQ== X-Gm-Message-State: AOAM531wFWUAdvMygGGo9Re4BnSyxD4FXuGIEQucjDivP4qw54MDORG+ 6Je+TdzVjMyjOvZAsBekbk342U9VE9KLYA== X-Google-Smtp-Source: ABdhPJy5RHRchrX1iFOvNZ6xbCLi0jRtBgxwO6xDxPMZz1VtcYCE21Fo3hAvdYkwZR9mqA4MkKem8A== X-Received: by 2002:a63:5d5f:: with SMTP id o31mr23444902pgm.295.1608703328421; Tue, 22 Dec 2020 22:02:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/22] tcg/i386: Move constraint type check to tcg_target_const_match Date: Tue, 22 Dec 2020 22:01:44 -0800 Message-Id: <20201223060204.576856-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Rather than check the type when filling in the constraint, check it when matching the constant. This removes the only use of the type argument to target_parse_constraint. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d8797ed398..b73873f715 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -254,13 +254,13 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, break; =20 case 'e': - ct->ct |=3D (type =3D=3D TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONS= T_S32); + ct->ct |=3D TCG_CT_CONST_S32; break; case 'Z': - ct->ct |=3D (type =3D=3D TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONS= T_U32); + ct->ct |=3D TCG_CT_CONST_U32; break; case 'I': - ct->ct |=3D (type =3D=3D TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONS= T_I32); + ct->ct |=3D TCG_CT_CONST_I32; break; =20 default: @@ -277,14 +277,20 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, if (ct & TCG_CT_CONST) { return 1; } - if ((ct & TCG_CT_CONST_S32) && val =3D=3D (int32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_U32) && val =3D=3D (uint32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_I32) && ~val =3D=3D (int32_t)~val) { - return 1; + if (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I32) { + if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32))= { + return 1; + } + } else { + if ((ct & TCG_CT_CONST_S32) && val =3D=3D (int32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_U32) && val =3D=3D (uint32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_I32) && ~val =3D=3D (int32_t)~val) { + return 1; + } } if ((ct & TCG_CT_CONST_WSZ) && val =3D=3D (type =3D=3D TCG_TYPE_I32 ? = 32 : 64)) { return 1; --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608703711; cv=none; d=zohomail.com; s=zohoarc; b=i3f7dVCsITQQ74MqShOQBTZFgR5Sj9sW5zxRQaNavzlq2ujAT998OFjYqTrBChr0e7bZv14HJqOiuoxbDO5LRhBVy54NKxQbwbD8Qq18ahVP6EfOKVy75P4LWXu9XaEKq1lSH/c7YA9XctmdTT91sDmMZCG7KZfmqleTq6irCW0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608703711; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jwoUkFYPLhkV44osybn2ygv0a2eAfyC9vW2c8OoHcPA=; b=JsjqX325/dE3LkO0Wj5CFaASIkuPsdudW6n9vlG2+YVVJn11nhRYrQwCXzg1nKBD8Ki7HV7h3UcWUd2ljSpmOXoiB5PRCX5l3ZsdFii/mbowoM1GUKf3l2uH2upw8rYFNSUrpgbihkodRNsopoWwXEumus5VleREE0GplTkD/98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608703711258860.2712508454048; Tue, 22 Dec 2020 22:08:31 -0800 (PST) Received: from localhost ([::1]:34614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxK2-0005LY-37 for importer@patchew.org; Wed, 23 Dec 2020 01:08:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE5-0008Py-Np for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:35769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDv-0000Lc-LG for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: by mail-pj1-x102d.google.com with SMTP id b5so2623339pjl.0 for ; Tue, 22 Dec 2020 22:02:10 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. 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Since this is done directly into the switch statement, duplicates are compilation errors rather than silently ignored at runtime. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-constr.h | 26 ++++++++++++++ tcg/i386/tcg-target.h | 1 + tcg/tcg.c | 33 ++++++++++++++--- tcg/i386/tcg-target.c.inc | 70 ++---------------------------------- 4 files changed, 58 insertions(+), 72 deletions(-) create mode 100644 tcg/i386/tcg-target-constr.h diff --git a/tcg/i386/tcg-target-constr.h b/tcg/i386/tcg-target-constr.h new file mode 100644 index 0000000000..e4a4886b6c --- /dev/null +++ b/tcg/i386/tcg-target-constr.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +/* + * i386 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +REGS('a', 1u << TCG_REG_EAX) +REGS('b', 1u << TCG_REG_EBX) +REGS('c', 1u << TCG_REG_ECX) +REGS('d', 1u << TCG_REG_EDX) +REGS('S', 1u << TCG_REG_ESI) +REGS('D', 1u << TCG_REG_EDI) + +REGS('r', ALL_GENERAL_REGS) +REGS('x', ALL_VECTOR_REGS) +/* A register that can be used as a byte operand. */ +REGS('q', ALL_BYTEL_REGS) +/* A register with an addressable second byte (e.g. %ah). */ +REGS('Q', ALL_BYTEH_REGS) +/* qemu_ld/st address constraint */ +REGS('L', ALL_GENERAL_REGS & ~((1 << TCG_REG_L0) | (1 << TCG_REG_L1))) + +CONST('e', TCG_CT_CONST_S32) +CONST('I', TCG_CT_CONST_I32) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_U32) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abd4ac7fc0..7c405e166d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 43c6cf8f52..f5b53d739e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -102,8 +102,10 @@ static void tcg_register_jit_int(void *buf, size_t siz= e, __attribute__((unused)); =20 /* Forward declarations for functions declared and used in tcg-target.c.in= c. */ +#ifndef TCG_TARGET_CONSTR_H static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e); +#endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); @@ -2239,7 +2241,6 @@ static void process_op_defs(TCGContext *s) for (op =3D 0; op < NB_OPS; op++) { TCGOpDef *def =3D &tcg_op_defs[op]; const TCGTargetOpDef *tdefs; - TCGType type; int i, nb_args; =20 if (def->flags & TCG_OPF_NOT_PRESENT) { @@ -2255,7 +2256,6 @@ static void process_op_defs(TCGContext *s) /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(tdefs !=3D NULL); =20 - type =3D (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32= ); for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; /* Incomplete TCGTargetOpDef entry. */ @@ -2287,11 +2287,34 @@ static void process_op_defs(TCGContext *s) def->args_ct[i].ct |=3D TCG_CT_CONST; ct_str++; break; + +#ifdef TCG_TARGET_CONSTR_H + /* Include all of the target-specific constraints. */ + +#undef CONST +#define CONST(CASE, MASK) \ + case CASE: def->args_ct[i].ct |=3D MASK; ct_str++; break; +#define REGS(CASE, MASK) \ + case CASE: def->args_ct[i].regs |=3D MASK; ct_str++; break; + +#include "tcg-target-constr.h" + +#undef REGS +#undef CONST default: - ct_str =3D target_parse_constraint(&def->args_ct[i], - ct_str, type); /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str !=3D NULL); + g_assert_not_reached(); +#else + default: + { + TCGType type =3D (def->flags & TCG_OPF_64BIT + ? TCG_TYPE_I64 : TCG_TYPE_I32); + ct_str =3D target_parse_constraint(&def->args_ct[i= ], + ct_str, type); + /* Typo in TCGTargetOpDef constraint. */ + tcg_debug_assert(ct_str !=3D NULL); + } +#endif } } } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b73873f715..981dd9aca4 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -194,81 +194,17 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, return true; } =20 +#define ALL_BYTEH_REGS 0x0000000fu #if TCG_TARGET_REG_BITS =3D=3D 64 #define ALL_GENERAL_REGS 0x0000ffffu #define ALL_VECTOR_REGS 0xffff0000u +#define ALL_BYTEL_REGS ALL_GENERAL_REGS #else #define ALL_GENERAL_REGS 0x000000ffu #define ALL_VECTOR_REGS 0x00ff0000u +#define ALL_BYTEL_REGS ALL_BYTEH_REGS #endif =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch(*ct_str++) { - case 'a': - tcg_regset_set_reg(ct->regs, TCG_REG_EAX); - break; - case 'b': - tcg_regset_set_reg(ct->regs, TCG_REG_EBX); - break; - case 'c': - tcg_regset_set_reg(ct->regs, TCG_REG_ECX); - break; - case 'd': - tcg_regset_set_reg(ct->regs, TCG_REG_EDX); - break; - case 'S': - tcg_regset_set_reg(ct->regs, TCG_REG_ESI); - break; - case 'D': - tcg_regset_set_reg(ct->regs, TCG_REG_EDI); - break; - case 'q': - /* A register that can be used as a byte operand. */ - ct->regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xf; - break; - case 'Q': - /* A register with an addressable second byte (e.g. %ah). */ - ct->regs =3D 0xf; - break; - case 'r': - /* A general register. */ - ct->regs |=3D ALL_GENERAL_REGS; - break; - case 'W': - /* With TZCNT/LZCNT, we can have operand-size as an input. */ - ct->ct |=3D TCG_CT_CONST_WSZ; - break; - case 'x': - /* A vector register. */ - ct->regs |=3D ALL_VECTOR_REGS; - break; - - /* qemu_ld/st address constraint */ - case 'L': - ct->regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->regs, TCG_REG_L1); - break; - - case 'e': - ct->ct |=3D TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_U32; - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_I32; - break; - - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608703507; cv=none; d=zohomail.com; s=zohoarc; b=l/pP9td00Il2pJVRp3aXFMqIFal07632T5RzfSKPr1YoIjS+wltO0YLzzXvCBcJU5xDGdXQjwqXI6tP7bqPdsGknz9EQsMeeSb++hQm9+YvADnafg/z+Q8m9ABb+tHoDKxhxl8DOamVGypFmLZ5/UCxPFhZeoa7De/YneFwX2WQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608703507; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NrM0nd/vAh/xuPN3ZjF7gS1lRQ4hob266SPoNoDOWZg=; b=HEBNnjE8KLCpI07NJNUi2yQGRnZN/IhzC4lo0awrdEDGMBx7Y6U2JlNygNqx9m8YAnj1AN73iQ3L8qcvVzJspT2E/Cy/5jlwpKtNl2YTjlbhjNRzibgD4U7+F+LIXj4haiM8g4vBHzyZu35mgVvSBbIBpMkS+KauZYaICySDsBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608703507727894.7725331730024; Tue, 22 Dec 2020 22:05:07 -0800 (PST) Received: from localhost ([::1]:54198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxGk-0001ip-LL for importer@patchew.org; Wed, 23 Dec 2020 01:05:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE3-0008Pm-E6 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:38060) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDx-0000Lg-RN for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:19 -0500 Received: by mail-pg1-x52c.google.com with SMTP id e2so9935531pgi.5 for ; Tue, 22 Dec 2020 22:02:11 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-constr.h | 31 +++++++++++++++++++ tcg/arm/tcg-target.h | 1 + tcg/arm/tcg-target.c.inc | 60 ------------------------------------- 3 files changed, 32 insertions(+), 60 deletions(-) create mode 100644 tcg/arm/tcg-target-constr.h diff --git a/tcg/arm/tcg-target-constr.h b/tcg/arm/tcg-target-constr.h new file mode 100644 index 0000000000..15c5e53406 --- /dev/null +++ b/tcg/arm/tcg-target-constr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Arm target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffu + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ + (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ + (1 << TCG_REG_R14))) +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ + (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \ + ((TARGET_LONG_BITS =3D=3D 64) << TCG_REG_R3))) +#else +#define ALL_QLOAD_REGS ALL_GENERAL_REGS +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('l', ALL_QLOAD_REGS) +REGS('s', ALL_QSTORE_REGS) + +CONST('I', TCG_CT_CONST_ARM) +CONST('K', TCG_CT_CONST_INV) +CONST('N', TCG_CT_CONST_NEG) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 17e771374d..6f058d6d9b 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,5 +146,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 62c37a954b..ab1b295293 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -234,66 +234,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, #define TCG_CT_CONST_NEG 0x400 #define TCG_CT_CONST_ZERO 0x800 =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'I': - ct->ct |=3D TCG_CT_CONST_ARM; - break; - case 'K': - ct->ct |=3D TCG_CT_CONST_INV; - break; - case 'N': /* The gcc constraint letter is L, already used here. */ - ct->ct |=3D TCG_CT_CONST_NEG; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - - case 'r': - ct->regs =3D 0xffff; - break; - - /* qemu_ld address */ - case 'l': - ct->regs =3D 0xffff; -#ifdef CONFIG_SOFTMMU - /* r0-r2,lr will be overwritten when reading the tlb entry, - so don't use these. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->regs, TCG_REG_R14); -#endif - break; - - /* qemu_st address & data */ - case 's': - ct->regs =3D 0xffff; - /* r0-r2 will be overwritten when reading the tlb entry (softmmu o= nly) - and r0-r1 doing the byte swapping, so don't use these. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->regs, TCG_REG_R1); -#if defined(CONFIG_SOFTMMU) - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); -#if TARGET_LONG_BITS =3D=3D 64 - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#endif - tcg_regset_reset_reg(ct->regs, TCG_REG_R14); -#endif - break; - - default: - return NULL; - } - return ct_str; -} - static inline uint32_t rotl(uint32_t val, int n) { return (val << n) | (val >> (32 - n)); --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-constr.h | 27 +++++++++++++++++++ tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.c.inc | 46 --------------------------------- 3 files changed, 28 insertions(+), 46 deletions(-) create mode 100644 tcg/aarch64/tcg-target-constr.h diff --git a/tcg/aarch64/tcg-target-constr.h b/tcg/aarch64/tcg-target-const= r.h new file mode 100644 index 0000000000..28f7aa6f03 --- /dev/null +++ b/tcg/aarch64/tcg-target-constr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * AArch64 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu +#define ALL_VECTOR_REGS 0xffffffff00000000ull + +#ifdef CONFIG_SOFTMMU +#define ALL_QLDST_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \ + (1 << TCG_REG_X2) | (1 << TCG_REG_X3))) +#else +#define ALL_QLDST_REGS ALL_GENERAL_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('l', ALL_QLDST_REGS) +REGS('w', ALL_VECTOR_REGS) + +CONST('A', TCG_CT_CONST_AIMM) +CONST('L', TCG_CT_CONST_LIMM) +CONST('M', TCG_CT_CONST_MONE) +CONST('O', TCG_CT_CONST_ORRI) +CONST('N', TCG_CT_CONST_ANDI) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 663dd0b95e..ca7af5a589 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,5 +159,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 26f71cb599..310bc972e3 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -122,52 +122,6 @@ static inline bool patch_reloc(tcg_insn_unit *code_ptr= , int type, #define TCG_CT_CONST_ORRI 0x1000 #define TCG_CT_CONST_ANDI 0x2000 =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': /* general registers */ - ct->regs |=3D 0xffffffffu; - break; - case 'w': /* advsimd registers */ - ct->regs |=3D 0xffffffff00000000ull; - break; - case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->regs =3D 0xffffffffu; -#ifdef CONFIG_SOFTMMU - /* x0 and x1 will be overwritten when reading the tlb entry, - and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->regs, TCG_REG_X3); -#endif - break; - case 'A': /* Valid for arithmetic immediate (positive or negative). */ - ct->ct |=3D TCG_CT_CONST_AIMM; - break; - case 'L': /* Valid for logical immediate. */ - ct->ct |=3D TCG_CT_CONST_LIMM; - break; - case 'M': /* minus one */ - ct->ct |=3D TCG_CT_CONST_MONE; - break; - case 'O': /* vector orr/bic immediate */ - ct->ct |=3D TCG_CT_CONST_ORRI; - break; - case 'N': /* vector orr/bic immediate, inverted */ - ct->ct |=3D TCG_CT_CONST_ANDI; - break; - case 'Z': /* zero */ - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* Match a constant valid for addition (12-bit, optionally shifted). */ static inline bool is_aimm(uint64_t val) { --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=G/axsKwIG6T95QPg/jBLY9DS0jhAHEEiPneseNdvWWM=; b=kaiq0ERQx/+EJlrpuuO91ERJ2WAxm/0DD2cLD9eGxVBZeQEueUzAa7KfPwnAJsK74k vbxNd46ufuhPlVf08EBLBGmhBdlhLmcRuS7BSyDVBMvGrd/7HcS2zn8n9eIaK6AwkL0B Stqf9+q9hA4/FATl4hQM6d3dG5YP46SCoZluk8gYS/C7xp1V+3hXLMBtbO0BEdZtXNxi xUYg+AU1kbo3Rqo2Hgyr0zTHgAnhoW6BSGKywZTExNRRBpuxWauqvcaNiofT64yNQl1n qmgsCS8XOUgsUADZGqTgWLLjIwJmreZqGzDT+Oe1SL/0xKWmTaAzIvB2G+S+r/xnUjpf fSwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G/axsKwIG6T95QPg/jBLY9DS0jhAHEEiPneseNdvWWM=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-constr.h | 37 +++++++++++++++++++++++ tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.c.inc | 58 ------------------------------------- 3 files changed, 38 insertions(+), 58 deletions(-) create mode 100644 tcg/ppc/tcg-target-constr.h diff --git a/tcg/ppc/tcg-target-constr.h b/tcg/ppc/tcg-target-constr.h new file mode 100644 index 0000000000..b4937f37f7 --- /dev/null +++ b/tcg/ppc/tcg-target-constr.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * PowerPC target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu +#define ALL_VECTOR_REGS 0xffffffff00000000ull + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (ALL_GENERAL_REGS & \ + ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ + (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) +#else +#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) +#define ALL_QSTORE_REGS ALL_QLOAD_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('v', ALL_VECTOR_REGS) +REGS('A', 1u << TCG_REG_R3) +REGS('B', 1u << TCG_REG_R4) +REGS('C', 1u << TCG_REG_R5) +REGS('D', 1u << TCG_REG_R6) +REGS('L', ALL_QLOAD_REGS) +REGS('S', ALL_QSTORE_REGS) + +CONST('I', TCG_CT_CONST_S16) +CONST('J', TCG_CT_CONST_U16) +CONST('M', TCG_CT_CONST_MONE) +CONST('T', TCG_CT_CONST_S32) +CONST('U', TCG_CT_CONST_U32) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be10363956..78d3470f3c 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 18ee989f95..c97f95f3cf 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -218,64 +218,6 @@ static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_uni= t *target) return false; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'A': case 'B': case 'C': case 'D': - tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A'); - break; - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'v': - ct->regs =3D 0xffffffff00000000ull; - break; - case 'L': /* qemu_ld constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->regs, TCG_REG_R5); -#endif - break; - case 'S': /* qemu_st constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->regs, TCG_REG_R6); -#endif - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_U16; - break; - case 'M': - ct->ct |=3D TCG_CT_CONST_MONE; - break; - case 'T': - ct->ct |=3D TCG_CT_CONST_S32; - break; - case 'U': - ct->ct |=3D TCG_CT_CONST_U32; - break; - case 'W': - ct->ct |=3D TCG_CT_CONST_WSZ; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rh7bsPAA/9+Eab4XLXyBRxwo882az2z0pvk2WgOaAN8=; b=eS9kQpMT7d1nxQeK20G/nwJ/+ZlKzIxNEebr8nosWzKLgX24I2/UoCdF9qN8ooGPM5 JIMJSU+7DUmbDeixpBIifMgs2PpzxEXjHJDiG0/CPScHLGKMUuI+o4oY2RHhklQvnZIm xNdBpsPMvQjHzsbL/j2Eii205W6bzWAT5JsLWK3kjuAleWdlDrItSSzCpE3ncU+5srnc nyCHYHJHyxioNmUUB97lclFY2FOTt2LjJCd8zQp1mEaK5sHVY+1keYqgQImLaMcSEYIo FReKmRrSy4sZvKkanUwOHwg54uTCoIAOFyD7rzRPK9jwX4CK3akcDS0H2bsXE/MQtxzu 6gtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rh7bsPAA/9+Eab4XLXyBRxwo882az2z0pvk2WgOaAN8=; b=eoKs/60HVxG1NqAa3DzwVWwHRVpdRjCdIOGoP/QfD/uDOiVn1X1Sg/YhwLkju+xjQa mntoUyztBRfLvhG4u1oD2czMFq4rjvPuskTckY+wybgdqXGM1c4NonxiBEz4WMr3J8Ep pPbJCmwJHxKUeE8YkmarOt9pfRMO+mOglMaiixX43leee1V+RjzIbxM6I6opXL0V7YLY LbHd4hSDPa3rleHPJwZZ2pfj9xge6F2tZln25OQL4ktlUoth/xJHyRZxHvAyU4oSDfrI Inv6eZ0gr6g09K88Ey6oO2BEI88KKBJ8s61BmuyNRqJ315wP9IfjJlN5o0kkKyWxxnu2 L9gA== X-Gm-Message-State: AOAM5327IC4pZZtSgZzbT3HvlV11KvQa44Cc6imiiX7Nl7/Sn0yqqAlN iqa9LGeHe7NX6jqX7SEZY1WboBnBcy3Cyw== X-Google-Smtp-Source: ABdhPJzHXqcQg47B/NQvvh2/0Wcn1KkSgVSDzWd8e0fjdvhH+iza5r7vekc6BBnL/JnqGZoF8Uorxg== X-Received: by 2002:a17:902:8687:b029:dc:2a2c:e99b with SMTP id g7-20020a1709028687b02900dc2a2ce99bmr23861489plo.37.1608703334983; Tue, 22 Dec 2020 22:02:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/22] tcg/tci: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:49 -0800 Message-Id: <20201223060204.576856-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-constr.h | 9 +++++++++ tcg/tci/tcg-target.h | 2 ++ tcg/tci/tcg-target.c.inc | 14 -------------- 3 files changed, 11 insertions(+), 14 deletions(-) create mode 100644 tcg/tci/tcg-target-constr.h diff --git a/tcg/tci/tcg-target-constr.h b/tcg/tci/tcg-target-constr.h new file mode 100644 index 0000000000..ddf57ca9d0 --- /dev/null +++ b/tcg/tci/tcg-target-constr.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +/* + * TCI target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) +REGS('L', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) +REGS('S', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8c1c1d265d..cd3dee51bb 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,4 +210,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, /* no need to flush icache explicitly */ } =20 +#define TCG_TARGET_CONSTR_H + #endif /* TCG_TARGET_H */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 50a08bef03..9ac6da2e21 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -384,20 +384,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -/* Parse target specific constraints. */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': - ct->regs =3D BIT(TCG_TARGET_NB_REGS) - 1; - break; - default: - return NULL; - } - return ct_str; -} - #if defined(CONFIG_DEBUG_TCG_INTERPRETER) /* Show current bytecode. Used by tcg interpreter. */ void tci_disas(uint8_t opc) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608703901; cv=none; d=zohomail.com; s=zohoarc; b=K8o8AmS6kLxFwutctBscEZphyEPT4znN6iTfDL2vrG6T6ZAcoVeSzmpCaZwXVJ/MzXYuO0RqvGCloMqYjylwziYOb6PUTvz3bd7rEVT9fdjkkJvVjebzwxIa9/Y6CbnZqzBIi1nkk6HGuqpMcDcUcaCs8nIGXHM3W1zkTlsPRbY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608703901; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CtwhY3hIgVrDdc8+WsDSaNPBuzHJliRzCFCUKzXl3IE=; b=IsQOMmjz5NstCETJuapH+91AYHPdEXHbMlFRm0bm7ohaQSwJo4zfXT6I9/vsEQob9FXI95sj1FmyWMh8h2WJgPZGGGwTKaoLRo4sAZ0VWL5W0nwLAn4bfnhUGdRFGnKX0fKj8sDRY5thr1ajRRk8RY0+1vwA7r3VcBy0pZftnNI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608703901778161.92463552858203; Tue, 22 Dec 2020 22:11:41 -0800 (PST) Received: from localhost ([::1]:43780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxN5-0000n8-QN for importer@patchew.org; Wed, 23 Dec 2020 01:11:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE5-0008Q8-SA for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:22 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:39001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE2-0000Mv-Pz for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: by mail-pl1-x62b.google.com with SMTP id x18so8605105pln.6 for ; Tue, 22 Dec 2020 22:02:17 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CtwhY3hIgVrDdc8+WsDSaNPBuzHJliRzCFCUKzXl3IE=; b=fBmI1DRdRV4MIZWBG/BYZ/tecK/nmTWnWwfp98toic37VCWkRJyYElfLGR9iTuzDq4 bwhQRf+aXFKyDSQjWuoclCo18GpYudZo+LvKTBwGa0RYfh0Ao+vWVss5rFREkvE7Bm8C DA9EY+mpufSfLGc511Wfnnu8u40puwUoJQdPb0tZZZN4ElcahY/jfmVgCahCKSEfejeb AOXE3c2T11MA4UA6l85HRSZ1Q517QiNn4czWqNjYreIFxlW7vT6WihdkLVYo4PcJhUK+ swLGPHlljLyML4/lyfa6ixKZ2EE3T2gUWSmocFfQqwCKlhWSj8D6b5RZukZdFxMNdJ8z FVRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CtwhY3hIgVrDdc8+WsDSaNPBuzHJliRzCFCUKzXl3IE=; b=OrYU6ddUhlVw3cEG3Uli5vAWNhsoRMks+722BkV38GILjh9FSwZ1VMNhf+NTBjB1G+ C//qJfRirVwjiy+DlDHGRXAOWDMuNWqvvM1loWB2wjlpttL7UFAxlGIrEaHTklFs/D/d au59KruWDaz1wCn/h7vgmTPNCAhyGPJYCEIoPRhTTqkGytdrszgjwsFKFKjJ2SIZ4idD NdhhclJ6HvfpOYVaT6f5nAASjKeujUDYymsNYvagVNsWXfX5b09+L20SgSeytwCNfwkO awq6T/giCc6XhHkIX34GRFY0fgGZfiWjDi7cPmbqm/7uVaj1fyzVot4p9IGfbRpdW7mh mCpw== X-Gm-Message-State: AOAM531si/tmDPTCTaB2Hr/Id8DjYhFwFn6+uPRgmyCstdAyBYfX5Tec a1hIuNlEfDfhuy+uoMBWGXc5jOQaCyFlzA== X-Google-Smtp-Source: ABdhPJxwMK/Mcot+pGx6tgyekqLD2Ix87oolvHD8e/9JZ8VO1jP/l7P6M4NZF44mLT3eAdadOdtq4w== X-Received: by 2002:a17:902:aa43:b029:dc:26a7:7391 with SMTP id c3-20020a170902aa43b02900dc26a77391mr24280121plr.51.1608703336118; Tue, 22 Dec 2020 22:02:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/22] tcg/mips: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:50 -0800 Message-Id: <20201223060204.576856-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-constr.h | 31 ++++++++++++++++++++ tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 56 ------------------------------------ 3 files changed, 32 insertions(+), 56 deletions(-) create mode 100644 tcg/mips/tcg-target-constr.h diff --git a/tcg/mips/tcg-target-constr.h b/tcg/mips/tcg-target-constr.h new file mode 100644 index 0000000000..22f6df0806 --- /dev/null +++ b/tcg/mips/tcg-target-constr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * MIPS target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu +#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) +#define ALL_QSTORE_REGS \ + (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ + ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ + : (1 << TCG_REG_A1))) +#else +#define ALL_QLOAD_REGS NOA0_REGS +#define ALL_QSTORE_REGS NOA0_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_QLOAD_REGS) +REGS('S', ALL_QSTORE_REGS) + +CONST('I', TCG_CT_CONST_U16) +CONST('J', TCG_CT_CONST_S16) +CONST('K', TCG_CT_CONST_P2M1) +CONST('N', TCG_CT_CONST_N16) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d849..f4a79bcad1 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,5 +217,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41be574e89..d0b674582a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -189,62 +189,6 @@ static inline bool is_p2m1(tcg_target_long val) return val && ((val + 1) & val) =3D=3D 0; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch(*ct_str++) { - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'L': /* qemu_ld input arg constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->regs, TCG_REG_A2); - } -#endif - break; - case 'S': /* qemu_st constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->regs, TCG_REG_A2); - tcg_regset_reset_reg(ct->regs, TCG_REG_A3); - } else { - tcg_regset_reset_reg(ct->regs, TCG_REG_A1); - } -#endif - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_U16; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_S16; - break; - case 'K': - ct->ct |=3D TCG_CT_CONST_P2M1; - break; - case 'N': - ct->ct |=3D TCG_CT_CONST_N16; - break; - case 'W': - ct->ct |=3D TCG_CT_CONST_WSZ; - break; - case 'Z': - /* We are cheating a bit here, using the fact that the register - ZERO is also the register number 0. Hence there is no need - to check for const_args in each instruction. */ - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704078; cv=none; d=zohomail.com; s=zohoarc; b=lwPIzdbRSVx6WFEjrB0iDCf8aL/6C3J7adwC9y6TO+eOwgNCRbmJwLPFQdquhTuLmaUeJB9cMajXwXc8tAa/gWf2G9zGh2VN/5TXWNkU+7rIO1zFOaydTd9uireO34rhm0khSa6Rdv9isJUF34AMD9X1hdmTGTrMXUuZW1t34YA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704078; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1Y85WkunXwYTbEnJROwkrffmDCY/UpF3UWrZcQqlD/E=; b=gDmr+7M9i/bCjft/SXCwpMV5t441SdeBH6640uD7QQqEff5vFedbZHpSFn8DvyP902h8bxiGlw7SdfBsR2HFyxn/wqnDOmhgfVZm+XMvp01V7Vy+dyVID45zftYI5DQw7JNTcwnHlokUceSQz8g964rOLHtqTRnDUkyo2EymSxs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608704078155460.5559540964209; Tue, 22 Dec 2020 22:14:38 -0800 (PST) Received: from localhost ([::1]:51408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxPw-0003wH-PY for importer@patchew.org; Wed, 23 Dec 2020 01:14:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEE-0008RV-1E for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:34517) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE2-0000NZ-RR for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:28 -0500 Received: by mail-pl1-x629.google.com with SMTP id t6so8614650plq.1 for ; Tue, 22 Dec 2020 22:02:18 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1Y85WkunXwYTbEnJROwkrffmDCY/UpF3UWrZcQqlD/E=; b=PjjK3AYMoheYlh8Onx724Ybsuc879EHOlx9y8DnoKGQOFQraamYPAMF2WwxbHvWlPQ QaIvM/s8dokW6DTHwqV4yQBsC7Y5sXWH7VuIx8+IgPipcMU21P9QMXip2GAynmAMYc2P 3tNBi6k4/LL1MBh7KUw2A/L225uo5J+DpdXIRN3YO5yDWVKWixPZVhsQ9VFleSb4zJBY RxWTQUy0Vp0O4vuB3nMfycvedUZ+ubqWoDBPkiW0cTxfyGc8MtkJ/O93iF86kpXDPUf3 jCGEpMoq2WanRHTXDVGlPfYGZMDncktAZh728ARx2VHniTVjV0t8lpS4iYlQdtpEzSqp Um0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Y85WkunXwYTbEnJROwkrffmDCY/UpF3UWrZcQqlD/E=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Alistair Francis --- tcg/riscv/tcg-target-constr.h | 24 +++++++++++++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 39 ----------------------------------- 3 files changed, 25 insertions(+), 39 deletions(-) create mode 100644 tcg/riscv/tcg-target-constr.h diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h new file mode 100644 index 0000000000..5daf2e6a5b --- /dev/null +++ b/tcg/riscv/tcg-target-constr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * RISC-V target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu + +#ifdef CONFIG_SOFTMMU +#define ALL_QLDST_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \ + (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \ + (1 << TCG_REG_A5))) +#else +#define ALL_QLDST_REGS ALL_GENERAL_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_QLDST_REGS) + +CONST('I', TCG_CT_CONST_S12) +CONST('N', TCG_CT_CONST_N12) +CONST('M', TCG_CT_CONST_M12) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..ff8ff43a46 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d536f3ccc1..33047c1951 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -131,45 +131,6 @@ static inline tcg_target_long sextreg(tcg_target_long = val, int pos, int len) } } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'L': - /* qemu_ld/qemu_st constraint */ - ct->regs =3D 0xffffffff; - /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ -#if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); -#endif - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_S12; - break; - case 'N': - ct->ct |=3D TCG_CT_CONST_N12; - break; - case 'M': - ct->ct |=3D TCG_CT_CONST_M12; - break; - case 'Z': - /* we can use a zero immediate as a zero register argument. */ - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704093; cv=none; d=zohomail.com; s=zohoarc; b=LAcoZWZcwk8w9AAkQ08+JdwdnkdMmGOPiSbmThSZ6t76BzAvV23epv4iqUxppJhzIc68ReR3DXw6bAHiFngRGYs56XDhxc60GT22KSwFZWY2HJ0WPjUIW1RwSJe7M05mfvKxtYMND+nL6t2TWP2QuEsBdj0F909J/KHAAq643GY= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-constr.h | 15 ++++++++++++++ tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.c.inc | 40 ------------------------------------ 3 files changed, 16 insertions(+), 40 deletions(-) create mode 100644 tcg/s390/tcg-target-constr.h diff --git a/tcg/s390/tcg-target-constr.h b/tcg/s390/tcg-target-constr.h new file mode 100644 index 0000000000..885e91e19b --- /dev/null +++ b/tcg/s390/tcg-target-constr.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * S390 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +REGS('r', 0xffff) +REGS('L', 0xffff & ~((1 << TCG_REG_R2) | (1 << TCG_REG_R3) | (1 << TCG_REG= _R4))) +REGS('a', 1u << TCG_REG_R2) +REGS('b', 1u << TCG_REG_R3) + +CONST('A', TCG_CT_CONST_S33) +CONST('I', TCG_CT_CONST_S16) +CONST('J', TCG_CT_CONST_S32) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 63c8797bd3..3aff3cc572 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,5 +162,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index c5e096449b..d00d78f0b9 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -402,46 +402,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return false; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': /* all registers */ - ct->regs =3D 0xffff; - break; - case 'L': /* qemu_ld/st constraint */ - ct->regs =3D 0xffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - break; - case 'a': /* force R2 for division */ - ct->regs =3D 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R2); - break; - case 'b': /* force R3 for division */ - ct->regs =3D 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R3); - break; - case 'A': - ct->ct |=3D TCG_CT_CONST_S33; - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target-constr.h | 16 ++++++++++++++ tcg/sparc/tcg-target.h | 1 + tcg/sparc/tcg-target.c.inc | 39 ----------------------------------- 3 files changed, 17 insertions(+), 39 deletions(-) create mode 100644 tcg/sparc/tcg-target-constr.h diff --git a/tcg/sparc/tcg-target-constr.h b/tcg/sparc/tcg-target-constr.h new file mode 100644 index 0000000000..379eb83ca4 --- /dev/null +++ b/tcg/sparc/tcg-target-constr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Sparc target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define RESERVE_QLDST (7u << TCG_REG_O0) /* O0, O1, O2 */ + +REGS('r', 0xffffffff) +REGS('R', ALL_64) +REGS('s', 0xffffffff & ~RESERVE_QLDST) +REGS('S', ALL_64 & ~RESERVE_QLDST) + +CONST('I', TCG_CT_CONST_S11) +CONST('J', TCG_CT_CONST_S13) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 633841ebf2..bfee6191b3 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,5 +179,6 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6775bd30fc..c92742aaec 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -319,45 +319,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'R': - ct->regs =3D ALL_64; - break; - case 'A': /* qemu_ld/st address constraint */ - ct->regs =3D TARGET_LONG_BITS =3D=3D 64 ? ALL_64 : 0xffffffff; - reserve_helpers: - tcg_regset_reset_reg(ct->regs, TCG_REG_O0); - tcg_regset_reset_reg(ct->regs, TCG_REG_O1); - tcg_regset_reset_reg(ct->regs, TCG_REG_O2); - break; - case 's': /* qemu_st data 32-bit constraint */ - ct->regs =3D 0xffffffff; - goto reserve_helpers; - case 'S': /* qemu_st data 64-bit constraint */ - ct->regs =3D ALL_64; - goto reserve_helpers; - case 'I': - ct->ct |=3D TCG_CT_CONST_S11; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_S13; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704634; cv=none; d=zohomail.com; s=zohoarc; b=YBM8/YuHiwWLuq4FpH68NzAqin/+JsIXKNQwljhkZKRVyVzpPLI9RwV/Y7KMvCBapaERODcr0Sx53Ml1F8qwSo/FoypIsXLmkH0hskNb7skdG/WZL6t4sjGxUwKPc3KbAbkBBSOID1P6mKTUQB52XwOx9X2mWliOiurVkYwAKbA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704634; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V4vB0rW5AGYTUzpH9bZPj6pKd188ROq1dP7ocy5w9zA=; b=BrNBGaQVkLkxcCDVsmplJKp3fMqhg/jOiWq73NkkGKfQUKwgeIRx4p8oYI+K7i5NPdpqiI88T8Uikhe0iLdECpPIHds6vWE1sclxIB40Qqt6VX7MYkIe5aiC5lpYCPXh+9IUr7IhTp2xbjgDvdU/g27bOhyKo/ttrq9ZSTgsCfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608704634096509.19549122904664; Tue, 22 Dec 2020 22:23:54 -0800 (PST) Received: from localhost ([::1]:40430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxYu-000320-Q2 for importer@patchew.org; Wed, 23 Dec 2020 01:23:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEL-0008Sb-5Z for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:37 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:37332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE8-0000Nv-2k for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:36 -0500 Received: by mail-pl1-x62e.google.com with SMTP id be12so8604907plb.4 for ; Tue, 22 Dec 2020 22:02:21 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=V4vB0rW5AGYTUzpH9bZPj6pKd188ROq1dP7ocy5w9zA=; b=GE+Gwgyj6oY0a61WS22zqwLII2E100SUH248bc2UY910kYxqqkC0kHVmbu++okZfSu WYSieScYT58mWCKbbJGiCoWIHE5EYzkxvwYqfn8R9GqVVPdnm8PPV1TDDK7gT78Z8o1y bQ0j/FTTWyX+Qn363sSKstlEqogiM3O32epFpiJQrj2+uoxRKtouPvjVIcDlrfxMVdj7 KKNldjyPkNI4dRrgMXKHHoedbik/wYRpO80b7uzu4ZWzSaFet7x8vAi4WaIiZPoEJLoo 8aQ/1CqRQDoAj5/dNwimTWDph0PRRcPC2cKpCcvbBeSpPn/wCyLa8EOSFmqFyRTaaEOi 1DCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V4vB0rW5AGYTUzpH9bZPj6pKd188ROq1dP7ocy5w9zA=; b=q+lwRThBk8EpttuJtNpWUh4nLVNJtJ0kWuOQP0I5DKm0qmbJPig4Y2Qv9ptVvypoyT LB0uN9c1E20+lpxTnFZtt4PUF8G8fsqHVSORMs9oG6Mr3kYDSGAdI+PUdeqCDCqy8QXv 1qOWmto7w3x/qoWNYlp4Tk5X5FN3YFC4R/s6o7Qelvv2g6HJCEHOmuxm3MAarnGsHdcB 9JB6Cb5YbqKI11A2MdfSsjBYgwdWXF7aytXSb3hU8OtAutyoFwCEyezOyd/VmZHu0qW+ iVQa7kpR06tZrKit3NNiQu/HAFf4vnnAVNvXadvonbkWRzaaqATH1zTWMaIN9SOy39yk uF8A== X-Gm-Message-State: AOAM532+oeJB9Bv++Dgc2oEmJYTuo8ItzCj8rXn2xOHvU7AHx7IsYV2c L8xVs7+ny5qWeLLYvYzU76uMQPle2QvA6w== X-Google-Smtp-Source: ABdhPJyAMk2vNGozQ27HnaPF9SIhV5vwxlHSYOnAbQxHnfQFWkLFOQXo5s3ITxrScU/Of5pdK+Ul8Q== X-Received: by 2002:a17:90a:67ce:: with SMTP id g14mr25600413pjm.33.1608703340644; Tue, 22 Dec 2020 22:02:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H Date: Tue, 22 Dec 2020 22:01:54 -0800 Message-Id: <20201223060204.576856-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All backends have now been converted to tcg-target-constr.h, so we can remove the fallback code. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 2 -- tcg/tcg.c | 16 ---------------- 10 files changed, 26 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index ca7af5a589..663dd0b95e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 6f058d6d9b..17e771374d 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7c405e166d..abd4ac7fc0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index f4a79bcad1..c6b091d849 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif -#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 78d3470f3c..be10363956 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ff8ff43a46..032439d806 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 3aff3cc572..63c8797bd3 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index bfee6191b3..633841ebf2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H =20 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index cd3dee51bb..8c1c1d265d 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, /* no need to flush icache explicitly */ } =20 -#define TCG_TARGET_CONSTR_H - #endif /* TCG_TARGET_H */ diff --git a/tcg/tcg.c b/tcg/tcg.c index f5b53d739e..2bde926315 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -102,10 +102,6 @@ static void tcg_register_jit_int(void *buf, size_t siz= e, __attribute__((unused)); =20 /* Forward declarations for functions declared and used in tcg-target.c.in= c. */ -#ifndef TCG_TARGET_CONSTR_H -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e); -#endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); @@ -2288,7 +2284,6 @@ static void process_op_defs(TCGContext *s) ct_str++; break; =20 -#ifdef TCG_TARGET_CONSTR_H /* Include all of the target-specific constraints. */ =20 #undef CONST @@ -2304,17 +2299,6 @@ static void process_op_defs(TCGContext *s) default: /* Typo in TCGTargetOpDef constraint. */ g_assert_not_reached(); -#else - default: - { - TCGType type =3D (def->flags & TCG_OPF_64BIT - ? TCG_TYPE_I64 : TCG_TYPE_I32); - ct_str =3D target_parse_constraint(&def->args_ct[i= ], - ct_str, type); - /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str !=3D NULL); - } -#endif } } } --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704365; cv=none; d=zohomail.com; s=zohoarc; b=Hi/6tcA6hFsTNNK4EzfXfKAsnb48MCwc+k30vA0JJuUaIF/2zZsewY7IdM2BGAQ2HJCVput4F4Go2rAi7dJawW7Za6mb1j9e1Tey2y6a+zFxXfH0guak0jK8i/jF2Mwnrdoc2r2J/JteatBdYyrH6rbSaI50AibfkzcH1DKc+N0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704365; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+YifPKBjeNPD3+AdzdyhluVeDh6aW7Lq7n/ZdL+ewjA=; b=W/sZ1qbDlzBFgiUa2bxMgtJzZAZSrOOjdbE7KaJ/SIMEIg3iJ/+et8jowK7dbu9Un+QbucdzSfZXybdUqZ1WynzAX6DFQQiEkNf7Y8ucNCiKuRJEzRBUr651Xvm9R1odWGfOMVjeVvzj8IN9eVKPCw1r4zGD+l4eiPTlHwT4t1A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160870436530885.38458198864635; Tue, 22 Dec 2020 22:19:25 -0800 (PST) Received: from localhost ([::1]:60116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxUa-0007jf-46 for importer@patchew.org; Wed, 23 Dec 2020 01:19:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEG-0008Ra-PD for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:35770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE8-0000OE-39 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:31 -0500 Received: by mail-pj1-x102d.google.com with SMTP id b5so2623662pjl.0 for ; Tue, 22 Dec 2020 22:02:23 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+YifPKBjeNPD3+AdzdyhluVeDh6aW7Lq7n/ZdL+ewjA=; b=ssywNbmrhfbHmx6kvvyMkon5Gxxy/W+yIo1dBlrfE74KjhnDM1+LHQ6/kan98pk9sY MnA6wVb20K3k/qJSAqJ+rDSmG4c+S3NbQAd+9533vAwXOAJt3rfMvJIbdYivAX50x7N+ UkPJpxHfPsaZVtFBxTSOq03XH32Yp9cxwIQ5Bvx2r1Hy16l07S6SHraJMBxNIGoDEEPK ITYPH0B6fkb8MLNGrx0Ff26ab31IErFKHf/kulnEfH6FCxvUeAaYEIXr3XPcI6DQNhhD mFjr38OIHpnPG6cVeFA6/l7AQIU49lCL+mmUhIzvyhui0J1MMoIdYhFoH47OwDVvyd0u ERpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+YifPKBjeNPD3+AdzdyhluVeDh6aW7Lq7n/ZdL+ewjA=; b=OyqQgGEvLJftmLWmBfcyQtCZKG+iT+eAdzq/9pHEbDmd7aaIjnlQaeXu/LHXITQcmb AN+zmE5mDhR74SmkVqsVE6W6g0vS7S0xUywo321BUGZUS8wn0n9hwrqRvro9SIt3TgPI de8wIIS5ED3V44xZjHrG2EDk5UQbgGnWYd47+90aCqjpKUBuaAHpNaeCqaqrgGZCSsTS FOKljLfMpLHTfRlOB3AOLKVNDauxO9G9zJyhJmwCIEOlpZYSTsA3pxC+XizXmvgL9ohK H1fTb8ExuEFbuFzxBVhVJhc7lpO11vqA4gQ4tmj5df7CVkOvwIfV8+iqHsm9xicVwFI1 P9Pw== X-Gm-Message-State: AOAM532F3fzf003S+RruJGf4csIps9LLwrdb38U1z4qfbM1ZrTDZjowf xV6gJ5xbVOLMJNGeDkM0cRJ0M5eJ0gjO/g== X-Google-Smtp-Source: ABdhPJxOAHPBGYhDUrkwmqiMwzTOpSIvnp2r7uXnUBVqokCOSkg9bOnc04zTfpvDVX9YqE1fN2CdJA== X-Received: by 2002:a17:90a:bf05:: with SMTP id c5mr24783970pjs.95.1608703341906; Tue, 22 Dec 2020 22:02:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:01:55 -0800 Message-Id: <20201223060204.576856-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This exports the constraint sets from tcg_target_op_def to a place we will be able to manipulate more in future. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-conset.h | 44 ++++++++ tcg/i386/tcg-target.h | 1 + tcg/tcg.c | 126 +++++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 189 ++++++++++++----------------------- 4 files changed, 236 insertions(+), 124 deletions(-) create mode 100644 tcg/i386/tcg-target-conset.h diff --git a/tcg/i386/tcg-target-conset.h b/tcg/i386/tcg-target-conset.h new file mode 100644 index 0000000000..5a4f991d78 --- /dev/null +++ b/tcg/i386/tcg-target-conset.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: MIT */ +/* + * i386 target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(qi, r) +C_O0_I2(re, r) +C_O0_I2(ri, r) +C_O0_I2(r, re) +C_O0_I2(x, r) +C_O0_I3(L, L, L) +C_O0_I4(L, L, L, L) +C_O0_I4(r, r, ri, ri) +C_O1_I1(r, 0) +C_O1_I1(r, L) +C_O1_I1(r, q) +C_O1_I1(r, r) +C_O1_I1(x, r) +C_O1_I1(x, x) +C_O1_I2(Q, 0, Q) +C_O1_I2(q, r, re) +C_O1_I2(r, 0, ci) +C_O1_I2(r, 0, r) +C_O1_I2(r, 0, re) +C_O1_I2(r, 0, reZ) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, L, L) +C_O1_I2(r, r, re) +C_O1_I2(r, r, ri) +C_O1_I2(x, x, x) +C_N1_I2(r, r, r) +C_N1_I2(r, r, rW) +C_O1_I3(x, x, x, x) +C_O1_I4(r, r, re, r, 0) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(r, r, L) +C_O2_I2(a, d, a, r) +C_O2_I2(r, r, L, L) +C_O2_I3(a, d, 0, 1, r) +C_O2_I4(r, r, 0, 1, re, re) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abd4ac7fc0..74a2566900 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 2bde926315..c58d728ca5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -68,7 +68,11 @@ /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); +#ifdef TCG_TARGET_CONSET_H +static int tcg_target_op_def(TCGOpcode); +#else static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); +#endif static void tcg_target_qemu_prologue(TCGContext *s); static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); @@ -340,6 +344,121 @@ static void set_jmp_reset_offset(TCGContext *s, int w= hich) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 +#ifdef TCG_TARGET_CONSET_H +#define C_PFX1(P, A) P##A +#define C_PFX2(P, A, B) P##A##_##B +#define C_PFX3(P, A, B, C) P##A##_##B##_##C +#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D +#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E +#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F + +/* Define an enumeration for the various combinations. */ + +#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), +#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), +#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), +#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), + +#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), +#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), +#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), +#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I= 4), + +#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), + +#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), +#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), +#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I= 3), +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4), + +typedef enum { +#include "tcg-target-conset.h" +} TCGConstraintSetIndex; + + +#undef C_O0_I1 +#undef C_O0_I2 +#undef C_O0_I3 +#undef C_O0_I4 +#undef C_O1_I1 +#undef C_O1_I2 +#undef C_O1_I3 +#undef C_O1_I4 +#undef C_N1_I2 +#undef C_O2_I1 +#undef C_O2_I2 +#undef C_O2_I3 +#undef C_O2_I4 + +/* Put all of the constraint sets into an array, indexed by the enum. */ + +#define C_O0_I1(I1) { .args_ct_str =3D { #I1 } }, +#define C_O0_I2(I1, I2) { .args_ct_str =3D { #I1, #I2 } }, +#define C_O0_I3(I1, I2, I3) { .args_ct_str =3D { #I1, #I2, #I3= } }, +#define C_O0_I4(I1, I2, I3, I4) \ + { .args_ct_str =3D { #I1, #I2, #I3, #I4 } }, + +#define C_O1_I1(O1, I1) { .args_ct_str =3D { #O1, #I1 } }, +#define C_O1_I2(O1, I1, I2) { .args_ct_str =3D { #O1, #I1, #I2= } }, +#define C_O1_I3(O1, I1, I2, I3) \ + { .args_ct_str =3D { #O1, #I1, #I2, #I3 } }, +#define C_O1_I4(O1, I1, I2, I3, I4) \ + { .args_ct_str =3D { #O1, #I1, #I2, #I3, #I4 } }, + +#define C_N1_I2(O1, I1, I2) \ + { .args_ct_str =3D { "&" #O1, #I1, #I2 } }, + +#define C_O2_I1(O1, O2, I1) \ + { .args_ct_str =3D { #O1, #O2, #I1 } }, +#define C_O2_I2(O1, O2, I1, I2) \ + { .args_ct_str =3D { #O1, #O2, #I1, #I2 } }, +#define C_O2_I3(O1, O2, I1, I2, I3) \ + { .args_ct_str =3D { #O1, #O2, #I1, #I2, #I3 } }, +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + { .args_ct_str =3D { #O1, #O2, #I1, #I2, #I3, #I4 } }, + +static const TCGTargetOpDef constraint_sets[] =3D { +#include "tcg-target-conset.h" +}; + + +#undef C_O0_I1 +#undef C_O0_I2 +#undef C_O0_I3 +#undef C_O0_I4 +#undef C_O1_I1 +#undef C_O1_I2 +#undef C_O1_I3 +#undef C_O1_I4 +#undef C_N1_I2 +#undef C_O2_I1 +#undef C_O2_I2 +#undef C_O2_I3 +#undef C_O2_I4 + +/* Expand the enumerator to be returned from tcg_target_op_def(). */ + +#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) +#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) +#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) +#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) + +#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) +#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) +#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) +#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I= 4) + +#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) + +#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) +#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) +#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I= 3) +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) + +#endif /* TCG_TARGET_CONSET_H */ + #include "tcg-target.c.inc" =20 /* compare a pointer @ptr and a tb_tc @s */ @@ -2248,9 +2367,16 @@ static void process_op_defs(TCGContext *s) continue; } =20 +#ifdef TCG_TARGET_CONSET_H + i =3D tcg_target_op_def(op); + /* Missing TCGTargetOpDef entry. */ + tcg_debug_assert(i >=3D 0 && i < ARRAY_SIZE(constraint_sets)); + tdefs =3D &constraint_sets[i]; +#else tdefs =3D tcg_target_op_def(op); /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(tdefs !=3D NULL); +#endif =20 for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 981dd9aca4..708d465cbb 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2903,39 +2903,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef ri_r =3D { .args_ct_str =3D { "ri", "r" } = }; - static const TCGTargetOpDef re_r =3D { .args_ct_str =3D { "re", "r" } = }; - static const TCGTargetOpDef qi_r =3D { .args_ct_str =3D { "qi", "r" } = }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_q =3D { .args_ct_str =3D { "r", "q" } }; - static const TCGTargetOpDef r_re =3D { .args_ct_str =3D { "r", "re" } = }; - static const TCGTargetOpDef r_0 =3D { .args_ct_str =3D { "r", "0" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_re =3D { .args_ct_str =3D { "r", "r", = "re" } }; - static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; - static const TCGTargetOpDef r_0_re =3D { .args_ct_str =3D { "r", "0", = "re" } }; - static const TCGTargetOpDef r_0_ci =3D { .args_ct_str =3D { "r", "0", = "ci" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef r_r_L =3D { .args_ct_str =3D { "r", "r", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; - static const TCGTargetOpDef x_x =3D { .args_ct_str =3D { "x", "x" } }; - static const TCGTargetOpDef x_x_x =3D { .args_ct_str =3D { "x", "x", "= x" } }; - static const TCGTargetOpDef x_x_x_x - =3D { .args_ct_str =3D { "x", "x", "x", "x" } }; - static const TCGTargetOpDef x_r =3D { .args_ct_str =3D { "x", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2949,22 +2921,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st8_i64: - return &qi_r; + return C_O0_I2(qi, r); + case INDEX_op_st16_i32: case INDEX_op_st16_i64: case INDEX_op_st_i32: case INDEX_op_st32_i64: - return &ri_r; + return C_O0_I2(ri, r); + case INDEX_op_st_i64: - return &re_r; + return C_O0_I2(re, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_re; + return C_O1_I2(r, r, re); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_mul_i32: @@ -2973,24 +2948,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return &r_0_re; + return C_O1_I2(r, 0, re); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: - { - static const TCGTargetOpDef and - =3D { .args_ct_str =3D { "r", "0", "reZ" } }; - return ∧ - } - break; + return C_O1_I2(r, 0, reZ); + case INDEX_op_andc_i32: case INDEX_op_andc_i64: - { - static const TCGTargetOpDef andc - =3D { .args_ct_str =3D { "r", "r", "rI" } }; - return &andc; - } - break; + return C_O1_I2(r, 0, rI); =20 case INDEX_op_shl_i32: case INDEX_op_shl_i64: @@ -2998,16 +2964,17 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i32: case INDEX_op_sar_i64: - return have_bmi2 ? &r_r_ri : &r_0_ci; + return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); + case INDEX_op_rotl_i32: case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - return &r_0_ci; + return C_O1_I2(r, 0, ci); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_re; + return C_O0_I2(r, re); =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -3019,13 +2986,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_not_i32: case INDEX_op_not_i64: case INDEX_op_extrh_i64_i32: - return &r_0; + return C_O1_I1(r, 0); =20 case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: - return &r_q; + return C_O1_I1(r, q); + case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: @@ -3040,108 +3008,80 @@ static const TCGTargetOpDef *tcg_target_op_def(TCG= Opcode op) case INDEX_op_sextract_i32: case INDEX_op_ctpop_i32: case INDEX_op_ctpop_i64: - return &r_r; + return C_O1_I1(r, r); + case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &r_0_r; + return C_O1_I2(r, 0, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "Q", "0", "Q" } }; - return &dep; - } + return C_O1_I2(Q, 0, Q); + case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - { - static const TCGTargetOpDef setc - =3D { .args_ct_str =3D { "q", "r", "re" } }; - return &setc; - } + return C_O1_I2(q, r, re); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "re", "r", "0" } }; - return &movc; - } + return C_O1_I4(r, r, re, r, 0); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - =3D { .args_ct_str =3D { "a", "d", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(a, d, 0, 1, r); + case INDEX_op_mulu2_i32: case INDEX_op_mulu2_i64: case INDEX_op_muls2_i32: case INDEX_op_muls2_i64: - { - static const TCGTargetOpDef mul2 - =3D { .args_ct_str =3D { "a", "d", "a", "r" } }; - return &mul2; - } + return C_O2_I2(a, d, a, r); + case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - =3D { .args_ct_str =3D { "r", "r", "0", "1", "re", "re" } = }; - return &arith2; - } + return C_O2_I4(r, r, 0, 1, re, re); + case INDEX_op_ctz_i32: case INDEX_op_ctz_i64: - { - static const TCGTargetOpDef ctz[2] =3D { - { .args_ct_str =3D { "&r", "r", "r" } }, - { .args_ct_str =3D { "&r", "r", "rW" } }, - }; - return &ctz[have_bmi1]; - } + return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); + case INDEX_op_clz_i32: case INDEX_op_clz_i64: - { - static const TCGTargetOpDef clz[2] =3D { - { .args_ct_str =3D { "&r", "r", "r" } }, - { .args_ct_str =3D { "&r", "r", "rW" } }, - }; - return &clz[have_lzcnt]; - } + return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(L, L) : C_O0_I3(L, L, L)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r= , L) + : C_O2_I2(r, r, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &L_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(L, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(L, L= , L) + : C_O0_I4(L, L, L, L)); =20 case INDEX_op_brcond2_i32: - { - static const TCGTargetOpDef b2 - =3D { .args_ct_str =3D { "r", "r", "ri", "ri" } }; - return &b2; - } + return C_O0_I4(r, r, ri, ri); + case INDEX_op_setcond2_i32: - { - static const TCGTargetOpDef s2 - =3D { .args_ct_str =3D { "r", "r", "r", "ri", "ri" } }; - return &s2; - } + return C_O1_I4(r, r, r, ri, ri); =20 case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &x_r; + return C_O1_I1(x, r); + + case INDEX_op_st_vec: + return C_O0_I2(x, r); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3176,21 +3116,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_dup2_vec: #endif - return &x_x_x; + return C_O1_I2(x, x, x); + case INDEX_op_abs_vec: case INDEX_op_dup_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: case INDEX_op_x86_psrldq_vec: - return &x_x; + return C_O1_I1(x, x); + case INDEX_op_x86_vpblendvb_vec: - return &x_x_x_x; + return C_O1_I3(x, x, x, x); =20 default: - break; + g_assert_not_reached(); } - return NULL; } =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704085; cv=none; d=zohomail.com; s=zohoarc; b=lGFwd+K/FK8bcoRA94P2tlovarDGDlYNkREA9Sm2Kwo+thO8X6xh9u5+cMcfpNq0gTvFlFhaoBGHG8il2AiUZ2bqMOYkXQhdHNpOuCiyVk7nwx+J1tPi5/6rPm/fYSv1L2xA1811sRdi1tN8zi2MTuN5LsSHFYow6FzF00/Bp6E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704085; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uRTDlrjsZd2ECIgzVgTpVsKManvsUod3zyWxTNTa0RQ=; b=f4LIzlJyHOG1IBeCUkf321SkVX2sBBQboTME0PCResS1GEPijubc0PsiyWYHKnUzTq0rWny3QcIocp66yvLTvLMQzEvSnF6/TFS/pmTgndHpiQ2CGnWnkPDfTrd+cJfb4+2g+Yao19ip2dbfNoxsj5E+YF3pbprA4dCSqT2B36w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16087040853236.595545004542942; Tue, 22 Dec 2020 22:14:45 -0800 (PST) Received: from localhost ([::1]:51730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxQ4-000443-5q for importer@patchew.org; Wed, 23 Dec 2020 01:14:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEG-0008Rc-S4 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:34029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEA-0000OQ-Tx for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:32 -0500 Received: by mail-pj1-x1035.google.com with SMTP id n3so610589pjm.1 for ; Tue, 22 Dec 2020 22:02:24 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-conset.h | 31 ++++++++++++ tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.c.inc | 86 +++++++++++---------------------- 3 files changed, 60 insertions(+), 58 deletions(-) create mode 100644 tcg/aarch64/tcg-target-conset.h diff --git a/tcg/aarch64/tcg-target-conset.h b/tcg/aarch64/tcg-target-conse= t.h new file mode 100644 index 0000000000..2df8157b15 --- /dev/null +++ b/tcg/aarch64/tcg-target-conset.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * AArch64 target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(lZ, l) +C_O0_I2(r, rA) +C_O0_I2(rZ, r) +C_O0_I2(w, r) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I1(w, r) +C_O1_I1(w, w) +C_O1_I1(w, wr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rA) +C_O1_I2(r, r, rAL) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rL) +C_O1_I2(r, rZ, rZ) +C_O1_I2(w, 0, w) +C_O1_I2(w, w, w) +C_O1_I2(w, w, wN) +C_O1_I2(w, w, wO) +C_O1_I2(w, w, wZ) +C_O1_I3(w, w, w, w) +C_O1_I4(r, r, rA, rZ, rZ) +C_O2_I4(r, r, rZ, rZ, rA, rMZ) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 663dd0b95e..a81f6dadf9 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,5 +159,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 310bc972e3..aaf8918a4b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2541,42 +2541,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, va_end(va); } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef w_w =3D { .args_ct_str =3D { "w", "w" } }; - static const TCGTargetOpDef w_r =3D { .args_ct_str =3D { "w", "r" } }; - static const TCGTargetOpDef w_wr =3D { .args_ct_str =3D { "w", "wr" } = }; - static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; - static const TCGTargetOpDef r_rA =3D { .args_ct_str =3D { "r", "rA" } = }; - static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; - static const TCGTargetOpDef w_0_w =3D { .args_ct_str =3D { "w", "0", "= w" } }; - static const TCGTargetOpDef w_w_wO =3D { .args_ct_str =3D { "w", "w", = "wO" } }; - static const TCGTargetOpDef w_w_wN =3D { .args_ct_str =3D { "w", "w", = "wN" } }; - static const TCGTargetOpDef w_w_wZ =3D { .args_ct_str =3D { "w", "w", = "wZ" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rA =3D { .args_ct_str =3D { "r", "r", = "rA" } }; - static const TCGTargetOpDef r_r_rL =3D { .args_ct_str =3D { "r", "r", = "rL" } }; - static const TCGTargetOpDef r_r_rAL - =3D { .args_ct_str =3D { "r", "r", "rAL" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef ext2 - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "rA", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; - static const TCGTargetOpDef w_w_w_w - =3D { .args_ct_str =3D { "w", "w", "w", "w" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2615,7 +2584,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2624,7 +2593,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: @@ -2632,7 +2601,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return &r_r_rA; + return C_O1_I2(r, r, rA); =20 case INDEX_op_mul_i32: case INDEX_op_mul_i64: @@ -2646,7 +2615,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_remu_i64: case INDEX_op_muluh_i64: case INDEX_op_mulsh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: @@ -2660,7 +2629,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return &r_r_rL; + return C_O1_I2(r, r, rL); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -2672,42 +2641,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_sar_i64: case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rAL; + return C_O1_I2(r, r, rAL); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_rA; + return C_O0_I2(r, rA); =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, rA, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; + return C_O1_I1(r, l); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; + return C_O0_I2(lZ, l); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); =20 case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &ext2; + return C_O1_I2(r, rZ, rZ); =20 case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rA, rMZ); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2725,35 +2694,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: case INDEX_op_aa64_sshl_vec: - return &w_w_w; + return C_O1_I2(w, w, w); case INDEX_op_not_vec: case INDEX_op_neg_vec: case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return &w_w; + return C_O1_I1(w, w); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &w_r; + return C_O1_I1(w, r); + case INDEX_op_st_vec: + return C_O0_I2(w, r); case INDEX_op_dup_vec: - return &w_wr; + return C_O1_I1(w, wr); case INDEX_op_or_vec: case INDEX_op_andc_vec: - return &w_w_wO; + return C_O1_I2(w, w, wO); case INDEX_op_and_vec: case INDEX_op_orc_vec: - return &w_w_wN; + return C_O1_I2(w, w, wN); case INDEX_op_cmp_vec: - return &w_w_wZ; + return C_O1_I2(w, w, wZ); case INDEX_op_bitsel_vec: - return &w_w_w_w; + return C_O1_I3(w, w, w, w); case INDEX_op_aa64_sli_vec: - return &w_0_w; + return C_O1_I2(w, 0, w); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-conset.h | 30 ++++++++++++ tcg/arm/tcg-target.h | 1 + tcg/arm/tcg-target.c.inc | 94 +++++++++++++------------------------ 3 files changed, 63 insertions(+), 62 deletions(-) create mode 100644 tcg/arm/tcg-target-conset.h diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h new file mode 100644 index 0000000000..7e972e70e0 --- /dev/null +++ b/tcg/arm/tcg-target-conset.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Arm target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, rIN) +C_O0_I2(s, s) +C_O0_I3(s, s, s) +C_O0_I4(r, r, rI, rI) +C_O0_I4(s, s, s, s) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, l, l) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rIN) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, r, r, rI, rI) +C_O1_I4(r, r, rIN, rIK, 0) +C_O2_I1(r, r, l) +C_O2_I2(r, r, l, l) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, rIN, rIK) +C_O2_I4(r, r, rI, rI, rIN, rIK) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 17e771374d..918f09239a 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,5 +146,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index ab1b295293..029d58e4b7 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2012,57 +2012,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef s_s =3D { .args_ct_str =3D { "s", "s" } }; - static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef r_r_l =3D { .args_ct_str =3D { "r", "r", "= l" } }; - static const TCGTargetOpDef r_l_l =3D { .args_ct_str =3D { "r", "l", "= l" } }; - static const TCGTargetOpDef s_s_s =3D { .args_ct_str =3D { "s", "s", "= s" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; - static const TCGTargetOpDef r_r_rIN - =3D { .args_ct_str =3D { "r", "r", "rIN" } }; - static const TCGTargetOpDef r_r_rIK - =3D { .args_ct_str =3D { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_r_r - =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l - =3D { .args_ct_str =3D { "r", "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s_s - =3D { .args_ct_str =3D { "s", "s", "s", "s" } }; - static const TCGTargetOpDef br - =3D { .args_ct_str =3D { "r", "rIN" } }; - static const TCGTargetOpDef ext2 - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "rIN", "rIK", "0" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "r", "r", "rIN", "rIK" } }; - static const TCGTargetOpDef sub2 - =3D { .args_ct_str =3D { "r", "r", "rI", "rI", "rIN", "rIK" } }; - static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "r", "r", "rI", "rI" } }; - static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "r", "r", "rI", "rI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: case INDEX_op_bswap16_i32: @@ -2072,62 +2032,72 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ext16u_i32: case INDEX_op_extract_i32: case INDEX_op_sextract_i32: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_setcond_i32: - return &r_r_rIN; + return C_O1_I2(r, r, rIN); + case INDEX_op_and_i32: case INDEX_op_andc_i32: case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); + case INDEX_op_mul_i32: case INDEX_op_div_i32: case INDEX_op_divu_i32: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); + case INDEX_op_or_i32: case INDEX_op_xor_i32: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_brcond_i32: - return &br; + return C_O0_I2(r, rIN); case INDEX_op_deposit_i32: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_extract2_i32: - return &ext2; + return C_O1_I2(r, rZ, rZ); case INDEX_op_movcond_i32: - return &movc; + return C_O1_I4(r, r, rIN, rIK, 0); case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rIN, rIK); case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rI, rIN, rIK); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, rI, rI); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, rI, rI); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS =3D=3D 32 ? &r_l : &r_l_l; + return TARGET_LONG_BITS =3D=3D 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, = l); case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS =3D=3D 32 ? &r_r_l : &r_r_l_l; + return TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, = r, l, l); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS =3D=3D 32 ? &s_s : &s_s_s; + return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, = s); case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS =3D=3D 32 ? &s_s_s : &s_s_s_s; + return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, = s, s, s); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704867; cv=none; d=zohomail.com; s=zohoarc; b=KbILRPMkJoYfgyvccWqcB31j9lT8A/zKgtIju7ZG5MPn/TLNNOlo+KF07puAzf4dj/TVwN3JJGrkejMxTJtf0dd0RW+GkaU3l3oBXzlaXaSXtldnL2B1t64b1OXcYurdH0rwYoh9j49z/F8oQ+fBvVeKdn8Cc9KdU+e9CEiT7IQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704867; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X758HD6K1J6obb9plyMDfKBI50GFn/H1bBv6I/APYbM=; b=Y2LkUrPU9NmcpwrboRanE2cafonH0NE9Q2VrREOE32dZtCamXr+g6vXNEIU26sFQ6GKZpAdCMb6TzHRR2XsNG5PCEAq5DSYukLWtNVmYCWPxWZAumzuTy8IPeBAx+WZCQG68d9F7ze8j9/iPz0IXurhuyd5WVuMxYcEZl59NXow= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608704867345698.2370467012796; Tue, 22 Dec 2020 22:27:47 -0800 (PST) Received: from localhost ([::1]:48794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxcg-0006fY-34 for importer@patchew.org; Wed, 23 Dec 2020 01:27:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEP-0008Tl-KB for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:41 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:40056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEB-0000Q4-JR for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:39 -0500 Received: by mail-pl1-x634.google.com with SMTP id q4so8596856plr.7 for ; Tue, 22 Dec 2020 22:02:26 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X758HD6K1J6obb9plyMDfKBI50GFn/H1bBv6I/APYbM=; b=Er2JoGa/KxiBTlhJjrZ0DNAnCKsHKrwM3JuCQgsGqmij6wIzATl26lelqage4oFBDs 0hQEQtArB/6n88nq8f1FJe2qkbUa+O4CzXh2x8JjZycmCdijkkWB1uWmiXyeGeo2jwO9 3XE3KKByV9sH6F6tJt60S/U7kLSeNhb3/hdFt9LN8g+UlMjx5FQfkigj/eKy7qpsv6Yv /Vvro0frIsxXw5u2C0lhcweG2wDDTwj5w/4dM/Fv2wEDPYU7yJafVYstjPRjqiHLOUQY f9qeZDpRMwh3hzDqXaAWJi85meXo1Oavj1ZjXjqperAkZV28hr1Uo2z9iG4OTNioWfRB 5Xww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X758HD6K1J6obb9plyMDfKBI50GFn/H1bBv6I/APYbM=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-conset.h | 31 ++++++++++++ tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 96 +++++++++++------------------------- 3 files changed, 61 insertions(+), 67 deletions(-) create mode 100644 tcg/mips/tcg-target-conset.h diff --git a/tcg/mips/tcg-target-conset.h b/tcg/mips/tcg-target-conset.h new file mode 100644 index 0000000000..94f8f5f683 --- /dev/null +++ b/tcg/mips/tcg-target-conset.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * MIPS target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I2(SZ, S) +C_O0_I3(SZ, S, S) +C_O0_I3(SZ, SZ, S) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O0_I4(SZ, SZ, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rJ) +C_O1_I2(r, r, rWZ) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, 0) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d849..688d691cda 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,5 +217,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d0b674582a..2ec1d6ac05 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2104,52 +2104,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef SZ_S =3D { .args_ct_str =3D { "SZ", "S" } = }; - static const TCGTargetOpDef rZ_rZ =3D { .args_ct_str =3D { "rZ", "rZ" = } }; - static const TCGTargetOpDef r_r_L =3D { .args_ct_str =3D { "r", "r", "= L" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; - static const TCGTargetOpDef r_r_rJ =3D { .args_ct_str =3D { "r", "r", = "rJ" } }; - static const TCGTargetOpDef SZ_S_S =3D { .args_ct_str =3D { "SZ", "S",= "S" } }; - static const TCGTargetOpDef SZ_SZ_S - =3D { .args_ct_str =3D { "SZ", "SZ", "S" } }; - static const TCGTargetOpDef SZ_SZ_S_S - =3D { .args_ct_str =3D { "SZ", "SZ", "S", "S" } }; - static const TCGTargetOpDef r_rZ_rN - =3D { .args_ct_str =3D { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_rIK - =3D { .args_ct_str =3D { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_rWZ - =3D { .args_ct_str =3D { "r", "r", "rWZ" } }; - static const TCGTargetOpDef r_r_r_r - =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "0" } }; - static const TCGTargetOpDef movc_r6 - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rN", "rN" } }; - static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "rZ" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2182,7 +2141,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2191,14 +2150,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_rJ; + return C_O1_I2(r, r, rJ); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: case INDEX_op_muluh_i32: @@ -2217,20 +2176,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_remu_i64: case INDEX_op_nor_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_muls2_i32: case INDEX_op_mulu2_i32: case INDEX_op_muls2_i64: case INDEX_op_mulu2_i64: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); case INDEX_op_or_i32: case INDEX_op_xor_i32: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: @@ -2241,44 +2200,47 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_sar_i64: case INDEX_op_rotr_i64: case INDEX_op_rotl_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_clz_i64: - return &r_r_rWZ; + return C_O1_I2(r, r, rWZ); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return use_mips32r6_instructions ? &movc_r6 : &movc; - + return (use_mips32r6_instructions + ? C_O1_I4(r, rZ, rZ, rZ, rZ) + : C_O1_I4(r, rZ, rZ, rZ, 0)); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rN, rN); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(rZ, rZ, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &SZ_S : &SZ_S_S); + ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS =3D=3D 32 ? &r_r_L : &r_r_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &SZ_S - : TARGET_LONG_BITS =3D=3D 32 ? &SZ_SZ_S : &SZ_SZ_S_S); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(SZ, S) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(SZ, SZ, S) + : C_O0_I4(SZ, SZ, S, S)); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704375; cv=none; d=zohomail.com; s=zohoarc; b=S9k1Ow3lcrQ3D3K97hOHE6LfSQVP1PTXoUanelIHnKwnAls9QI4/g/+LnsPhRmEmHXoMecuTAbFGZ7m8jlfJ0zVMm9pgWFsyykznOCHIAmFrm07IHEciV8RatMIYSS5zPh49PPJgAE4FsUvjryVbS6P29ScK5hMsKFqgTsiA/zo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704375; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=I5Jif50OCQX6bqPE3vNJ6iG9LjkUrr2qR3pVG1LDHQI=; b=VV2y3gH/BqBOAebehEoHEmTLuGQwhto7N/XS+G/mlmvUy9emt6FE0+gElWVPKZnO7YJSENJEHNkIwKNF0I1GDAZyOqs9AukRXkp7cbF7AeER7zteg363XNKKBUt1HoFCjtgJhLo55++zusw9OOTpv2V99Fkrvci9pX+xy6+l24c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608704375112869.989912362265; Tue, 22 Dec 2020 22:19:35 -0800 (PST) Received: from localhost ([::1]:60410 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxUk-0007qa-0V for importer@patchew.org; Wed, 23 Dec 2020 01:19:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39544) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxET-0008WN-Bd for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:45 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:36128) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxED-0000QE-QY for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:45 -0500 Received: by mail-pf1-x429.google.com with SMTP id t22so9787553pfl.3 for ; Tue, 22 Dec 2020 22:02:28 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-conset.h | 37 ++++++++++ tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.c.inc | 136 +++++++++++++++--------------------- 3 files changed, 94 insertions(+), 80 deletions(-) create mode 100644 tcg/ppc/tcg-target-conset.h diff --git a/tcg/ppc/tcg-target-conset.h b/tcg/ppc/tcg-target-conset.h new file mode 100644 index 0000000000..448ac6d155 --- /dev/null +++ b/tcg/ppc/tcg-target-conset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * PowerPC target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I2(S, S) +C_O0_I2(v, r) +C_O0_I3(S, S, S) +C_O0_I4(r, r, ri, ri) +C_O0_I4(S, S, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, v) +C_O1_I1(v, vr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, rI, ri) +C_O1_I2(r, rI, rT) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rT) +C_O1_I2(r, r, rU) +C_O1_I2(r, r, rZW) +C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) +C_O1_I4(r, r, ri, rZ, rZ) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(L, L, L) +C_O2_I2(L, L, L, L) +C_O2_I4(r, r, rI, rZM, r, r) +C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be10363956..c958faffb7 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index c97f95f3cf..eb8a626ad4 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3425,62 +3425,17 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, va_end(va); } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef S_S =3D { .args_ct_str =3D { "S", "S" } }; - static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef S_S_S =3D { .args_ct_str =3D { "S", "S", "= S" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; - static const TCGTargetOpDef r_r_rT =3D { .args_ct_str =3D { "r", "r", = "rT" } }; - static const TCGTargetOpDef r_r_rU =3D { .args_ct_str =3D { "r", "r", = "rU" } }; - static const TCGTargetOpDef r_rI_ri - =3D { .args_ct_str =3D { "r", "rI", "ri" } }; - static const TCGTargetOpDef r_rI_rT - =3D { .args_ct_str =3D { "r", "rI", "rT" } }; - static const TCGTargetOpDef r_r_rZW - =3D { .args_ct_str =3D { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - =3D { .args_ct_str =3D { "S", "S", "S", "S" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "ri", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "r", "r", "rI", "rZM" } }; - static const TCGTargetOpDef sub2 - =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; - static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; - static const TCGTargetOpDef v_vr =3D { .args_ct_str =3D { "v", "vr" } = }; - static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; - static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; - static const TCGTargetOpDef v_v_v_v - =3D { .args_ct_str =3D { "v", "v", "v", "v" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_ctpop_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: @@ -3496,10 +3451,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: case INDEX_op_ctpop_i64: case INDEX_op_neg_i64: case INDEX_op_not_i64: @@ -3512,7 +3463,16 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -3535,10 +3495,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); + case INDEX_op_mul_i32: case INDEX_op_mul_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_div_i32: case INDEX_op_divu_i32: case INDEX_op_nand_i32: @@ -3553,55 +3515,63 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_divu_i64: case INDEX_op_mulsh_i64: case INDEX_op_muluh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_sub_i32: - return &r_rI_ri; + return C_O1_I2(r, rI, ri); case INDEX_op_add_i64: - return &r_r_rT; + return C_O1_I2(r, r, rT); case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rU; + return C_O1_I2(r, r, rU); case INDEX_op_sub_i64: - return &r_rI_rT; + return C_O1_I2(r, rI, rT); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rZW; + return C_O1_I2(r, r, rZW); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, ri, rZ, rZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, ri, ri); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, ri, ri); case INDEX_op_add2_i64: case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rI, rZM); case INDEX_op_sub2_i64: case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rZM, r, r); =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) + : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &S_S : &S_S_S); + ? C_O0_I2(S, S) + : C_O0_I3(S, S, S)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS =3D=3D 32 ? &L_L_L : &L_L_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(L, L, L) + : C_O2_I2(L, L, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &S_S - : TARGET_LONG_BITS =3D=3D 32 ? &S_S_S : &S_S_S_S); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(S, S) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, S, S) + : C_O0_I4(S, S, S, S)); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3631,22 +3601,28 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_dup2_vec: - return &v_v_v; + return C_O1_I2(v, v, v); + case INDEX_op_not_vec: case INDEX_op_neg_vec: - return &v_v; + return C_O1_I1(v, v); + case INDEX_op_dup_vec: - return have_isa_3_00 ? &v_vr : &v_v; + return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); + case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &v_r; + return C_O1_I1(v, r); + + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_bitsel_vec: case INDEX_op_ppc_msum_vec: - return &v_v_v_v; + return C_O1_I3(v, v, v, v); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704640; cv=none; d=zohomail.com; s=zohoarc; b=SyJpjUbJuqLsGxs28pg1Sgwo4VQ2bcJQOKzbNcQWcViPn6YUBOOtvDc9kpTsTt95XxGHsPd+P/sfudF15exwWWpe0bvfVGHvNg/HO5wwvfkUA4r0M5CIc2s0evgPtFpAicww53tPnuC06YU8OQNqdYWQtUaRQ8BCekouDBRnWlA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704640; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0q5ANbZEj0KFtnrT7+j+pQ6Kp2i0ZGMJCtKydc5+1vo=; b=ipligJ7hhakrFbVniu4nyw4bAyjeSIN89+UD91Z+JdbuEF0frLvVFarhCMeSpvY+c2lBR4ynaU4bE9kz44T96HX7lDL4ox4Qsha4tI5sKYflG0ceH2qMOx2e+OcIbAcnXw3EeOmCH/7XE6etvAhP+I3nXH9gPdzc/fj8cBMYqlY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608704640553926.6805698617702; Tue, 22 Dec 2020 22:24:00 -0800 (PST) Received: from localhost ([::1]:40660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxZ1-000386-IZ for importer@patchew.org; Wed, 23 Dec 2020 01:23:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEU-00006C-VB for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:47 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:55878) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxED-0000Qw-RV for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:46 -0500 Received: by mail-pj1-x102d.google.com with SMTP id lb18so2473933pjb.5 for ; Tue, 22 Dec 2020 22:02:29 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- tcg/riscv/tcg-target-conset.h | 25 +++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------- 3 files changed, 49 insertions(+), 60 deletions(-) create mode 100644 tcg/riscv/tcg-target-conset.h diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h new file mode 100644 index 0000000000..116dd75db2 --- /dev/null +++ b/tcg/riscv/tcg-target-conset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * RISC-V target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(LZ, L) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I3(LZ, L, L) +C_O0_I3(LZ, LZ, L) +C_O0_I4(LZ, LZ, L, L) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..a357962e01 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 33047c1951..d222692704 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1571,50 +1571,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r - =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r - =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef rZ_r - =3D { .args_ct_str =3D { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - =3D { .args_ct_str =3D { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - =3D { .args_ct_str =3D { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - =3D { .args_ct_str =3D { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - =3D { .args_ct_str =3D { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - =3D { .args_ct_str =3D { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef r_r_L - =3D { .args_ct_str =3D { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - =3D { .args_ct_str =3D { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - =3D { .args_ct_str =3D { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - =3D { .args_ct_str =3D { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - =3D { .args_ct_str =3D { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - =3D { .args_ct_str =3D { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rM", "rM" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1646,7 +1607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -1655,7 +1616,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -1665,11 +1626,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); =20 case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); =20 case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: @@ -1687,7 +1648,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_rem_i64: case INDEX_op_remu_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -1695,39 +1656,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); =20 case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; + return C_O2_I4(r, r, rZ, rZ, rM, rM); =20 case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; + return C_O0_I4(rZ, rZ, rZ, rZ); =20 case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; + return C_O1_I4(r, rZ, rZ, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r,= L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS =3D=3D 64 ? &LZ_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(LZ, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(LZ, L= Z, L) + : C_O0_I4(LZ, LZ, L, L)); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608703881; cv=none; d=zohomail.com; s=zohoarc; b=m5YDOwidaqcBNf3XYHRQK3RdWR4eLlhfN/Pz+xY5xrlwY67qtAY/1LCcITSwWdR7B3CAQk57FfnyGx2ZuoZ3WQAbPp+sYPOqlPWb+QcX2qS0wzg7xYD2cpnk+MgJbdTT3vHWFKuz/yuvCkE/mUc31JzjJlAhleXJMeFDvKV8CvU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608703881; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D1cssy5nr73dcyGZN4wFfC1KpMYyeCV3YiIqsmzd9bY=; b=Uh2/bAtiDaXUqaUktcuJs4jSjOg7AVlruO+paaauS66U98SoA+0wOWkO76oalXrdHHZpy0QD1joIwHA9iSfHf3Y7lk9/FVt1bQbOtwxZsBo9ctUp1DSwoai3MNMQDLY3TPAlRLYRK3hQhxsm64+5iDaWDVEzMki0xV2YkdBKUNc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160870388157618.821529029905832; Tue, 22 Dec 2020 22:11:21 -0800 (PST) Received: from localhost ([::1]:43084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxMm-0000UZ-9k for importer@patchew.org; Wed, 23 Dec 2020 01:11:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39494) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEM-0008TF-5l for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:39 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:39428) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEF-0000R7-Op for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:37 -0500 Received: by mail-pg1-x533.google.com with SMTP id f17so9926630pge.6 for ; Tue, 22 Dec 2020 22:02:30 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-conset.h | 24 +++++++ tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.c.inc | 121 +++++++++++++++-------------------- 3 files changed, 76 insertions(+), 70 deletions(-) create mode 100644 tcg/s390/tcg-target-conset.h diff --git a/tcg/s390/tcg-target-conset.h b/tcg/s390/tcg-target-conset.h new file mode 100644 index 0000000000..e68baabbfd --- /dev/null +++ b/tcg/s390/tcg-target-conset.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * S390 target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, 0, rJ) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, r) +C_O1_I4(r, r, ri, r, 0) +C_O1_I4(r, r, ri, rI, 0) +C_O2_I2(b, a, 0, r) +C_O2_I3(b, a, 0, 1, r) +C_O2_I4(r, r, 0, 1, rA, r) +C_O2_I4(r, r, 0, 1, ri, r) +C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 63c8797bd3..78277a8d07 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,5 +162,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index d00d78f0b9..410f63104f 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2274,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; - static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; - static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; - static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; - static const TCGTargetOpDef a2_r - =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; - static const TCGTargetOpDef a2_ri - =3D { .args_ct_str =3D { "r", "r", "0", "1", "ri", "r" } }; - static const TCGTargetOpDef a2_rA - =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2308,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: + return C_O1_I1(r, r); + case INDEX_op_st8_i32: case INDEX_op_st8_i64: case INDEX_op_st16_i32: @@ -2315,11 +2301,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &r_r; + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_ri; + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_and_i32: @@ -2328,35 +2325,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); =20 case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_r= I); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, ri) + : C_O1_I2(r, 0, rI)); + case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, rJ) + : C_O1_I2(r, 0, rI)); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); - - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_r_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2379,63 +2374,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_extu_i32_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_clz_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I1(r, r); =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_L; + return C_O1_I1(r, L); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return &L_L; + return C_O0_I2(L, L); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "rZ", "r" } }; - return &dep; - } + return C_O1_I2(r, rZ, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "ri", "r", "0" } }; - static const TCGTargetOpDef movc_l - =3D { .args_ct_str =3D { "r", "r", "ri", "rI", "0" } }; - return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &= movc); - } + return (s390_facilities & FACILITY_LOAD_ON_COND2 + ? C_O1_I4(r, r, ri, rI, 0) + : C_O1_I4(r, r, ri, r, 0)); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - =3D { .args_ct_str =3D { "b", "a", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(b, a, 0, 1, r); + case INDEX_op_mulu2_i64: - { - static const TCGTargetOpDef mul2 - =3D { .args_ct_str =3D { "b", "a", "0", "r" } }; - return &mul2; - } + return C_O2_I2(b, a, 0, r); =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, ri, r) + : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, rA, r) + : C_O2_I4(r, r, 0, 1, r, r)); =20 default: - break; + g_assert_not_reached(); } - return NULL; } =20 static void query_s390_facilities(void) --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608704374; cv=none; d=zohomail.com; s=zohoarc; b=WYJgX4bIFvzMtGYEPt9FmuNnqWlxXTT4DFEi7U6aeXDymF6Yh+4T0dyabMnM+Zwt27sid8pJw3L0BJMmg71LAik7d3I4f2N47v/Hwbc8a2741dIW6dlGElyDQZgOgIWii/j+5BL/ChQgivxJ3kQtYXoy3HfK9t3b+YJEMyHhRHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608704374; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i8gt3VnD/hjlZ07ZVemULHRXuFsYp1d7hadsdqF1IbM=; b=km6DDxwJSHjWbvF6+9SexH5Je6TyRFEQ3e9WYEyMqqcV69xdyFwW56xAXBFTOsY0W7AvaLTFV0YA1XlJ/KZGYfcJpiV3k0EThTVxC/PUx3EWXNv6Jv0U0nlYUWowePA1OqrxcWcNbGgEyBA1ZX0C6dtNIdwDNIrkRM3RayGQu8U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608704374656676.9721050018895; Tue, 22 Dec 2020 22:19:34 -0800 (PST) Received: from localhost ([::1]:60326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxUj-0007on-Cm for importer@patchew.org; Wed, 23 Dec 2020 01:19:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEW-00006U-Em for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:48 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:36705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEG-0000RC-Dt for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:48 -0500 Received: by mail-pj1-x102d.google.com with SMTP id l23so2621728pjg.1 for ; Tue, 22 Dec 2020 22:02:31 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target-conset.h | 27 +++++++++++++ tcg/sparc/tcg-target.h | 1 + tcg/sparc/tcg-target.c.inc | 75 +++++++++++------------------------ 3 files changed, 51 insertions(+), 52 deletions(-) create mode 100644 tcg/sparc/tcg-target-conset.h diff --git a/tcg/sparc/tcg-target-conset.h b/tcg/sparc/tcg-target-conset.h new file mode 100644 index 0000000000..fe7324af9a --- /dev/null +++ b/tcg/sparc/tcg-target-conset.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Sparc target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(RZ, r) +C_O0_I2(rZ, rJ) +C_O0_I2(RZ, RJ) +C_O0_I2(sZ, A) +C_O0_I2(SZ, A) +C_O1_I1(r, A) +C_O1_I1(R, A) +C_O1_I1(r, r) +C_O1_I1(r, R) +C_O1_I1(R, r) +C_O1_I1(R, R) +C_O1_I2(R, R, R) +C_O1_I2(r, rZ, rJ) +C_O1_I2(R, RZ, RJ) +C_O1_I4(r, rZ, rJ, rI, 0) +C_O1_I4(R, RZ, RJ, RI, 0) +C_O2_I2(r, r, rZ, rJ) +C_O2_I4(R, R, RZ, RZ, RJ, RI) +C_O2_I4(r, r, rZ, rZ, rJ, rJ) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 633841ebf2..1304c225b1 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,5 +179,6 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index c92742aaec..c225bdd7bd 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1555,40 +1555,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef R_r =3D { .args_ct_str =3D { "R", "r" } }; - static const TCGTargetOpDef r_R =3D { .args_ct_str =3D { "r", "R" } }; - static const TCGTargetOpDef R_R =3D { .args_ct_str =3D { "R", "R" } }; - static const TCGTargetOpDef r_A =3D { .args_ct_str =3D { "r", "A" } }; - static const TCGTargetOpDef R_A =3D { .args_ct_str =3D { "R", "A" } }; - static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef RZ_r =3D { .args_ct_str =3D { "RZ", "r" } = }; - static const TCGTargetOpDef sZ_A =3D { .args_ct_str =3D { "sZ", "A" } = }; - static const TCGTargetOpDef SZ_A =3D { .args_ct_str =3D { "SZ", "A" } = }; - static const TCGTargetOpDef rZ_rJ =3D { .args_ct_str =3D { "rZ", "rJ" = } }; - static const TCGTargetOpDef RZ_RJ =3D { .args_ct_str =3D { "RZ", "RJ" = } }; - static const TCGTargetOpDef R_R_R =3D { .args_ct_str =3D { "R", "R", "= R" } }; - static const TCGTargetOpDef r_rZ_rJ - =3D { .args_ct_str =3D { "r", "rZ", "rJ" } }; - static const TCGTargetOpDef R_RZ_RJ - =3D { .args_ct_str =3D { "R", "RZ", "RJ" } }; - static const TCGTargetOpDef r_r_rZ_rJ - =3D { .args_ct_str =3D { "r", "r", "rZ", "rJ" } }; - static const TCGTargetOpDef movc_32 - =3D { .args_ct_str =3D { "r", "rZ", "rJ", "rI", "0" } }; - static const TCGTargetOpDef movc_64 - =3D { .args_ct_str =3D { "R", "RZ", "RJ", "RI", "0" } }; - static const TCGTargetOpDef add2_32 - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; - static const TCGTargetOpDef add2_64 - =3D { .args_ct_str =3D { "R", "R", "RZ", "RZ", "RJ", "RI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1597,12 +1568,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ld_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: case INDEX_op_st_i32: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_mul_i32: @@ -1618,18 +1589,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_setcond_i32: - return &r_rZ_rJ; + return C_O1_I2(r, rZ, rJ); =20 case INDEX_op_brcond_i32: - return &rZ_rJ; + return C_O0_I2(rZ, rJ); case INDEX_op_movcond_i32: - return &movc_32; + return C_O1_I4(r, rZ, rJ, rI, 0); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2_32; + return C_O2_I4(r, r, rZ, rZ, rJ, rJ); case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_rZ_rJ; + return C_O2_I2(r, r, rZ, rJ); =20 case INDEX_op_ld8u_i64: case INDEX_op_ld8s_i64: @@ -1640,13 +1611,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ld_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: - return &R_r; + return C_O1_I1(R, r); =20 case INDEX_op_st8_i64: case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &RZ_r; + return C_O0_I2(RZ, r); =20 case INDEX_op_add_i64: case INDEX_op_mul_i64: @@ -1662,39 +1633,39 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i64: case INDEX_op_setcond_i64: - return &R_RZ_RJ; + return C_O1_I2(R, RZ, RJ); =20 case INDEX_op_neg_i64: case INDEX_op_not_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: - return &R_R; + return C_O1_I1(R, R); =20 case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - return &r_R; + return C_O1_I1(r, R); =20 case INDEX_op_brcond_i64: - return &RZ_RJ; + return C_O0_I2(RZ, RJ); case INDEX_op_movcond_i64: - return &movc_64; + return C_O1_I4(R, RZ, RJ, RI, 0); case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return &add2_64; + return C_O2_I4(R, R, RZ, RZ, RJ, RI); case INDEX_op_muluh_i64: - return &R_R_R; + return C_O1_I2(R, R, R); =20 case INDEX_op_qemu_ld_i32: - return &r_A; + return C_O1_I1(r, A); case INDEX_op_qemu_ld_i64: - return &R_A; + return C_O1_I1(R, A); case INDEX_op_qemu_st_i32: - return &sZ_A; + return C_O0_I2(sZ, A); case INDEX_op_qemu_st_i64: - return &SZ_A; + return C_O0_I2(SZ, A); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LM+ixEH8S5xhbIyjTdMFVRGEOmMUxSrxvI2DWExWedA=; b=hzl6wnpeD1h72Bx5n0AVg00ZMZoSY/hiK6KnZGC9AMUk1v66ckEOnxY9lVWgPT4lJT 2ViqDKRZNsL0RdWQ5xRZpYnjemKqchP84zuMaYRn56EaP43VPz1cHxpJ6Tu6p5gS5mzN ysIR5l5AKC4pEljeipPnqxxwzzNdaVFoChy//HS/hDQfrBTNW+y75VqO5IVXrS+ycs5U csmP5yuK+d+X1q6QinO/A3EjvujIZCyoXAKWgphiksGx24cDiI8LOTetZs2QxdjPM5Ed bGCNd3sQDJZ/+SeV1JFmmn708IoJMszS74wWiTdXnwRwMZjng9JsMLCBebLhTIvFSq9Z 4ljA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LM+ixEH8S5xhbIyjTdMFVRGEOmMUxSrxvI2DWExWedA=; b=IggJHKfpwptbaZjGvYRonkua/a9y9ECOjxHxqasjE8Wm0Wms8aEpi2H3fNjlbJKO+J IU6CTFq/lbGH9+5zn3cuDBv9hXL5BVR7KToTymx8Ukoj4vR/3mdSnpUACtSotKwdTNR8 dOWoK5XUEQLX5PEsO58yKPE1FeDVi94e+NfgNgqtlf7V2CHKacPzArOnArqfS3benQry k9hQNyJa1/rdATKgT9+xiYH9JZkwjpreoohq00XaDA13herGBYeSkgtr5dI9obPj4Bn9 opSe/wTA8Rc6s0XZlBnS/1j0oOZ699CkWOipPCb/KS/CpzV3Z5IzmCpKocaefWZH8eqi bqxg== X-Gm-Message-State: AOAM53369zgdZbospkgZQ41+EDnNiZ1ZvTk6hcM12x7aKYvUlxA/vB42 O9phD9xuEKyZ4YCh1LZx5SQ94lbTYI/iFA== X-Google-Smtp-Source: ABdhPJyFxTmqKMU7/wCeI0+hNBB+3nEbhMBSIA7oS0JkBglQZ6HrrR9RUp+HgOlY1ss1VCe/Pc+Bow== X-Received: by 2002:a62:8f0e:0:b029:1aa:1268:fa4e with SMTP id n14-20020a628f0e0000b02901aa1268fa4emr22738274pfd.18.1608703351723; Tue, 22 Dec 2020 22:02:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/22] tcg/tci: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:02:03 -0800 Message-Id: <20201223060204.576856-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This does require finishing the conversion to tcg_target_op_def. Remove quite a lot of ifdefs, since we can reference opcodes even if they are not implemented. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-conset.h | 20 +++ tcg/tci/tcg-target.h | 2 + tcg/tci/tcg-target.c.inc | 343 +++++++++++++----------------------- 3 files changed, 147 insertions(+), 218 deletions(-) create mode 100644 tcg/tci/tcg-target-conset.h diff --git a/tcg/tci/tcg-target-conset.h b/tcg/tci/tcg-target-conset.h new file mode 100644 index 0000000000..efcefab37e --- /dev/null +++ b/tcg/tci/tcg-target-conset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +/* + * TCI target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I3(r, r, r) +C_O0_I4(r, r, ri, ri) +C_O0_I4(r, r, r, r) +C_O1_I1(r, r) +C_O1_I2(r, 0, r) +C_O1_I2(r, ri, ri) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8c1c1d265d..42b84a0e87 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,4 +210,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, /* no need to flush icache explicitly */ } =20 +#define TCG_TARGET_CONSET_H + #endif /* TCG_TARGET_H */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 9ac6da2e21..f9fb6cb399 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -37,236 +37,143 @@ /* Bitfield n...m (in 32 bit value). */ #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) =20 -/* Macros used in tcg_target_op_defs. */ -#define R "r" -#define RI "ri" -#if TCG_TARGET_REG_BITS =3D=3D 32 -# define R64 "r", "r" -#else -# define R64 "r" -#endif -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "r", "r" -# define S "r", "r" -#else -# define L "r" -# define S "r" -#endif +static int tcg_target_op_def(TCGOpcode op) +{ + switch (op) { + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + return C_O1_I1(r, r); =20 -/* TODO: documentation. */ -static const TCGTargetOpDef tcg_target_op_defs[] =3D { - { INDEX_op_exit_tb, { NULL } }, - { INDEX_op_goto_tb, { NULL } }, - { INDEX_op_br, { NULL } }, + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); =20 - { INDEX_op_ld8u_i32, { R, R } }, - { INDEX_op_ld8s_i32, { R, R } }, - { INDEX_op_ld16u_i32, { R, R } }, - { INDEX_op_ld16s_i32, { R, R } }, - { INDEX_op_ld_i32, { R, R } }, - { INDEX_op_st8_i32, { R, R } }, - { INDEX_op_st16_i32, { R, R } }, - { INDEX_op_st_i32, { R, R } }, + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + return C_O1_I2(r, r, r); =20 - { INDEX_op_add_i32, { R, RI, RI } }, - { INDEX_op_sub_i32, { R, RI, RI } }, - { INDEX_op_mul_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i32 - { INDEX_op_div_i32, { R, R, R } }, - { INDEX_op_divu_i32, { R, R, R } }, - { INDEX_op_rem_i32, { R, R, R } }, - { INDEX_op_remu_i32, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i32 - { INDEX_op_div2_i32, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i32, { R, R, "0", "1", R } }, -#endif - /* TODO: Does R, RI, RI result in faster code than R, R, RI? - If both operands are constants, we can optimize. */ - { INDEX_op_and_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i32 - { INDEX_op_andc_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i32 - { INDEX_op_eqv_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i32 - { INDEX_op_nand_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i32 - { INDEX_op_nor_i32, { R, RI, RI } }, -#endif - { INDEX_op_or_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i32 - { INDEX_op_orc_i32, { R, RI, RI } }, -#endif - { INDEX_op_xor_i32, { R, RI, RI } }, - { INDEX_op_shl_i32, { R, RI, RI } }, - { INDEX_op_shr_i32, { R, RI, RI } }, - { INDEX_op_sar_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i32 - { INDEX_op_rotl_i32, { R, RI, RI } }, - { INDEX_op_rotr_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i32 - { INDEX_op_deposit_i32, { R, "0", R } }, -#endif + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + /* TODO: Does R, RI, RI result in faster code than R, R, RI? */ + return C_O1_I2(r, ri, ri); =20 - { INDEX_op_brcond_i32, { R, RI } }, + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return C_O1_I2(r, 0, r); =20 - { INDEX_op_setcond_i32, { R, R, RI } }, -#if TCG_TARGET_REG_BITS =3D=3D 64 - { INDEX_op_setcond_i64, { R, R, RI } }, -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return C_O0_I2(r, ri); + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ - { INDEX_op_add2_i32, { R, R, R, R, R, R } }, - { INDEX_op_sub2_i32, { R, R, R, R, R, R } }, - { INDEX_op_brcond2_i32, { R, R, RI, RI } }, - { INDEX_op_mulu2_i32, { R, R, R, R } }, - { INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return C_O2_I4(r, r, r, r, r, r); + case INDEX_op_brcond2_i32: + return C_O0_I4(r, r, ri, ri); + case INDEX_op_mulu2_i32: + return C_O2_I2(r, r, r, r); + case INDEX_op_setcond2_i32 + return C_O1_I4(r, r, r, ri, ri); #endif =20 -#if TCG_TARGET_HAS_not_i32 - { INDEX_op_not_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i32 - { INDEX_op_neg_i32, { R, R } }, -#endif + case INDEX_op_qemu_ld_i32: + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r= , r) + : C_O2_I2(r, r, r, r)); + case INDEX_op_qemu_st_i32: + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(r, r= , r) + : C_O0_I4(r, r, r, r)); =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 - { INDEX_op_ld8u_i64, { R, R } }, - { INDEX_op_ld8s_i64, { R, R } }, - { INDEX_op_ld16u_i64, { R, R } }, - { INDEX_op_ld16s_i64, { R, R } }, - { INDEX_op_ld32u_i64, { R, R } }, - { INDEX_op_ld32s_i64, { R, R } }, - { INDEX_op_ld_i64, { R, R } }, - - { INDEX_op_st8_i64, { R, R } }, - { INDEX_op_st16_i64, { R, R } }, - { INDEX_op_st32_i64, { R, R } }, - { INDEX_op_st_i64, { R, R } }, - - { INDEX_op_add_i64, { R, RI, RI } }, - { INDEX_op_sub_i64, { R, RI, RI } }, - { INDEX_op_mul_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i64 - { INDEX_op_div_i64, { R, R, R } }, - { INDEX_op_divu_i64, { R, R, R } }, - { INDEX_op_rem_i64, { R, R, R } }, - { INDEX_op_remu_i64, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i64 - { INDEX_op_div2_i64, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i64, { R, R, "0", "1", R } }, -#endif - { INDEX_op_and_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i64 - { INDEX_op_andc_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i64 - { INDEX_op_eqv_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i64 - { INDEX_op_nand_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i64 - { INDEX_op_nor_i64, { R, RI, RI } }, -#endif - { INDEX_op_or_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i64 - { INDEX_op_orc_i64, { R, RI, RI } }, -#endif - { INDEX_op_xor_i64, { R, RI, RI } }, - { INDEX_op_shl_i64, { R, RI, RI } }, - { INDEX_op_shr_i64, { R, RI, RI } }, - { INDEX_op_sar_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i64 - { INDEX_op_rotl_i64, { R, RI, RI } }, - { INDEX_op_rotr_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i64 - { INDEX_op_deposit_i64, { R, "0", R } }, -#endif - { INDEX_op_brcond_i64, { R, RI } }, - -#if TCG_TARGET_HAS_ext8s_i64 - { INDEX_op_ext8s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i64 - { INDEX_op_ext16s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32s_i64 - { INDEX_op_ext32s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i64 - { INDEX_op_ext8u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i64 - { INDEX_op_ext16u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32u_i64 - { INDEX_op_ext32u_i64, { R, R } }, -#endif - { INDEX_op_ext_i32_i64, { R, R } }, - { INDEX_op_extu_i32_i64, { R, R } }, -#if TCG_TARGET_HAS_bswap16_i64 - { INDEX_op_bswap16_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i64 - { INDEX_op_bswap32_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap64_i64 - { INDEX_op_bswap64_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_not_i64 - { INDEX_op_not_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i64 - { INDEX_op_neg_i64, { R, R } }, -#endif -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ - - { INDEX_op_qemu_ld_i32, { R, L } }, - { INDEX_op_qemu_ld_i64, { R64, L } }, - - { INDEX_op_qemu_st_i32, { R, S } }, - { INDEX_op_qemu_st_i64, { R64, S } }, - -#if TCG_TARGET_HAS_ext8s_i32 - { INDEX_op_ext8s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i32 - { INDEX_op_ext16s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i32 - { INDEX_op_ext8u_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i32 - { INDEX_op_ext16u_i32, { R, R } }, -#endif - -#if TCG_TARGET_HAS_bswap16_i32 - { INDEX_op_bswap16_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i32 - { INDEX_op_bswap32_i32, { R, R } }, -#endif - - { INDEX_op_mb, { } }, - { -1 }, -}; - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - int i, n =3D ARRAY_SIZE(tcg_target_op_defs); - - for (i =3D 0; i < n; ++i) { - if (tcg_target_op_defs[i].op =3D=3D op) { - return &tcg_target_op_defs[i]; - } + default: + g_assert_not_reached(); } - return NULL; } =20 static const int tcg_target_reg_alloc_order[] =3D { --=20 2.25.1 From nobody Mon Feb 9 13:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608705041; cv=none; d=zohomail.com; s=zohoarc; b=MwlkQJNiUs050d/2n+njwJrP45hs7Fx/lGJrDYglMgA6iCIxNA1bMsOSaNiipeBUhjvbE5AVijEo0AmbXSN2TQR3JH4xrG234uvctHjuLCY2meTXxUBiuuXCApkOqR7vQnzREEhx+B7tBil0UX/LGpZd5UT9XTHQvNqQDYcbWc4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nk60H3yRhOTIra88/cLIs2xseWbxfALm0i3pKXgYJOM=; b=CJ1TSbySDLhtl/YbmGtWQfFNI9ZnElrA0jkVVcP1qZ9CDt6rrXkkB4CtWYDh8jI4b2 JSbzQnGMZMgK3PxOLxzmC04Ywzo5z7/Td+y85iFUGcgNlhebGN0GyLis5hc4VXbWYwho J3uR2/OXtBLNGsmp3lHvUMP4z//5lH1cg+3hxk0c46/ogBDW0H3cSc7Qw8HUg7Jt1HfK 42pOOq87CyvZQ0+EKJ8Nuwek+D3PHiYGxwvUQMJU1YeyttLLw2lML10lFIfyUlracgLX CjNJJjCETimU7BB3wnL9SSIofM33Aqm9XLPlbFd9dWPgVCd7wB+SaEWKY7DCtmG8XoKx UqEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nk60H3yRhOTIra88/cLIs2xseWbxfALm0i3pKXgYJOM=; b=YJdsiPtATwcy9UY1jii4PgphoU3PyacRIKdgnI7NzXdNRGaRzbxMKZ3JHDO/PW/ea6 KFn56gp2W/fIGZjPmpRxMuOT3r56qFgzt4zpL2XkzmfJk9pfv8Wq4xWzYN23pNuvIP72 L8Srp1qm4eJz5Lp9Hl8i1mj7+m0qbIPlMThMVCt72P8hNp2P6w9NofEVbmtPkOxM5KnD yChU3dxr9Kx6uHGkFbqMT0dfAg2jHJjXsEF3BBnYTtoJy1DUCvVM52MTd0wz/CmLTfRx Xgnb+Zrwn02uyCwUIqxkM3QErNuR11dCnlRkEGOCyDwYB7YfA8UT/G11OLLfIZLRx4Ze kA/A== X-Gm-Message-State: AOAM5314/RnjVgZ3lXKQWX1nEMefgaxh/c+fQDRnB1Ft/m3NUwpb/vH8 jZReb/tK+g4QUMg0UqYp/QYRT1b3In2mug== X-Google-Smtp-Source: ABdhPJzk8m1ussJ2yCNVl5DAVV0C2AfGUhfDfUF4aJfB2vM4jX6NzJnWbwU8Hhjuevb4VIMy0KfZPg== X-Received: by 2002:a17:90b:4d0e:: with SMTP id mw14mr25494265pjb.92.1608703352954; Tue, 22 Dec 2020 22:02:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H Date: Tue, 22 Dec 2020 22:02:04 -0800 Message-Id: <20201223060204.576856-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All backends have now been converted to tcg-target-conset.h, so we can remove the fallback code. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 2 -- tcg/tcg.c | 13 ------------- 10 files changed, 23 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index a81f6dadf9..663dd0b95e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 918f09239a..17e771374d 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 74a2566900..abd4ac7fc0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 688d691cda..c6b091d849 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif -#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c958faffb7..be10363956 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index a357962e01..032439d806 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 78277a8d07..63c8797bd3 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 1304c225b1..633841ebf2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H =20 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 42b84a0e87..8c1c1d265d 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, /* no need to flush icache explicitly */ } =20 -#define TCG_TARGET_CONSET_H - #endif /* TCG_TARGET_H */ diff --git a/tcg/tcg.c b/tcg/tcg.c index c58d728ca5..dd5b045d88 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -68,11 +68,7 @@ /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); -#ifdef TCG_TARGET_CONSET_H static int tcg_target_op_def(TCGOpcode); -#else -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); -#endif static void tcg_target_qemu_prologue(TCGContext *s); static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); @@ -344,7 +340,6 @@ static void set_jmp_reset_offset(TCGContext *s, int whi= ch) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 -#ifdef TCG_TARGET_CONSET_H #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -457,8 +452,6 @@ static const TCGTargetOpDef constraint_sets[] =3D { #define C_O2_I4(O1, O2, I1, I2, I3, I4) \ C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) =20 -#endif /* TCG_TARGET_CONSET_H */ - #include "tcg-target.c.inc" =20 /* compare a pointer @ptr and a tb_tc @s */ @@ -2367,16 +2360,10 @@ static void process_op_defs(TCGContext *s) continue; } =20 -#ifdef TCG_TARGET_CONSET_H i =3D tcg_target_op_def(op); /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(i >=3D 0 && i < ARRAY_SIZE(constraint_sets)); tdefs =3D &constraint_sets[i]; -#else - tdefs =3D tcg_target_op_def(op); - /* Missing TCGTargetOpDef entry. */ - tcg_debug_assert(tdefs !=3D NULL); -#endif =20 for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; --=20 2.25.1